^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * GSPCA sub driver for W996[78]CF JPEG USB Dual Mode Camera Chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 Hans de Goede <hdegoede@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This module is adapted from the in kernel v4l1 w9968cf driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2002-2004 by Luca Risolia <luca.risolia@studio.unibo.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Note this is not a stand alone driver, it gets included in ov519.c, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) is a bit of a hack, but it needs the driver code for a lot of different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ov sensors which is already present in ov519.c (the old v4l1 driver used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) the ovchipcam framework). When we have the time we really should move
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) the sensor drivers to v4l2 sub drivers, and properly split of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) driver from ov519.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define W9968CF_I2C_BUS_DELAY 4 /* delay in us for I2C bit r/w operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define Y_QUANTABLE (&sd->jpeg_hdr[JPEG_QT0_OFFSET])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UV_QUANTABLE (&sd->jpeg_hdr[JPEG_QT1_OFFSET])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const struct v4l2_pix_format w9968cf_vga_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {160, 120, V4L2_PIX_FMT_UYVY, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .bytesperline = 160 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .sizeimage = 160 * 120 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .colorspace = V4L2_COLORSPACE_JPEG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {176, 144, V4L2_PIX_FMT_UYVY, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .bytesperline = 176 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .sizeimage = 176 * 144 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .colorspace = V4L2_COLORSPACE_JPEG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .bytesperline = 320 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .sizeimage = 320 * 240 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .colorspace = V4L2_COLORSPACE_JPEG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .bytesperline = 352 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .sizeimage = 352 * 288 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .colorspace = V4L2_COLORSPACE_JPEG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .bytesperline = 640 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .sizeimage = 640 * 480 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .colorspace = V4L2_COLORSPACE_JPEG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void reg_w(struct sd *sd, u16 index, u16 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*--------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Write 64-bit data to the fast serial bus registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) Return 0 on success, -1 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) --------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void w9968cf_write_fsb(struct sd *sd, u16* data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct usb_device *udev = sd->gspca_dev.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (sd->gspca_dev.usb_err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) value = *data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) memcpy(sd->gspca_dev.usb_buf, data, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Avoid things going to fast for the bridge with a xhci host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) USB_TYPE_VENDOR | USB_DIR_OUT | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) value, 0x06, sd->gspca_dev.usb_buf, 6, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pr_err("Write FSB registers failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) sd->gspca_dev.usb_err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*--------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) Write data to the serial bus control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) Return 0 on success, a negative number otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) --------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void w9968cf_write_sb(struct sd *sd, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (sd->gspca_dev.usb_err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Avoid things going to fast for the bridge with a xhci host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* We don't use reg_w here, as that would cause all writes when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bitbanging i2c to be logged, making the logs impossible to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = usb_control_msg(sd->gspca_dev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) usb_sndctrlpipe(sd->gspca_dev.dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) value, 0x01, NULL, 0, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) udelay(W9968CF_I2C_BUS_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pr_err("Write SB reg [01] %04x failed\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) sd->gspca_dev.usb_err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*--------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Read data from the serial bus control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) Return 0 on success, a negative number otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) --------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int w9968cf_read_sb(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (sd->gspca_dev.usb_err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Avoid things going to fast for the bridge with a xhci host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* We don't use reg_r here, as the w9968cf is special and has 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bit registers instead of 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = usb_control_msg(sd->gspca_dev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0, 0x01, sd->gspca_dev.usb_buf, 2, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = sd->gspca_dev.usb_buf[0] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) (sd->gspca_dev.usb_buf[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pr_err("Read SB reg [01] failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) sd->gspca_dev.usb_err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Make sure the buffer is zeroed to avoid uninitialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) memset(sd->gspca_dev.usb_buf, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) udelay(W9968CF_I2C_BUS_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*--------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) Upload quantization tables for the JPEG compression.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) This function is called by w9968cf_start_transfer().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) Return 0 on success, a negative number otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) --------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void w9968cf_upload_quantizationtables(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u16 a, b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) reg_w(sd, 0x39, 0x0010); /* JPEG clock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) for (i = 0, j = 0; i < 32; i++, j += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) a = Y_QUANTABLE[j] | ((unsigned)(Y_QUANTABLE[j + 1]) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) b = UV_QUANTABLE[j] | ((unsigned)(UV_QUANTABLE[j + 1]) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) reg_w(sd, 0x40 + i, a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) reg_w(sd, 0x60 + i, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) reg_w(sd, 0x39, 0x0012); /* JPEG encoder enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Low-level I2C I/O functions. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * The adapter supports the following I2C transfer functions: *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * i2c_adap_fastwrite_byte_data() (at 400 kHz bit frequency only) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * i2c_adap_read_byte_data() *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * i2c_adap_read_byte() *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void w9968cf_smbus_start(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) w9968cf_write_sb(sd, 0x0011); /* SDE=1, SDA=0, SCL=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) w9968cf_write_sb(sd, 0x0010); /* SDE=1, SDA=0, SCL=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void w9968cf_smbus_stop(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) w9968cf_write_sb(sd, 0x0010); /* SDE=1, SDA=0, SCL=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) w9968cf_write_sb(sd, 0x0011); /* SDE=1, SDA=0, SCL=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) w9968cf_write_sb(sd, 0x0013); /* SDE=1, SDA=1, SCL=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void w9968cf_smbus_write_byte(struct sd *sd, u8 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int sda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (bit = 0 ; bit < 8 ; bit++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sda = (v & 0x80) ? 2 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) v <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* SDE=1, SDA=sda, SCL=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) w9968cf_write_sb(sd, 0x10 | sda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* SDE=1, SDA=sda, SCL=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) w9968cf_write_sb(sd, 0x11 | sda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* SDE=1, SDA=sda, SCL=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) w9968cf_write_sb(sd, 0x10 | sda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void w9968cf_smbus_read_byte(struct sd *sd, u8 *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* No need to ensure SDA is high as we are always called after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) read_ack which ends with SDA high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) for (bit = 0 ; bit < 8 ; bit++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *v <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* SDE=1, SDA=1, SCL=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) w9968cf_write_sb(sd, 0x0013);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *v |= (w9968cf_read_sb(sd) & 0x0008) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* SDE=1, SDA=1, SCL=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) w9968cf_write_sb(sd, 0x0012);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void w9968cf_smbus_write_nack(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* No need to ensure SDA is high as we are always called after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) read_byte which ends with SDA high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) w9968cf_write_sb(sd, 0x0013); /* SDE=1, SDA=1, SCL=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) w9968cf_write_sb(sd, 0x0012); /* SDE=1, SDA=1, SCL=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void w9968cf_smbus_read_ack(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int sda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Ensure SDA is high before raising clock to avoid a spurious stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) w9968cf_write_sb(sd, 0x0012); /* SDE=1, SDA=1, SCL=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) w9968cf_write_sb(sd, 0x0013); /* SDE=1, SDA=1, SCL=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) sda = w9968cf_read_sb(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) w9968cf_write_sb(sd, 0x0012); /* SDE=1, SDA=1, SCL=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (sda >= 0 && (sda & 0x08)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) gspca_dbg(gspca_dev, D_USBI, "Did not receive i2c ACK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) sd->gspca_dev.usb_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* SMBus protocol: S Addr Wr [A] Subaddr [A] Value [A] P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void w9968cf_i2c_w(struct sd *sd, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u16* data = (u16 *)sd->gspca_dev.usb_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) data[0] = 0x082f | ((sd->sensor_addr & 0x80) ? 0x1500 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) data[0] |= (sd->sensor_addr & 0x40) ? 0x4000 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) data[1] = 0x2082 | ((sd->sensor_addr & 0x40) ? 0x0005 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) data[1] |= (sd->sensor_addr & 0x20) ? 0x0150 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) data[1] |= (sd->sensor_addr & 0x10) ? 0x5400 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) data[2] = 0x8208 | ((sd->sensor_addr & 0x08) ? 0x0015 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) data[2] |= (sd->sensor_addr & 0x04) ? 0x0540 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) data[2] |= (sd->sensor_addr & 0x02) ? 0x5000 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) data[3] = 0x1d20 | ((sd->sensor_addr & 0x02) ? 0x0001 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) data[3] |= (sd->sensor_addr & 0x01) ? 0x0054 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) w9968cf_write_fsb(sd, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) data[0] = 0x8208 | ((reg & 0x80) ? 0x0015 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) data[0] |= (reg & 0x40) ? 0x0540 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) data[0] |= (reg & 0x20) ? 0x5000 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) data[1] = 0x0820 | ((reg & 0x20) ? 0x0001 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) data[1] |= (reg & 0x10) ? 0x0054 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) data[1] |= (reg & 0x08) ? 0x1500 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) data[1] |= (reg & 0x04) ? 0x4000 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) data[2] = 0x2082 | ((reg & 0x04) ? 0x0005 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) data[2] |= (reg & 0x02) ? 0x0150 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) data[2] |= (reg & 0x01) ? 0x5400 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) data[3] = 0x001d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) w9968cf_write_fsb(sd, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) data[0] = 0x8208 | ((value & 0x80) ? 0x0015 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) data[0] |= (value & 0x40) ? 0x0540 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) data[0] |= (value & 0x20) ? 0x5000 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) data[1] = 0x0820 | ((value & 0x20) ? 0x0001 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) data[1] |= (value & 0x10) ? 0x0054 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) data[1] |= (value & 0x08) ? 0x1500 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) data[1] |= (value & 0x04) ? 0x4000 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) data[2] = 0x2082 | ((value & 0x04) ? 0x0005 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) data[2] |= (value & 0x02) ? 0x0150 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) data[2] |= (value & 0x01) ? 0x5400 : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) data[3] = 0xfe1d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) w9968cf_write_fsb(sd, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) gspca_dbg(gspca_dev, D_USBO, "i2c 0x%02x -> [0x%02x]\n", value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* SMBus protocol: S Addr Wr [A] Subaddr [A] P S Addr+1 Rd [A] [Value] NA P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int w9968cf_i2c_r(struct sd *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Fast serial bus data control disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) w9968cf_write_sb(sd, 0x0013); /* don't change ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) w9968cf_smbus_start(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) w9968cf_smbus_write_byte(sd, sd->sensor_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) w9968cf_smbus_read_ack(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) w9968cf_smbus_write_byte(sd, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) w9968cf_smbus_read_ack(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) w9968cf_smbus_stop(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) w9968cf_smbus_start(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) w9968cf_smbus_write_byte(sd, sd->sensor_addr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) w9968cf_smbus_read_ack(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) w9968cf_smbus_read_byte(sd, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* signal we don't want to read anymore, the v4l1 driver used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) send an ack here which is very wrong! (and then fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) the issues this gave by retrying reads) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) w9968cf_smbus_write_nack(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) w9968cf_smbus_stop(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Fast serial bus data control re-enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) w9968cf_write_sb(sd, 0x0030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (sd->gspca_dev.usb_err >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) gspca_dbg(gspca_dev, D_USBI, "i2c [0x%02X] -> 0x%02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) gspca_err(gspca_dev, "i2c read [0x%02x] failed\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*--------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) Turn on the LED on some webcams. A beep should be heard too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) Return 0 on success, a negative number otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) --------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void w9968cf_configure(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) reg_w(sd, 0x00, 0xff00); /* power-down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) reg_w(sd, 0x00, 0xbf17); /* reset everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) reg_w(sd, 0x00, 0xbf10); /* normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) reg_w(sd, 0x01, 0x0010); /* serial bus, SDS high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) reg_w(sd, 0x01, 0x0000); /* serial bus, SDS low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) reg_w(sd, 0x01, 0x0010); /* ..high 'beep-beep' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) reg_w(sd, 0x01, 0x0030); /* Set sda scl to FSB mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) sd->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void w9968cf_init(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned long hw_bufsize = sd->sif ? (352 * 288 * 2) : (640 * 480 * 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) y0 = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u0 = y0 + hw_bufsize / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) v0 = u0 + hw_bufsize / 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) y1 = v0 + hw_bufsize / 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u1 = y1 + hw_bufsize / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) v1 = u1 + hw_bufsize / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) reg_w(sd, 0x00, 0xff00); /* power off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) reg_w(sd, 0x00, 0xbf10); /* power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) reg_w(sd, 0x03, 0x405d); /* DRAM timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) reg_w(sd, 0x04, 0x0030); /* SDRAM timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) reg_w(sd, 0x20, y0 & 0xffff); /* Y buf.0, low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) reg_w(sd, 0x21, y0 >> 16); /* Y buf.0, high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) reg_w(sd, 0x24, u0 & 0xffff); /* U buf.0, low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) reg_w(sd, 0x25, u0 >> 16); /* U buf.0, high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) reg_w(sd, 0x28, v0 & 0xffff); /* V buf.0, low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) reg_w(sd, 0x29, v0 >> 16); /* V buf.0, high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) reg_w(sd, 0x22, y1 & 0xffff); /* Y buf.1, low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) reg_w(sd, 0x23, y1 >> 16); /* Y buf.1, high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) reg_w(sd, 0x26, u1 & 0xffff); /* U buf.1, low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) reg_w(sd, 0x27, u1 >> 16); /* U buf.1, high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) reg_w(sd, 0x2a, v1 & 0xffff); /* V buf.1, low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) reg_w(sd, 0x2b, v1 >> 16); /* V buf.1, high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) reg_w(sd, 0x32, y1 & 0xffff); /* JPEG buf 0 low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) reg_w(sd, 0x33, y1 >> 16); /* JPEG buf 0 high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) reg_w(sd, 0x34, y1 & 0xffff); /* JPEG buf 1 low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) reg_w(sd, 0x35, y1 >> 16); /* JPEG bug 1 high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) reg_w(sd, 0x36, 0x0000);/* JPEG restart interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) reg_w(sd, 0x37, 0x0804);/*JPEG VLE FIFO threshold*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) reg_w(sd, 0x38, 0x0000);/* disable hw up-scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) reg_w(sd, 0x3f, 0x0000); /* JPEG/MCTL test data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static void w9968cf_set_crop_window(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int start_cropx, start_cropy, x, y, fw, fh, cw, ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) max_width, max_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (sd->sif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) max_width = 352;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) max_height = 288;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) max_width = 640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) max_height = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (sd->sensor == SEN_OV7620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Sigh, this is dependend on the clock / framerate changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * made by the frequency control, sick.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Note we cannot use v4l2_ctrl_g_ctrl here, as we get called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * from ov519.c:setfreq() with the ctrl lock held!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (sd->freq->val == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) start_cropx = 277;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) start_cropy = 37;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) start_cropx = 105;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) start_cropy = 37;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) start_cropx = 320;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) start_cropy = 35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Work around to avoid FP arithmetic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SC(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Scaling factors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) fw = SC(sd->gspca_dev.pixfmt.width) / max_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) fh = SC(sd->gspca_dev.pixfmt.height) / max_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) cw = (fw >= fh) ? max_width : SC(sd->gspca_dev.pixfmt.width) / fh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ch = (fw >= fh) ? SC(sd->gspca_dev.pixfmt.height) / fw : max_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) sd->sensor_width = max_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) sd->sensor_height = max_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) x = (max_width - cw) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) y = (max_height - ch) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) reg_w(sd, 0x10, start_cropx + x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) reg_w(sd, 0x11, start_cropy + y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) reg_w(sd, 0x12, start_cropx + x + cw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) reg_w(sd, 0x13, start_cropy + y + ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static void w9968cf_mode_init_regs(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int val, vs_polarity, hs_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) w9968cf_set_crop_window(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) reg_w(sd, 0x14, sd->gspca_dev.pixfmt.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) reg_w(sd, 0x15, sd->gspca_dev.pixfmt.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* JPEG width & height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) reg_w(sd, 0x30, sd->gspca_dev.pixfmt.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) reg_w(sd, 0x31, sd->gspca_dev.pixfmt.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Y & UV frame buffer strides (in WORD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (w9968cf_vga_mode[sd->gspca_dev.curr_mode].pixelformat ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) V4L2_PIX_FMT_JPEG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) reg_w(sd, 0x2c, sd->gspca_dev.pixfmt.width / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) reg_w(sd, 0x2d, sd->gspca_dev.pixfmt.width / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) reg_w(sd, 0x2c, sd->gspca_dev.pixfmt.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) reg_w(sd, 0x00, 0xbf17); /* reset everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) reg_w(sd, 0x00, 0xbf10); /* normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Transfer size in WORDS (for UYVY format only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) val = sd->gspca_dev.pixfmt.width * sd->gspca_dev.pixfmt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) reg_w(sd, 0x3d, val & 0xffff); /* low bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) reg_w(sd, 0x3e, val >> 16); /* high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (w9968cf_vga_mode[sd->gspca_dev.curr_mode].pixelformat ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) V4L2_PIX_FMT_JPEG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* We may get called multiple times (usb isoc bw negotiat.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) jpeg_define(sd->jpeg_hdr, sd->gspca_dev.pixfmt.height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) sd->gspca_dev.pixfmt.width, 0x22); /* JPEG 420 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) jpeg_set_qual(sd->jpeg_hdr, v4l2_ctrl_g_ctrl(sd->jpegqual));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) w9968cf_upload_quantizationtables(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) v4l2_ctrl_grab(sd->jpegqual, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Video Capture Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (sd->sensor == SEN_OV7620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Seems to work around a bug in the image sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) vs_polarity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) hs_polarity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) vs_polarity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) hs_polarity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) val = (vs_polarity << 12) | (hs_polarity << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* NOTE: We may not have enough memory to do double buffering while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) doing compression (amount of memory differs per model cam).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) So we use the second image buffer also as jpeg stream buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) (see w9968cf_init), and disable double buffering. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (w9968cf_vga_mode[sd->gspca_dev.curr_mode].pixelformat ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) V4L2_PIX_FMT_JPEG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* val |= 0x0002; YUV422P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) val |= 0x0003; /* YUV420P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) val |= 0x0080; /* Enable HW double buffering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* val |= 0x0020; enable clamping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* val |= 0x0008; enable (1-2-1) filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* val |= 0x000c; enable (2-3-6-3-2) filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) val |= 0x8000; /* capt. enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) reg_w(sd, 0x16, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) sd->gspca_dev.empty_packet = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static void w9968cf_stop0(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) v4l2_ctrl_grab(sd->jpegqual, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) reg_w(sd, 0x39, 0x0000); /* disable JPEG encoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) reg_w(sd, 0x16, 0x0000); /* stop video capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* The w9968cf docs say that a 0 sized packet means EOF (and also SOF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) for the next frame). This seems to simply not be true when operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) in JPEG mode, in this case there may be empty packets within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) frame. So in JPEG mode use the JPEG SOI marker to detect SOF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) Note to make things even more interesting the w9968cf sends *PLANAR* jpeg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) to be precise it sends: SOI, SOF, DRI, SOS, Y-data, SOS, U-data, SOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) V-data, EOI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static void w9968cf_pkt_scan(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u8 *data, /* isoc packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int len) /* iso packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (w9968cf_vga_mode[gspca_dev->curr_mode].pixelformat ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) V4L2_PIX_FMT_JPEG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (len >= 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) data[0] == 0xff &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) data[1] == 0xd8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) gspca_frame_add(gspca_dev, LAST_PACKET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) gspca_frame_add(gspca_dev, FIRST_PACKET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) sd->jpeg_hdr, JPEG_HDR_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Strip the ff d8, our own header (which adds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) huffman and quantization tables) already has this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) len -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) data += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* In UYVY mode an empty packet signals EOF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (gspca_dev->empty_packet) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) gspca_frame_add(gspca_dev, LAST_PACKET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) gspca_frame_add(gspca_dev, FIRST_PACKET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) gspca_dev->empty_packet = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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