Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Quickcam cameras initialization data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * V4L2 by Jean-Francois Moine <http://moinejf.free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define MODULE_NAME "tv8532"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include "gspca.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) MODULE_DESCRIPTION("TV8532 USB Camera Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* specific webcam descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) struct sd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	struct gspca_dev gspca_dev;	/* !! must be the first item */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	__u8 packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static const struct v4l2_pix_format sif_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	{176, 144, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		.bytesperline = 176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		.sizeimage = 176 * 144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		.colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		.priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	{352, 288, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		.bytesperline = 352,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		.sizeimage = 352 * 288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		.colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		.priv = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* TV-8532A (ICM532A) registers (LE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define R00_PART_CONTROL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define		LATENT_CHANGE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define		EXPO_CHANGE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define R01_TIMING_CONTROL_LOW 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define		CMD_EEprom_Open 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define		CMD_EEprom_Close 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define R03_TABLE_ADDR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define R04_WTRAM_DATA_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define R05_WTRAM_DATA_M 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define R06_WTRAM_DATA_H 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define R07_TABLE_LEN	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define R08_RAM_WRITE_ACTION 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define R0C_AD_WIDTHL	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define R0D_AD_WIDTHH	0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define R0E_AD_HEIGHTL	0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define R0F_AD_HEIGHTH	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define R10_AD_COL_BEGINL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define R11_AD_COL_BEGINH 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define		MIRROR		0x04	/* [10] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define R14_AD_ROW_BEGINL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define R15_AD_ROWBEGINH  0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define R1C_AD_EXPOSE_TIMEL 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define R20_GAIN_G1L	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define R21_GAIN_G1H	0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define R22_GAIN_RL	0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define R23_GAIN_RH	0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define R24_GAIN_BL	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define R25_GAIN_BH	0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define R26_GAIN_G2L	0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define R27_GAIN_G2H	0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define R28_QUANT	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define R29_LINE	0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define R2C_POLARITY	0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define R2D_POINT	0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define R2E_POINTH	0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define R2F_POINTB	0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define R30_POINTBH	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define R31_UPD		0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define R2A_HIGH_BUDGET 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define R2B_LOW_BUDGET	0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define R34_VID		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define R35_VIDH	0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define R36_PID		0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define R37_PIDH	0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define R39_Test1	0x39		/* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define R3B_Test3	0x3b		/* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define R83_AD_IDH	0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define R91_AD_SLOPEREG 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define R94_AD_BITCONTROL 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static const u8 eeprom_data[][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /*	dataH dataM dataL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{0x01, 0x00, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{0x01, 0x80, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{0x05, 0x00, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{0x05, 0x00, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	{0x0d, 0x00, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{0x05, 0x00, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{0x05, 0x05, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	{0x05, 0x01, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	{0x05, 0x09, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	{0x0d, 0x89, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{0x05, 0x89, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{0x05, 0x0d, 0xd9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{0x05, 0x09, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* write 1 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void reg_w1(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		  __u16 index, __u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	gspca_dev->usb_buf[0] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	usb_control_msg(gspca_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			usb_sndctrlpipe(gspca_dev->dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			0,	/* value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			index, gspca_dev->usb_buf, 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* write 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void reg_w2(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		  u16 index, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	gspca_dev->usb_buf[0] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	gspca_dev->usb_buf[1] = value >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	usb_control_msg(gspca_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			usb_sndctrlpipe(gspca_dev->dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			0,	/* value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			index, gspca_dev->usb_buf, 2, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void tv_8532WriteEEprom(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	reg_w1(gspca_dev, R01_TIMING_CONTROL_LOW, CMD_EEprom_Open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	for (i = 0; i < ARRAY_SIZE(eeprom_data); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		reg_w1(gspca_dev, R03_TABLE_ADDR, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		reg_w1(gspca_dev, R04_WTRAM_DATA_L, eeprom_data[i][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		reg_w1(gspca_dev, R05_WTRAM_DATA_M, eeprom_data[i][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		reg_w1(gspca_dev, R06_WTRAM_DATA_H, eeprom_data[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		reg_w1(gspca_dev, R08_RAM_WRITE_ACTION, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	reg_w1(gspca_dev, R07_TABLE_LEN, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	reg_w1(gspca_dev, R01_TIMING_CONTROL_LOW, CMD_EEprom_Close);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* this function is called at probe time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int sd_config(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		     const struct usb_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct cam *cam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	cam = &gspca_dev->cam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	cam->cam_mode = sif_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	cam->nmodes = ARRAY_SIZE(sif_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void tv_8532_setReg(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	reg_w1(gspca_dev, R3B_Test3, 0x0a);	/* Test0Sel = 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/******************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	reg_w1(gspca_dev, R0E_AD_HEIGHTL, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	reg_w1(gspca_dev, R0F_AD_HEIGHTH, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	reg_w2(gspca_dev, R1C_AD_EXPOSE_TIMEL, 0x018f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	reg_w1(gspca_dev, R10_AD_COL_BEGINL, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 						/* begin active line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	reg_w1(gspca_dev, R11_AD_COL_BEGINH, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 						/* mirror and digital gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	reg_w1(gspca_dev, R14_AD_ROW_BEGINL, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	reg_w1(gspca_dev, R94_AD_BITCONTROL, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	reg_w1(gspca_dev, R91_AD_SLOPEREG, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 						/* = 0x84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* this function is called at probe and resume time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int sd_init(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	tv_8532WriteEEprom(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void setexposure(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	reg_w2(gspca_dev, R1C_AD_EXPOSE_TIMEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	reg_w1(gspca_dev, R00_PART_CONTROL, LATENT_CHANGE | EXPO_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 						/* 0x84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void setgain(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	reg_w2(gspca_dev, R20_GAIN_G1L, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	reg_w2(gspca_dev, R22_GAIN_RL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	reg_w2(gspca_dev, R24_GAIN_BL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	reg_w2(gspca_dev, R26_GAIN_G2L, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* -- start the camera -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int sd_start(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	reg_w1(gspca_dev, R0C_AD_WIDTHL, 0xe8);		/* 0x20; 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	reg_w1(gspca_dev, R0D_AD_WIDTHH, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	reg_w1(gspca_dev, R28_QUANT, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					/* 0x72 compressed mode 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		/* 176x144 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		reg_w1(gspca_dev, R29_LINE, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 					/* CIF - 2 lines/packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		/* 352x288 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		reg_w1(gspca_dev, R29_LINE, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 					/* CIF - 2 lines/packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	reg_w1(gspca_dev, R2C_POLARITY, 0x10);		/* slow clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	reg_w1(gspca_dev, R2D_POINT, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	reg_w1(gspca_dev, R2E_POINTH, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	reg_w1(gspca_dev, R2F_POINTB, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	reg_w1(gspca_dev, R30_POINTBH, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	tv_8532_setReg(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	reg_w1(gspca_dev, R31_UPD, 0x01);	/* update registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	reg_w1(gspca_dev, R31_UPD, 0x00);	/* end update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	gspca_dev->empty_packet = 0;		/* check the empty packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	sd->packet = 0;				/* ignore the first packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void sd_stopN(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	reg_w1(gspca_dev, R3B_Test3, 0x0b);	/* Test0Sel = 11 = GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void sd_pkt_scan(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			u8 *data,			/* isoc packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			int len)			/* iso packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	int packet_type0, packet_type1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	packet_type0 = packet_type1 = INTER_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (gspca_dev->empty_packet) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		gspca_dev->empty_packet = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		sd->packet = gspca_dev->pixfmt.height / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		packet_type0 = FIRST_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	} else if (sd->packet == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return;			/* 2 more lines in 352x288 ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	sd->packet--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (sd->packet == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		packet_type1 = LAST_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* each packet contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 * - header 2 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	 * - RGRG line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	 * - 4 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	 * - GBGB line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	 * - 4 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	gspca_frame_add(gspca_dev, packet_type0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			data + 2, gspca_dev->pixfmt.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	gspca_frame_add(gspca_dev, packet_type1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			data + gspca_dev->pixfmt.width + 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			gspca_dev->pixfmt.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int sd_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct gspca_dev *gspca_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		container_of(ctrl->handler, struct gspca_dev, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	gspca_dev->usb_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (!gspca_dev->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		setexposure(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	case V4L2_CID_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		setgain(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	return gspca_dev->usb_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct v4l2_ctrl_ops sd_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.s_ctrl = sd_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int sd_init_controls(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct v4l2_ctrl_handler *hdl = &gspca_dev->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	gspca_dev->vdev.ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	v4l2_ctrl_handler_init(hdl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			V4L2_CID_EXPOSURE, 0, 0x18f, 1, 0x18f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			V4L2_CID_GAIN, 0, 0x7ff, 1, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		pr_err("Could not initialize controls\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* sub-driver description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct sd_desc sd_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.config = sd_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.init = sd_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.init_controls = sd_init_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.start = sd_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.stopN = sd_stopN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.pkt_scan = sd_pkt_scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* -- module initialisation -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const struct usb_device_id device_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	{USB_DEVICE(0x046d, 0x0920)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{USB_DEVICE(0x046d, 0x0921)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{USB_DEVICE(0x0545, 0x808b)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	{USB_DEVICE(0x0545, 0x8333)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	{USB_DEVICE(0x0923, 0x010f)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_DEVICE_TABLE(usb, device_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* -- device connect -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int sd_probe(struct usb_interface *intf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		    const struct usb_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	return gspca_dev_probe(intf, id, &sd_desc, sizeof(struct sd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			       THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct usb_driver sd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	.name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.id_table = device_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	.probe = sd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.disconnect = gspca_disconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	.suspend = gspca_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	.resume = gspca_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.reset_resume = gspca_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) module_usb_driver(sd_driver);