^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ToupTek UCMOS / AmScope MU series camera driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * TODO: contrast with ScopeTek / AmScope MDC cameras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012-2014 John McMaster <JohnDMcMaster@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Special thanks to Bushing for helping with the decrypt algorithm and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Sean O'Sullivan / the Rensselaer Center for Open Source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Software (RCOS) for helping me learn kernel development
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "gspca.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MODULE_NAME "touptek"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) MODULE_AUTHOR("John McMaster");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MODULE_DESCRIPTION("ToupTek UCMOS / Amscope MU microscope camera driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Exposure reg is linear with exposure time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Exposure (sec), E (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * 0.000400, 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 0.001000, 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 0.005000, 0x0019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 0.020000, 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 0.080000, 0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 0.400000, 0x07D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 1.000000, 0x1388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 2.000000, 0x2710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Three gain stages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 0x1000: master channel enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 0x007F: low gain bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 0x0080: medium gain bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 0x0100: high gain bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * gain = enable * (1 + regH) * (1 + regM) * z * regL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Gain implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Want to do something similar to mt9v011.c's set_balance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Gain does not vary with resolution (checked 640x480 vs 1600x1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Constant derivation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Raw data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Gain, GTOP, B, R, GBOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 1.00, 0x105C, 0x1068, 0x10C8, 0x105C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 1.20, 0x106E, 0x107E, 0x10D6, 0x106E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 1.40, 0x10C0, 0x10CA, 0x10E5, 0x10C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 1.60, 0x10C9, 0x10D4, 0x10F3, 0x10C9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 1.80, 0x10D2, 0x10DE, 0x11C1, 0x10D2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 2.00, 0x10DC, 0x10E9, 0x11C8, 0x10DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 2.20, 0x10E5, 0x10F3, 0x11CF, 0x10E5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 2.40, 0x10EE, 0x10FE, 0x11D7, 0x10EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 2.60, 0x10F7, 0x11C4, 0x11DE, 0x10F7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 2.80, 0x11C0, 0x11CA, 0x11E5, 0x11C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 3.00, 0x11C5, 0x11CF, 0x11ED, 0x11C5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * zR = 0.0069605943152454778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * about 3/431 = 0.0069605568445475635
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * zB = 0.0095695970695970703
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * about 6/627 = 0.0095693779904306216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * zG = 0.010889328063241107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * about 6/551 = 0.010889292196007259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * about 10 bits for constant + 7 bits for value => at least 17 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * intermediate with 32 bit ints should be fine for overflow etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Essentially gains are in range 0-0x001FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * However, V4L expects a main gain channel + R and B balance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * To keep things simple for now saturate the values of balance is too high/low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * This isn't really ideal but easy way to fit the Linux model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Converted using gain model turns out to be quite linear:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Gain, GTOP, B, R, GBOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * 1.00, 92, 104, 144, 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * 1.20, 110, 126, 172, 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * 1.40, 128, 148, 202, 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * 1.60, 146, 168, 230, 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * 1.80, 164, 188, 260, 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * 2.00, 184, 210, 288, 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 2.20, 202, 230, 316, 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * 2.40, 220, 252, 348, 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 2.60, 238, 272, 376, 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * 2.80, 256, 296, 404, 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 3.00, 276, 316, 436, 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Maximum gain is 0x7FF * 2 * 2 => 0x1FFC (8188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * or about 13 effective bits of gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * The highest the commercial driver goes in my setup 436
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * However, because could *maybe* damage circuits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * limit the gain until have a reason to go higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Solution: gain clipped and warning emitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GAIN_MAX 511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Frame sync is a short read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BULK_SIZE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* MT9E001 reg names to give a rough approximation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_COARSE_INTEGRATION_TIME_ 0x3012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define REG_GROUPED_PARAMETER_HOLD_ 0x3022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define REG_MODE_SELECT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define REG_OP_SYS_CLK_DIV 0x030A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define REG_VT_SYS_CLK_DIV 0x0302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define REG_PRE_PLL_CLK_DIV 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_VT_PIX_CLK_DIV 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define REG_OP_PIX_CLK_DIV 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define REG_PLL_MULTIPLIER 0x0306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define REG_COARSE_INTEGRATION_TIME_ 0x3012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define REG_FRAME_LENGTH_LINES 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define REG_FRAME_LENGTH_LINES_ 0x300A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define REG_GREEN1_GAIN 0x3056
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define REG_GREEN2_GAIN 0x305C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define REG_GROUPED_PARAMETER_HOLD 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define REG_LINE_LENGTH_PCK_ 0x300C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define REG_MODE_SELECT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define REG_PLL_MULTIPLIER 0x0306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define REG_READ_MODE 0x3040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define REG_BLUE_GAIN 0x3058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define REG_RED_GAIN 0x305A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define REG_RESET_REGISTER 0x301A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define REG_SCALE_M 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define REG_SCALING_MODE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define REG_SOFTWARE_RESET 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define REG_X_ADDR_END 0x0348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define REG_X_ADDR_START 0x0344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define REG_X_ADDR_START 0x0344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define REG_X_OUTPUT_SIZE 0x034C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define REG_Y_ADDR_END 0x034A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define REG_Y_ADDR_START 0x0346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define REG_Y_OUTPUT_SIZE 0x034E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* specific webcam descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct sd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct gspca_dev gspca_dev; /* !! must be the first item */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* How many bytes this frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int this_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) Device has separate gains for each Bayer quadrant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) V4L supports master gain which is referenced to G1/G2 and supplies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) individual balance controls for R/B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct v4l2_ctrl *blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct v4l2_ctrl *red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Used to simplify reg write error handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u16 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct v4l2_pix_format vga_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {800, 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) V4L2_PIX_FMT_SGRBG8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .bytesperline = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .sizeimage = 800 * 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .colorspace = V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {1600, 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) V4L2_PIX_FMT_SGRBG8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .bytesperline = 1600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .sizeimage = 1600 * 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .colorspace = V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {3264, 2448,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) V4L2_PIX_FMT_SGRBG8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .bytesperline = 3264,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .sizeimage = 3264 * 2448,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .colorspace = V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * As there's no known frame sync, the only way to keep synced is to try hard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * to never miss any packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #if MAX_NURBS < 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #error "Not enough URBs in the gspca table"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int val_reply(struct gspca_dev *gspca_dev, const char *reply, int rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) gspca_err(gspca_dev, "reply has error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (rc != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) gspca_err(gspca_dev, "Bad reply size %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (reply[0] != 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) gspca_err(gspca_dev, "Bad reply 0x%02x\n", (int)reply[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void reg_w(struct gspca_dev *gspca_dev, u16 value, u16 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) char *buff = gspca_dev->usb_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) gspca_dbg(gspca_dev, D_USBO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "reg_w bReq=0x0B, bReqT=0xC0, wVal=0x%04X, wInd=0x%04X\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) value, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) rc = usb_control_msg(gspca_dev->dev, usb_rcvctrlpipe(gspca_dev->dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0x0B, 0xC0, value, index, buff, 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) gspca_dbg(gspca_dev, D_USBO, "rc=%d, ret={0x%02x}\n", rc, (int)buff[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) gspca_err(gspca_dev, "Failed reg_w(0x0B, 0xC0, 0x%04X, 0x%04X) w/ rc %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) value, index, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) gspca_dev->usb_err = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (val_reply(gspca_dev, buff, rc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) gspca_err(gspca_dev, "Bad reply to reg_w(0x0B, 0xC0, 0x%04X, 0x%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) value, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) gspca_dev->usb_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void reg_w_buf(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) const struct cmd *p, int l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) reg_w(gspca_dev, p->value, p->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) p++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } while (--l > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void setexposure(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned int w = gspca_dev->pixfmt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (w == 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) value = val * 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) else if (w == 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) value = val * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) else if (w == 3264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) value = val * 3 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) gspca_err(gspca_dev, "Invalid width %u\n", w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) gspca_dev->usb_err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) gspca_dbg(gspca_dev, D_STREAM, "exposure: 0x%04X ms\n\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Wonder if there's a good reason for sending it twice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* probably not but leave it in because...why not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) reg_w(gspca_dev, value, REG_COARSE_INTEGRATION_TIME_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) reg_w(gspca_dev, value, REG_COARSE_INTEGRATION_TIME_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int gainify(int in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * TODO: check if there are any issues with corner cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * 0x000 (0):0x07F (127): regL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * 0x080 (128) - 0x0FF (255): regM, regL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * 0x100 (256) - max: regH, regM, regL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (in <= 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0x1000 | in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) else if (in <= 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0x1080 | in / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0x1180 | in / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void setggain(struct gspca_dev *gspca_dev, u16 global_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u16 normalized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) normalized = gainify(global_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) gspca_dbg(gspca_dev, D_STREAM, "gain G1/G2 (0x%04X): 0x%04X (src 0x%04X)\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) REG_GREEN1_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) normalized, global_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) reg_w(gspca_dev, normalized, REG_GREEN1_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) reg_w(gspca_dev, normalized, REG_GREEN2_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void setbgain(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u16 gain, u16 global_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u16 normalized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) normalized = global_gain +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ((u32)global_gain) * gain / GAIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (normalized > GAIN_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) gspca_dbg(gspca_dev, D_STREAM, "Truncating blue 0x%04X w/ value 0x%04X\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) GAIN_MAX, normalized);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) normalized = GAIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) normalized = gainify(normalized);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) gspca_dbg(gspca_dev, D_STREAM, "gain B (0x%04X): 0x%04X w/ source 0x%04X\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) REG_BLUE_GAIN, normalized, gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) reg_w(gspca_dev, normalized, REG_BLUE_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void setrgain(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u16 gain, u16 global_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u16 normalized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) normalized = global_gain +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ((u32)global_gain) * gain / GAIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (normalized > GAIN_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) gspca_dbg(gspca_dev, D_STREAM, "Truncating gain 0x%04X w/ value 0x%04X\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) GAIN_MAX, normalized);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) normalized = GAIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) normalized = gainify(normalized);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) gspca_dbg(gspca_dev, D_STREAM, "gain R (0x%04X): 0x%04X w / source 0x%04X\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) REG_RED_GAIN, normalized, gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) reg_w(gspca_dev, normalized, REG_RED_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static void configure_wh(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned int w = gspca_dev->pixfmt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) gspca_dbg(gspca_dev, D_STREAM, "configure_wh\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (w == 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const struct cmd reg_init_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x0060, REG_X_ADDR_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x0CD9, REG_X_ADDR_END},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x0036, REG_Y_ADDR_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x098F, REG_Y_ADDR_END},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x07C7, REG_READ_MODE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) reg_w_buf(gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) reg_init_res, ARRAY_SIZE(reg_init_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) } else if (w == 1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct cmd reg_init_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x009C, REG_X_ADDR_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x0D19, REG_X_ADDR_END},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x0068, REG_Y_ADDR_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x09C5, REG_Y_ADDR_END},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x06C3, REG_READ_MODE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) reg_w_buf(gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) reg_init_res, ARRAY_SIZE(reg_init_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } else if (w == 3264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct cmd reg_init_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x00E8, REG_X_ADDR_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x0DA7, REG_X_ADDR_END},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x009E, REG_Y_ADDR_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x0A2D, REG_Y_ADDR_END},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x0241, REG_READ_MODE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) reg_w_buf(gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) reg_init_res, ARRAY_SIZE(reg_init_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) gspca_err(gspca_dev, "bad width %u\n", w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) gspca_dev->usb_err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) reg_w(gspca_dev, 0x0000, REG_SCALING_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) reg_w(gspca_dev, 0x0010, REG_SCALE_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) reg_w(gspca_dev, w, REG_X_OUTPUT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) reg_w(gspca_dev, gspca_dev->pixfmt.height, REG_Y_OUTPUT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (w == 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) reg_w(gspca_dev, 0x0384, REG_FRAME_LENGTH_LINES_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) reg_w(gspca_dev, 0x0960, REG_LINE_LENGTH_PCK_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) } else if (w == 1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) reg_w(gspca_dev, 0x0640, REG_FRAME_LENGTH_LINES_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) reg_w(gspca_dev, 0x0FA0, REG_LINE_LENGTH_PCK_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } else if (w == 3264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) reg_w(gspca_dev, 0x0B4B, REG_FRAME_LENGTH_LINES_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) reg_w(gspca_dev, 0x1F40, REG_LINE_LENGTH_PCK_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) gspca_err(gspca_dev, "bad width %u\n", w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) gspca_dev->usb_err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Packets that were encrypted, no idea if the grouping is significant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static void configure_encrypted(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct cmd reg_init_begin[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x0100, REG_SOFTWARE_RESET},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x0000, REG_MODE_SELECT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x0100, REG_GROUPED_PARAMETER_HOLD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x0004, REG_VT_PIX_CLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x0001, REG_VT_SYS_CLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x0008, REG_OP_PIX_CLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x0001, REG_OP_SYS_CLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x0004, REG_PRE_PLL_CLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x0040, REG_PLL_MULTIPLIER},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x0000, REG_GROUPED_PARAMETER_HOLD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x0100, REG_GROUPED_PARAMETER_HOLD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct cmd reg_init_end[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x0000, REG_GROUPED_PARAMETER_HOLD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x0301, 0x31AE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x0805, 0x3064},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x0071, 0x3170},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x10DE, REG_RESET_REGISTER},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x0000, REG_MODE_SELECT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x0010, REG_PLL_MULTIPLIER},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x0100, REG_MODE_SELECT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) gspca_dbg(gspca_dev, D_STREAM, "Encrypted begin, w = %u\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) gspca_dev->pixfmt.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) reg_w_buf(gspca_dev, reg_init_begin, ARRAY_SIZE(reg_init_begin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) configure_wh(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) reg_w_buf(gspca_dev, reg_init_end, ARRAY_SIZE(reg_init_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) reg_w(gspca_dev, 0x0100, REG_GROUPED_PARAMETER_HOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) reg_w(gspca_dev, 0x0000, REG_GROUPED_PARAMETER_HOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) gspca_dbg(gspca_dev, D_STREAM, "Encrypted end\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int configure(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) char *buff = gspca_dev->usb_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) gspca_dbg(gspca_dev, D_STREAM, "configure()\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * First driver sets a sort of encryption key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * A number of futur requests of this type have wValue and wIndex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * encrypted as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * -Compute key = this wValue rotate left by 4 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * (decrypt.py rotates right because we are decrypting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * -Later packets encrypt packets by XOR'ing with key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * XOR encrypt/decrypt is symmetrical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * wValue, and wIndex are encrypted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * bRequest is not and bRequestType is always 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * This allows resyncing if key is unknown?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * By setting 0 we XOR with 0 and the shifting and XOR drops out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) rc = usb_control_msg(gspca_dev->dev, usb_rcvctrlpipe(gspca_dev->dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 0x16, 0xC0, 0x0000, 0x0000, buff, 2, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (val_reply(gspca_dev, buff, rc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) gspca_err(gspca_dev, "failed key req\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * Next does some sort of 2 packet challenge / response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * evidence suggests its an Atmel I2C crypto part but nobody cares to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * look
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * (to make sure its not cloned hardware?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * Ignore: I want to work with their hardware, not clone it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * 16 bytes out challenge, requestType: 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * 16 bytes in response, requestType: 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) rc = usb_control_msg(gspca_dev->dev, usb_sndctrlpipe(gspca_dev->dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 0x01, 0x40, 0x0001, 0x000F, NULL, 0, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) gspca_err(gspca_dev, "failed to replay packet 176 w/ rc %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rc = usb_control_msg(gspca_dev->dev, usb_sndctrlpipe(gspca_dev->dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 0x01, 0x40, 0x0000, 0x000F, NULL, 0, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) gspca_err(gspca_dev, "failed to replay packet 178 w/ rc %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) rc = usb_control_msg(gspca_dev->dev, usb_sndctrlpipe(gspca_dev->dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 0x01, 0x40, 0x0001, 0x000F, NULL, 0, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) gspca_err(gspca_dev, "failed to replay packet 180 w/ rc %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * Serial number? Doesn't seem to be required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * cam1: \xE6\x0D\x00\x00, cam2: \x70\x19\x00\x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * rc = usb_control_msg(gspca_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * usb_rcvctrlpipe(gspca_dev->dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * 0x20, 0xC0, 0x0000, 0x0000, buff, 4, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Large (EEPROM?) read, skip it since no idea what to do with it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) gspca_dev->usb_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) configure_encrypted(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (gspca_dev->usb_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return gspca_dev->usb_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Omitted this by accident, does not work without it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) rc = usb_control_msg(gspca_dev->dev, usb_sndctrlpipe(gspca_dev->dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 0x01, 0x40, 0x0003, 0x000F, NULL, 0, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) gspca_err(gspca_dev, "failed to replay final packet w/ rc %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) gspca_dbg(gspca_dev, D_STREAM, "Configure complete\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int sd_config(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) const struct usb_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) gspca_dev->cam.cam_mode = vga_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) gspca_dev->cam.nmodes = ARRAY_SIZE(vga_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Yes we want URBs and we want them now! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) gspca_dev->cam.no_urb_create = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) gspca_dev->cam.bulk_nurbs = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Largest size the windows driver uses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) gspca_dev->cam.bulk_size = BULK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Def need to use bulk transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) gspca_dev->cam.bulk = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int sd_start(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) sd->this_f = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) rc = configure(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) gspca_err(gspca_dev, "Failed configure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* First two frames have messed up gains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) Drop them to avoid special cases in user apps? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void sd_pkt_scan(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u8 *data, /* isoc packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int len) /* iso packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (len != BULK_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* can we finish a frame? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (sd->this_f + len == gspca_dev->pixfmt.sizeimage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) gspca_frame_add(gspca_dev, LAST_PACKET, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) gspca_dbg(gspca_dev, D_FRAM, "finish frame sz %u/%u w/ len %u\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) sd->this_f, gspca_dev->pixfmt.sizeimage, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* lost some data, discard the frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) gspca_frame_add(gspca_dev, DISCARD_PACKET, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) gspca_dbg(gspca_dev, D_FRAM, "abort frame sz %u/%u w/ len %u\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) sd->this_f, gspca_dev->pixfmt.sizeimage, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) sd->this_f = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (sd->this_f == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) gspca_frame_add(gspca_dev, FIRST_PACKET, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) sd->this_f += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int sd_init(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int sd_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct gspca_dev *gspca_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) container_of(ctrl->handler, struct gspca_dev, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) gspca_dev->usb_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!gspca_dev->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) setexposure(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case V4L2_CID_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* gspca_dev->gain automatically updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) setggain(gspca_dev, gspca_dev->gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) case V4L2_CID_BLUE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) sd->blue->val = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) setbgain(gspca_dev, sd->blue->val, gspca_dev->gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case V4L2_CID_RED_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) sd->red->val = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) setrgain(gspca_dev, sd->red->val, gspca_dev->gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return gspca_dev->usb_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const struct v4l2_ctrl_ops sd_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .s_ctrl = sd_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int sd_init_controls(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct v4l2_ctrl_handler *hdl = &gspca_dev->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) gspca_dev->vdev.ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) v4l2_ctrl_handler_init(hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) gspca_dev->exposure = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Mostly limited by URB timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* XXX: make dynamic based on frame rate? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) V4L2_CID_EXPOSURE, 0, 800, 1, 350);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) gspca_dev->gain = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) V4L2_CID_GAIN, 0, 511, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) sd->blue = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) V4L2_CID_BLUE_BALANCE, 0, 1023, 1, 80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) sd->red = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) V4L2_CID_RED_BALANCE, 0, 1023, 1, 295);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) gspca_err(gspca_dev, "Could not initialize controls\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* sub-driver description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct sd_desc sd_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .config = sd_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .init = sd_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .init_controls = sd_init_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .start = sd_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .pkt_scan = sd_pkt_scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Table of supported USB devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static const struct usb_device_id device_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Commented out devices should be related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* AS: AmScope, TT: ToupTek */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* { USB_DEVICE(0x0547, 0x6035) }, TT UCMOS00350KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* { USB_DEVICE(0x0547, 0x6130) }, TT UCMOS01300KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* { USB_DEVICE(0x0547, 0x6200) }, TT UCMOS02000KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* { USB_DEVICE(0x0547, 0x6310) }, TT UCMOS03100KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* { USB_DEVICE(0x0547, 0x6510) }, TT UCMOS05100KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* { USB_DEVICE(0x0547, 0x6800) }, TT UCMOS08000KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* { USB_DEVICE(0x0547, 0x6801) }, TT UCMOS08000KPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { USB_DEVICE(0x0547, 0x6801) }, /* TT UCMOS08000KPB, AS MU800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* { USB_DEVICE(0x0547, 0x6900) }, TT UCMOS09000KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* { USB_DEVICE(0x0547, 0x6901) }, TT UCMOS09000KPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* { USB_DEVICE(0x0547, 0x6010) }, TT UCMOS10000KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* { USB_DEVICE(0x0547, 0x6014) }, TT UCMOS14000KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* { USB_DEVICE(0x0547, 0x6131) }, TT UCMOS01300KMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* { USB_DEVICE(0x0547, 0x6511) }, TT UCMOS05100KMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* { USB_DEVICE(0x0547, 0x8080) }, TT UHCCD00800KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* { USB_DEVICE(0x0547, 0x8140) }, TT UHCCD01400KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* { USB_DEVICE(0x0547, 0x8141) }, TT EXCCD01400KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* { USB_DEVICE(0x0547, 0x8200) }, TT UHCCD02000KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* { USB_DEVICE(0x0547, 0x8201) }, TT UHCCD02000KPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* { USB_DEVICE(0x0547, 0x8310) }, TT UHCCD03100KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* { USB_DEVICE(0x0547, 0x8500) }, TT UHCCD05000KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* { USB_DEVICE(0x0547, 0x8510) }, TT UHCCD05100KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* { USB_DEVICE(0x0547, 0x8600) }, TT UHCCD06000KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* { USB_DEVICE(0x0547, 0x8800) }, TT UHCCD08000KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* { USB_DEVICE(0x0547, 0x8315) }, TT UHCCD03150KPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* { USB_DEVICE(0x0547, 0x7800) }, TT UHCCD00800KMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* { USB_DEVICE(0x0547, 0x7140) }, TT UHCCD01400KMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* { USB_DEVICE(0x0547, 0x7141) }, TT UHCCD01400KMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* { USB_DEVICE(0x0547, 0x7200) }, TT UHCCD02000KMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* { USB_DEVICE(0x0547, 0x7315) }, TT UHCCD03150KMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) MODULE_DEVICE_TABLE(usb, device_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static int sd_probe(struct usb_interface *intf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) const struct usb_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return gspca_dev_probe(intf, id, &sd_desc, sizeof(struct sd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static struct usb_driver sd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .id_table = device_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .probe = sd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .disconnect = gspca_disconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .suspend = gspca_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .resume = gspca_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int __init sd_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = usb_register(&sd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static void __exit sd_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) usb_deregister(&sd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) module_init(sd_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) module_exit(sd_mod_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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