Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * STK1135 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2013 Ondrej Zary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define STK1135_REG_GCTRL	0x000	/* GPIO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define STK1135_REG_ICTRL	0x004	/* Interrupt control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define STK1135_REG_IDATA	0x008	/* Interrupt data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define STK1135_REG_RMCTL	0x00c	/* Remote wakeup control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define STK1135_REG_POSVA	0x010	/* Power-on strapping data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define STK1135_REG_SENSO	0x018	/* Sensor select options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define STK1135_REG_PLLFD	0x01c	/* PLL frequency divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define STK1135_REG_SCTRL	0x100	/* Sensor control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STK1135_REG_DCTRL	0x104	/* Decimation control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define STK1135_REG_CISPO	0x110	/* Capture image starting position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STK1135_REG_CIEPO	0x114	/* Capture image ending position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STK1135_REG_TCTRL	0x120	/* Test data control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STK1135_REG_SICTL	0x200	/* Serial interface control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STK1135_REG_SBUSW	0x204	/* Serial bus write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STK1135_REG_SBUSR	0x208	/* Serial bus read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STK1135_REG_SCSI	0x20c	/* Software control serial interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STK1135_REG_GSBWP	0x210	/* General serial bus write port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STK1135_REG_GSBRP	0x214	/* General serial bus read port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STK1135_REG_ASIC	0x2fc	/* Alternate serial interface control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STK1135_REG_TMGEN	0x300	/* Timing generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STK1135_REG_TCP1	0x350	/* Timing control parameter 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct stk1135_pkt_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	u8 seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	__le16 gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STK1135_HDR_FRAME_START	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STK1135_HDR_ODD		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define STK1135_HDR_I2C_VBLANK	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STK1135_HDR_SEQ_MASK	0x3f