Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * SPCA506 chip based cameras function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * M Xhaard 15/04/2004 based on different work Mark Taylor and others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * and my own snoopy file on a pv-321c donate by a german compagny
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *                "Firma Frank Gmbh" from  Saarbruecken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * V4L2 by Jean-Francois Moine <http://moinejf.free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define MODULE_NAME "spca506"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "gspca.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) MODULE_DESCRIPTION("GSPCA/SPCA506 USB Camera Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* specific webcam descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) struct sd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	struct gspca_dev gspca_dev;	/* !! must be the first item */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	char norme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	char channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static const struct v4l2_pix_format vga_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	{160, 120, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		.bytesperline = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		.sizeimage = 160 * 120 * 3 / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		.colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		.priv = 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{176, 144, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		.bytesperline = 176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		.sizeimage = 176 * 144 * 3 / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		.colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.priv = 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{320, 240, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.bytesperline = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.sizeimage = 320 * 240 * 3 / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.priv = 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{352, 288, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.bytesperline = 352,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.sizeimage = 352 * 288 * 3 / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{640, 480, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.bytesperline = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.sizeimage = 640 * 480 * 3 / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.priv = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SPCA50X_OFFSET_DATA 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SAA7113_bright 0x0a	/* defaults 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SAA7113_contrast 0x0b	/* defaults 0x47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SAA7113_saturation 0x0c	/* defaults 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SAA7113_hue 0x0d	/* defaults 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SAA7113_I2C_BASE_WRITE 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* read 'len' bytes to gspca_dev->usb_buf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static void reg_r(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		  __u16 req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		  __u16 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		  __u16 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	usb_control_msg(gspca_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			usb_rcvctrlpipe(gspca_dev->dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			0,		/* value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			index, gspca_dev->usb_buf, length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static void reg_w(struct usb_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		  __u16 req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		  __u16 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		  __u16 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	usb_control_msg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			usb_sndctrlpipe(dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			value, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			NULL, 0, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void spca506_Initi2c(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	reg_w(gspca_dev->dev, 0x07, SAA7113_I2C_BASE_WRITE, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static void spca506_WriteI2c(struct gspca_dev *gspca_dev, __u16 valeur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			     __u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	int retry = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	reg_w(gspca_dev->dev, 0x07, reg, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	reg_w(gspca_dev->dev, 0x07, valeur, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	while (retry--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		reg_r(gspca_dev, 0x07, 0x0003, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		if ((gspca_dev->usb_buf[0] | gspca_dev->usb_buf[1]) == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void spca506_SetNormeInput(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				 __u16 norme,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 				 __u16 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* fixme: check if channel == 0..3 and 6..9 (8 values) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	__u8 setbit0 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	__u8 setbit1 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	__u8 videomask = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	gspca_dbg(gspca_dev, D_STREAM, "** Open Set Norme **\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	spca506_Initi2c(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	/* NTSC bit0 -> 1(525 l) PAL SECAM bit0 -> 0 (625 l) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* Composite channel bit1 -> 1 S-video bit 1 -> 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* and exclude SAA7113 reserved channel set default 0 otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (norme & V4L2_STD_NTSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		setbit0 = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (channel == 4 || channel == 5 || channel > 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (channel < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		setbit1 = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	videomask = (0x48 | setbit0 | setbit1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	reg_w(gspca_dev->dev, 0x08, videomask, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	spca506_WriteI2c(gspca_dev, (0xc0 | (channel & 0x0F)), 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (norme & V4L2_STD_NTSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		spca506_WriteI2c(gspca_dev, 0x33, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 					/* Chrominance Control NTSC N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	else if (norme & V4L2_STD_SECAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		spca506_WriteI2c(gspca_dev, 0x53, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 					/* Chrominance Control SECAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		spca506_WriteI2c(gspca_dev, 0x03, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 					/* Chrominance Control PAL BGHIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	sd->norme = norme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	sd->channel = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	gspca_dbg(gspca_dev, D_STREAM, "Set Video Byte to 0x%2x\n", videomask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	gspca_dbg(gspca_dev, D_STREAM, "Set Norme: %08x Channel %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		  norme, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void spca506_GetNormeInput(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				  __u16 *norme, __u16 *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* Read the register is not so good value change so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	   we use your own copy in spca50x struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	*norme = sd->norme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	*channel = sd->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	gspca_dbg(gspca_dev, D_STREAM, "Get Norme: %d Channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		  *norme, *channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void spca506_Setsize(struct gspca_dev *gspca_dev, __u16 code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			    __u16 xmult, __u16 ymult)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct usb_device *dev = gspca_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	gspca_dbg(gspca_dev, D_STREAM, "** SetSize **\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	reg_w(dev, 0x04, (0x18 | (code & 0x07)), 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* Soft snap 0x40 Hard 0x41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	reg_w(dev, 0x04, 0x41, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	reg_w(dev, 0x04, 0x00, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	reg_w(dev, 0x04, 0x00, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	reg_w(dev, 0x04, 0x00, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	reg_w(dev, 0x04, 0x01, 0x0005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/* reserced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	reg_w(dev, 0x04, xmult, 0x0006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	/* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	reg_w(dev, 0x04, ymult, 0x0007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* compression 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	reg_w(dev, 0x04, 0x00, 0x0008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* T=64 -> 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	reg_w(dev, 0x04, 0x00, 0x0009);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* threshold2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	reg_w(dev, 0x04, 0x21, 0x000a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* quantization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	reg_w(dev, 0x04, 0x00, 0x000b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* this function is called at probe time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int sd_config(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			const struct usb_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct cam *cam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	cam = &gspca_dev->cam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	cam->cam_mode = vga_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	cam->nmodes = ARRAY_SIZE(vga_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* this function is called at probe and resume time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int sd_init(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct usb_device *dev = gspca_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	reg_w(dev, 0x03, 0x00, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	reg_w(dev, 0x03, 0xFF, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	reg_w(dev, 0x03, 0x00, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	reg_w(dev, 0x03, 0x1c, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	reg_w(dev, 0x03, 0x18, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* Init on PAL and composite input0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	spca506_SetNormeInput(gspca_dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	reg_w(dev, 0x03, 0x1c, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	reg_w(dev, 0x03, 0x18, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	reg_w(dev, 0x05, 0x00, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	reg_w(dev, 0x05, 0xef, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	reg_w(dev, 0x05, 0x00, 0x00c1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	reg_w(dev, 0x05, 0x00, 0x00c2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	reg_w(dev, 0x06, 0x18, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	reg_w(dev, 0x06, 0xf5, 0x0011);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	reg_w(dev, 0x06, 0x02, 0x0012);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	reg_w(dev, 0x06, 0xfb, 0x0013);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	reg_w(dev, 0x06, 0x00, 0x0014);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	reg_w(dev, 0x06, 0xa4, 0x0051);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	reg_w(dev, 0x06, 0x40, 0x0052);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	reg_w(dev, 0x06, 0x71, 0x0053);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	reg_w(dev, 0x06, 0x40, 0x0054);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	/************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	reg_w(dev, 0x03, 0x00, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	reg_w(dev, 0x03, 0x00, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	reg_w(dev, 0x03, 0x00, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	reg_w(dev, 0x03, 0xFF, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	reg_w(dev, 0x02, 0x00, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	reg_w(dev, 0x03, 0x60, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	reg_w(dev, 0x03, 0x18, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* for a better reading mx :)	  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/*sdca506_WriteI2c(value,register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	spca506_Initi2c(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	spca506_WriteI2c(gspca_dev, 0x08, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	spca506_WriteI2c(gspca_dev, 0xc0, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 						/* input composite video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	spca506_WriteI2c(gspca_dev, 0x33, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	spca506_WriteI2c(gspca_dev, 0x00, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	spca506_WriteI2c(gspca_dev, 0x00, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	spca506_WriteI2c(gspca_dev, 0x0d, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	spca506_WriteI2c(gspca_dev, 0xf0, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	spca506_WriteI2c(gspca_dev, 0x98, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	spca506_WriteI2c(gspca_dev, 0x03, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	spca506_WriteI2c(gspca_dev, 0x80, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	spca506_WriteI2c(gspca_dev, 0x47, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	spca506_WriteI2c(gspca_dev, 0x48, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	spca506_WriteI2c(gspca_dev, 0x00, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	spca506_WriteI2c(gspca_dev, 0x03, 0x0e);	/* Chroma Pal adjust */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	spca506_WriteI2c(gspca_dev, 0x2a, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	spca506_WriteI2c(gspca_dev, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	spca506_WriteI2c(gspca_dev, 0x0c, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	spca506_WriteI2c(gspca_dev, 0xb8, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	spca506_WriteI2c(gspca_dev, 0x01, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	spca506_WriteI2c(gspca_dev, 0x00, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	spca506_WriteI2c(gspca_dev, 0x00, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	spca506_WriteI2c(gspca_dev, 0x00, 0x16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	spca506_WriteI2c(gspca_dev, 0x00, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	spca506_WriteI2c(gspca_dev, 0x00, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	spca506_WriteI2c(gspca_dev, 0x00, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	spca506_WriteI2c(gspca_dev, 0x00, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	spca506_WriteI2c(gspca_dev, 0x00, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	spca506_WriteI2c(gspca_dev, 0x00, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	spca506_WriteI2c(gspca_dev, 0x00, 0x1d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	spca506_WriteI2c(gspca_dev, 0x00, 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	spca506_WriteI2c(gspca_dev, 0xa1, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	spca506_WriteI2c(gspca_dev, 0x02, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	spca506_WriteI2c(gspca_dev, 0xff, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	spca506_WriteI2c(gspca_dev, 0xff, 0x42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	spca506_WriteI2c(gspca_dev, 0xff, 0x43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	spca506_WriteI2c(gspca_dev, 0xff, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	spca506_WriteI2c(gspca_dev, 0xff, 0x45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	spca506_WriteI2c(gspca_dev, 0xff, 0x46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	spca506_WriteI2c(gspca_dev, 0xff, 0x47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	spca506_WriteI2c(gspca_dev, 0xff, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	spca506_WriteI2c(gspca_dev, 0xff, 0x49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	spca506_WriteI2c(gspca_dev, 0xff, 0x4a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	spca506_WriteI2c(gspca_dev, 0xff, 0x4b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	spca506_WriteI2c(gspca_dev, 0xff, 0x4c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	spca506_WriteI2c(gspca_dev, 0xff, 0x4d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	spca506_WriteI2c(gspca_dev, 0xff, 0x4e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	spca506_WriteI2c(gspca_dev, 0xff, 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	spca506_WriteI2c(gspca_dev, 0xff, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	spca506_WriteI2c(gspca_dev, 0xff, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	spca506_WriteI2c(gspca_dev, 0xff, 0x52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	spca506_WriteI2c(gspca_dev, 0xff, 0x53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	spca506_WriteI2c(gspca_dev, 0xff, 0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	spca506_WriteI2c(gspca_dev, 0xff, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	spca506_WriteI2c(gspca_dev, 0xff, 0x56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	spca506_WriteI2c(gspca_dev, 0xff, 0x57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	spca506_WriteI2c(gspca_dev, 0x00, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	spca506_WriteI2c(gspca_dev, 0x54, 0x59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	spca506_WriteI2c(gspca_dev, 0x07, 0x5a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	spca506_WriteI2c(gspca_dev, 0x83, 0x5b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	spca506_WriteI2c(gspca_dev, 0x00, 0x5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	spca506_WriteI2c(gspca_dev, 0x00, 0x5d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	spca506_WriteI2c(gspca_dev, 0x00, 0x5e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	spca506_WriteI2c(gspca_dev, 0x00, 0x5f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	spca506_WriteI2c(gspca_dev, 0x00, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	spca506_WriteI2c(gspca_dev, 0x05, 0x61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	spca506_WriteI2c(gspca_dev, 0x9f, 0x62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	gspca_dbg(gspca_dev, D_STREAM, "** Close Init *\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int sd_start(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	struct usb_device *dev = gspca_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	__u16 norme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	__u16 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	/**************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	reg_w(dev, 0x03, 0x00, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	reg_w(dev, 0x03, 0x00, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	reg_w(dev, 0x03, 0x00, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	reg_w(dev, 0x03, 0xFF, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	reg_w(dev, 0x02, 0x00, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	reg_w(dev, 0x03, 0x60, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	reg_w(dev, 0x03, 0x18, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	/*sdca506_WriteI2c(value,register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	spca506_Initi2c(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	spca506_WriteI2c(gspca_dev, 0x08, 0x01);	/* Increment Delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*	spca506_WriteI2c(gspca_dev, 0xc0, 0x02); * Analog Input Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	spca506_WriteI2c(gspca_dev, 0x33, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 						/* Analog Input Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	spca506_WriteI2c(gspca_dev, 0x00, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 						/* Analog Input Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	spca506_WriteI2c(gspca_dev, 0x00, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 						/* Analog Input Control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	spca506_WriteI2c(gspca_dev, 0x0d, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 					/* Horizontal Sync Start 0xe9-0x0d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	spca506_WriteI2c(gspca_dev, 0xf0, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 					/* Horizontal Sync Stop  0x0d-0xf0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	spca506_WriteI2c(gspca_dev, 0x98, 0x08);	/* Sync Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*		Defaults value			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	spca506_WriteI2c(gspca_dev, 0x03, 0x09);	/* Luminance Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	spca506_WriteI2c(gspca_dev, 0x80, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 						/* Luminance Brightness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	spca506_WriteI2c(gspca_dev, 0x47, 0x0b);	/* Luminance Contrast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	spca506_WriteI2c(gspca_dev, 0x48, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 						/* Chrominance Saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	spca506_WriteI2c(gspca_dev, 0x00, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 						/* Chrominance Hue Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	spca506_WriteI2c(gspca_dev, 0x2a, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 						/* Chrominance Gain Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	/**************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	spca506_WriteI2c(gspca_dev, 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 						/* Format/Delay Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	spca506_WriteI2c(gspca_dev, 0x0c, 0x11);	/* Output Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	spca506_WriteI2c(gspca_dev, 0xb8, 0x12);	/* Output Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	spca506_WriteI2c(gspca_dev, 0x01, 0x13);	/* Output Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	spca506_WriteI2c(gspca_dev, 0x00, 0x14);	/* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	spca506_WriteI2c(gspca_dev, 0x00, 0x15);	/* VGATE START */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	spca506_WriteI2c(gspca_dev, 0x00, 0x16);	/* VGATE STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	spca506_WriteI2c(gspca_dev, 0x00, 0x17);    /* VGATE Control (MSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	spca506_WriteI2c(gspca_dev, 0x00, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	spca506_WriteI2c(gspca_dev, 0x00, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	spca506_WriteI2c(gspca_dev, 0x00, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	spca506_WriteI2c(gspca_dev, 0x00, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	spca506_WriteI2c(gspca_dev, 0x00, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	spca506_WriteI2c(gspca_dev, 0x00, 0x1d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	spca506_WriteI2c(gspca_dev, 0x00, 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	spca506_WriteI2c(gspca_dev, 0xa1, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	spca506_WriteI2c(gspca_dev, 0x02, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	spca506_WriteI2c(gspca_dev, 0xff, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	spca506_WriteI2c(gspca_dev, 0xff, 0x42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	spca506_WriteI2c(gspca_dev, 0xff, 0x43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	spca506_WriteI2c(gspca_dev, 0xff, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	spca506_WriteI2c(gspca_dev, 0xff, 0x45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	spca506_WriteI2c(gspca_dev, 0xff, 0x46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	spca506_WriteI2c(gspca_dev, 0xff, 0x47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	spca506_WriteI2c(gspca_dev, 0xff, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	spca506_WriteI2c(gspca_dev, 0xff, 0x49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	spca506_WriteI2c(gspca_dev, 0xff, 0x4a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	spca506_WriteI2c(gspca_dev, 0xff, 0x4b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	spca506_WriteI2c(gspca_dev, 0xff, 0x4c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	spca506_WriteI2c(gspca_dev, 0xff, 0x4d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	spca506_WriteI2c(gspca_dev, 0xff, 0x4e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	spca506_WriteI2c(gspca_dev, 0xff, 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	spca506_WriteI2c(gspca_dev, 0xff, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	spca506_WriteI2c(gspca_dev, 0xff, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	spca506_WriteI2c(gspca_dev, 0xff, 0x52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	spca506_WriteI2c(gspca_dev, 0xff, 0x53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	spca506_WriteI2c(gspca_dev, 0xff, 0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	spca506_WriteI2c(gspca_dev, 0xff, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	spca506_WriteI2c(gspca_dev, 0xff, 0x56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	spca506_WriteI2c(gspca_dev, 0xff, 0x57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	spca506_WriteI2c(gspca_dev, 0x00, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	spca506_WriteI2c(gspca_dev, 0x54, 0x59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	spca506_WriteI2c(gspca_dev, 0x07, 0x5a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	spca506_WriteI2c(gspca_dev, 0x83, 0x5b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	spca506_WriteI2c(gspca_dev, 0x00, 0x5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	spca506_WriteI2c(gspca_dev, 0x00, 0x5d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	spca506_WriteI2c(gspca_dev, 0x00, 0x5e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	spca506_WriteI2c(gspca_dev, 0x00, 0x5f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	spca506_WriteI2c(gspca_dev, 0x00, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	spca506_WriteI2c(gspca_dev, 0x05, 0x61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	spca506_WriteI2c(gspca_dev, 0x9f, 0x62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	/**************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	reg_w(dev, 0x05, 0x00, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	reg_w(dev, 0x05, 0x00, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	reg_w(dev, 0x03, 0x10, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	reg_w(dev, 0x03, 0x78, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	switch (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		spca506_Setsize(gspca_dev, 0, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		spca506_Setsize(gspca_dev, 1, 0x1a, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		spca506_Setsize(gspca_dev, 2, 0x1c, 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		spca506_Setsize(gspca_dev, 4, 0x34, 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*	case 5: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		spca506_Setsize(gspca_dev, 5, 0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	/* compress setting and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	/* set i2c luma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	reg_w(dev, 0x02, 0x01, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	reg_w(dev, 0x03, 0x12, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	reg_r(gspca_dev, 0x04, 0x0001, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	gspca_dbg(gspca_dev, D_STREAM, "webcam started\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	spca506_GetNormeInput(gspca_dev, &norme, &channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	spca506_SetNormeInput(gspca_dev, norme, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static void sd_stopN(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	struct usb_device *dev = gspca_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	reg_w(dev, 0x02, 0x00, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	reg_w(dev, 0x03, 0x00, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	reg_w(dev, 0x03, 0x00, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void sd_pkt_scan(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 			u8 *data,			/* isoc packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 			int len)			/* iso packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	switch (data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	case 0:				/* start of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		data += SPCA50X_OFFSET_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		len -= SPCA50X_OFFSET_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		gspca_frame_add(gspca_dev, FIRST_PACKET, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	case 0xff:			/* drop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /*		gspca_dev->last_packet_type = DISCARD_PACKET; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		data += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		len -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static void setbrightness(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	spca506_Initi2c(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	spca506_WriteI2c(gspca_dev, val, SAA7113_bright);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	spca506_WriteI2c(gspca_dev, 0x01, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static void setcontrast(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	spca506_Initi2c(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	spca506_WriteI2c(gspca_dev, val, SAA7113_contrast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	spca506_WriteI2c(gspca_dev, 0x01, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static void setcolors(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	spca506_Initi2c(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	spca506_WriteI2c(gspca_dev, val, SAA7113_saturation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	spca506_WriteI2c(gspca_dev, 0x01, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static void sethue(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	spca506_Initi2c(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	spca506_WriteI2c(gspca_dev, val, SAA7113_hue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	spca506_WriteI2c(gspca_dev, 0x01, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int sd_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	struct gspca_dev *gspca_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		container_of(ctrl->handler, struct gspca_dev, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	gspca_dev->usb_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	if (!gspca_dev->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		setbrightness(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		setcontrast(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		setcolors(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		sethue(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	return gspca_dev->usb_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const struct v4l2_ctrl_ops sd_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	.s_ctrl = sd_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int sd_init_controls(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	struct v4l2_ctrl_handler *hdl = &gspca_dev->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	gspca_dev->vdev.ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	v4l2_ctrl_handler_init(hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 			V4L2_CID_CONTRAST, 0, 255, 1, 0x47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 			V4L2_CID_SATURATION, 0, 255, 1, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 			V4L2_CID_HUE, 0, 255, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 		pr_err("Could not initialize controls\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 		return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* sub-driver description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const struct sd_desc sd_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	.name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	.config = sd_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	.init = sd_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	.init_controls = sd_init_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	.start = sd_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	.stopN = sd_stopN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	.pkt_scan = sd_pkt_scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* -- module initialisation -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const struct usb_device_id device_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	{USB_DEVICE(0x06e1, 0xa190)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*	{USB_DEVICE(0x0733, 0x0430)}, FIXME: may be IntelPCCameraPro BRIDGE_SPCA505 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	{USB_DEVICE(0x0734, 0x043b)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	{USB_DEVICE(0x99fa, 0x8988)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) MODULE_DEVICE_TABLE(usb, device_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* -- device connect -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int sd_probe(struct usb_interface *intf, const struct usb_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	return gspca_dev_probe(intf, id, &sd_desc, sizeof(struct sd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 				THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static struct usb_driver sd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	.name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	.id_table = device_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	.probe = sd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	.disconnect = gspca_disconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	.suspend = gspca_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	.resume = gspca_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	.reset_resume = gspca_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) module_usb_driver(sd_driver);