Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * GSPCA Endpoints (formerly known as AOX) se401 USB Camera sub Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2011 Hans de Goede <hdegoede@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Based on the v4l1 se401 driver which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Copyright (c) 2000 Jeroen B. Vreeken (pe1rxq@amsat.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SE401_REQ_GET_CAMERA_DESCRIPTOR		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SE401_REQ_START_CONTINUOUS_CAPTURE	0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SE401_REQ_STOP_CONTINUOUS_CAPTURE	0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SE401_REQ_CAPTURE_FRAME			0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SE401_REQ_GET_BRT			0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SE401_REQ_SET_BRT			0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SE401_REQ_GET_WIDTH			0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SE401_REQ_SET_WIDTH			0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SE401_REQ_GET_HEIGHT			0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SE401_REQ_SET_HEIGHT			0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SE401_REQ_GET_OUTPUT_MODE		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SE401_REQ_SET_OUTPUT_MODE		0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SE401_REQ_GET_EXT_FEATURE		0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SE401_REQ_SET_EXT_FEATURE		0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SE401_REQ_CAMERA_POWER			0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SE401_REQ_LED_CONTROL			0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SE401_REQ_BIOS				0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SE401_BIOS_READ				0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SE401_FORMAT_BAYER	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Hyundai hv7131b registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)    7121 and 7141 should be the same (haven't really checked...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Mode registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HV7131_REG_MODE_A		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HV7131_REG_MODE_B		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HV7131_REG_MODE_C		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Frame registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HV7131_REG_FRSU		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HV7131_REG_FRSL		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HV7131_REG_FCSU		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HV7131_REG_FCSL		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HV7131_REG_FWHU		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HV7131_REG_FWHL		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HV7131_REG_FWWU		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HV7131_REG_FWWL		0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Timing registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HV7131_REG_THBU		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HV7131_REG_THBL		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HV7131_REG_TVBU		0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HV7131_REG_TVBL		0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HV7131_REG_TITU		0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HV7131_REG_TITM		0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HV7131_REG_TITL		0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HV7131_REG_TMCD		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Adjust Registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HV7131_REG_ARLV		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HV7131_REG_ARCG		0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HV7131_REG_AGCG		0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HV7131_REG_ABCG		0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HV7131_REG_APBV		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HV7131_REG_ASLP		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Offset Registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HV7131_REG_OFSR		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HV7131_REG_OFSG		0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HV7131_REG_OFSB		0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* REset level statistics registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HV7131_REG_LOREFNOH	0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HV7131_REG_LOREFNOL	0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HV7131_REG_HIREFNOH	0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HV7131_REG_HIREFNOL	0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* se401 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SE401_OPERATINGMODE	0x2000