^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OV519 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008-2011 Jean-François Moine <moinejf@free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 Hans de Goede <hdegoede@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This module is adapted from the ov51x-jpeg package, which itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * was adapted from the ov511 driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Original copyright for the ov511 driver is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (c) 1999-2006 Mark W. McClelland
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Support for OV519, OV8610 Copyright (c) 2003 Joerg Heckenbach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Many improvements by Bret Wallach <bwallac1@san.rr.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Color fixes by by Orion Sky Lawlor <olawlor@acm.org> (2/26/2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * OV7620 fixes by Charl P. Botha <cpbotha@ieee.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Changes by Claudio Matsuoka <claudio@conectiva.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ov51x-jpeg original copyright is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Copyright (c) 2004-2007 Romain Beauxis <toots@rastageeks.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Support for OV7670 sensors was contributed by Sam Skipsey <aoanla@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MODULE_NAME "ov519"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "gspca.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* The jpeg_hdr is used by w996Xcf only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* The CONEX_CAM define for jpeg.h needs renaming, now its used here too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CONEX_CAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "jpeg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_AUTHOR("Jean-Francois Moine <http://moinejf.free.fr>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MODULE_DESCRIPTION("OV519 USB Camera Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* global parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int frame_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Number of times to retry a failed I2C transaction. Increase this if you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * are getting "Failed to read sensor ID..." */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int i2c_detect_tries = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* ov519 device descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct sd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct gspca_dev gspca_dev; /* !! must be the first item */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct v4l2_ctrl *jpegqual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct v4l2_ctrl *freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct { /* h/vflip control cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct v4l2_ctrl *hflip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct v4l2_ctrl *vflip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct { /* autobrightness/brightness control cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct v4l2_ctrl *autobright;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct v4l2_ctrl *brightness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 packet_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) char bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BRIDGE_OV511 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BRIDGE_OV511PLUS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BRIDGE_OV518 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BRIDGE_OV518PLUS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BRIDGE_OV519 4 /* = ov530 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BRIDGE_OVFX2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BRIDGE_W9968CF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BRIDGE_MASK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) char invert_led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BRIDGE_INVERT_LED 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) char snapshot_pressed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) char snapshot_needs_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Determined by sensor type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 sif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define QUALITY_MIN 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define QUALITY_MAX 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define QUALITY_DEF 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 stopped; /* Streaming is temporarily paused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 first_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 frame_rate; /* current Framerate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 clockdiv; /* clockdiv override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) s8 sensor; /* Type of image sensor chip (SEN_*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 sensor_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 sensor_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u16 sensor_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) s16 sensor_reg_cache[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 jpeg_hdr[JPEG_HDR_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum sensors {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SEN_OV2610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SEN_OV2610AE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SEN_OV3610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SEN_OV6620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SEN_OV6630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SEN_OV66308AF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SEN_OV7610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SEN_OV7620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SEN_OV7620AE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SEN_OV7640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SEN_OV7648,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SEN_OV7660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SEN_OV7670,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SEN_OV76BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SEN_OV8610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SEN_OV9600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Note this is a bit of a hack, but the w9968cf driver needs the code for all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) the ov sensors which is already present here. When we have the time we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) really should move the sensor drivers to v4l2 sub drivers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #include "w996Xcf.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* table of the disabled controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct ctrl_valid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int has_brightness:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int has_contrast:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int has_exposure:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int has_autogain:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int has_sat:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int has_hvflip:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int has_autobright:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int has_freq:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct ctrl_valid valid_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [SEN_OV2610] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .has_exposure = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .has_autogain = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [SEN_OV2610AE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .has_exposure = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .has_autogain = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [SEN_OV3610] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* No controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [SEN_OV6620] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .has_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .has_contrast = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .has_sat = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .has_autobright = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .has_freq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [SEN_OV6630] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .has_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .has_contrast = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .has_sat = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .has_autobright = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .has_freq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [SEN_OV66308AF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .has_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .has_contrast = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .has_sat = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .has_autobright = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .has_freq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [SEN_OV7610] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .has_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .has_contrast = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .has_sat = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .has_autobright = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .has_freq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [SEN_OV7620] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .has_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .has_contrast = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .has_sat = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .has_autobright = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .has_freq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [SEN_OV7620AE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .has_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .has_contrast = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .has_sat = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .has_autobright = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .has_freq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [SEN_OV7640] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .has_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .has_sat = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .has_freq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [SEN_OV7648] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .has_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .has_sat = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .has_freq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [SEN_OV7660] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .has_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .has_contrast = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .has_sat = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .has_hvflip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .has_freq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [SEN_OV7670] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .has_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .has_contrast = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .has_hvflip = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .has_freq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [SEN_OV76BE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .has_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .has_contrast = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .has_sat = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .has_autobright = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .has_freq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [SEN_OV8610] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .has_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .has_contrast = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .has_sat = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .has_autobright = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [SEN_OV9600] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .has_exposure = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .has_autogain = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct v4l2_pix_format ov519_vga_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .bytesperline = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .sizeimage = 320 * 240 * 3 / 8 + 590,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .bytesperline = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .sizeimage = 640 * 480 * 3 / 8 + 590,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .priv = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const struct v4l2_pix_format ov519_sif_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {160, 120, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .bytesperline = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .sizeimage = 160 * 120 * 3 / 8 + 590,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .priv = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {176, 144, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .bytesperline = 176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .sizeimage = 176 * 144 * 3 / 8 + 590,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .bytesperline = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .sizeimage = 320 * 240 * 3 / 8 + 590,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .priv = 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .bytesperline = 352,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .sizeimage = 352 * 288 * 3 / 8 + 590,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .priv = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Note some of the sizeimage values for the ov511 / ov518 may seem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) larger then necessary, however they need to be this big as the ov511 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ov518 always fills the entire isoc frame, using 0 padding bytes when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) it doesn't have any data. So with low framerates the amount of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) transferred can become quite large (libv4l will remove all the 0 padding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) in userspace). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const struct v4l2_pix_format ov518_vga_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .bytesperline = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .sizeimage = 320 * 240 * 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {640, 480, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .bytesperline = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .sizeimage = 640 * 480 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .priv = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct v4l2_pix_format ov518_sif_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {160, 120, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .bytesperline = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .sizeimage = 70000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .priv = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {176, 144, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .bytesperline = 176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .sizeimage = 70000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .bytesperline = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .sizeimage = 320 * 240 * 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .priv = 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {352, 288, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .bytesperline = 352,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .sizeimage = 352 * 288 * 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .priv = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct v4l2_pix_format ov511_vga_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {320, 240, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .bytesperline = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .sizeimage = 320 * 240 * 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {640, 480, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .bytesperline = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .sizeimage = 640 * 480 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .priv = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct v4l2_pix_format ov511_sif_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {160, 120, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .bytesperline = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .sizeimage = 70000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .priv = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {176, 144, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .bytesperline = 176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .sizeimage = 70000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {320, 240, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .bytesperline = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .sizeimage = 320 * 240 * 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .priv = 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {352, 288, V4L2_PIX_FMT_OV511, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .bytesperline = 352,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .sizeimage = 352 * 288 * 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .priv = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct v4l2_pix_format ovfx2_ov2610_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {800, 600, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .bytesperline = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .sizeimage = 800 * 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {1600, 1200, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .bytesperline = 1600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .sizeimage = 1600 * 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .colorspace = V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct v4l2_pix_format ovfx2_ov3610_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .bytesperline = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .sizeimage = 640 * 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {800, 600, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .bytesperline = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .sizeimage = 800 * 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {1024, 768, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .bytesperline = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .sizeimage = 1024 * 768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {1600, 1200, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .bytesperline = 1600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .sizeimage = 1600 * 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .priv = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {2048, 1536, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .bytesperline = 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .sizeimage = 2048 * 1536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .priv = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct v4l2_pix_format ovfx2_ov9600_mode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {640, 480, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .bytesperline = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .sizeimage = 640 * 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .priv = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {1280, 1024, V4L2_PIX_FMT_SBGGR8, V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .bytesperline = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .sizeimage = 1280 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .colorspace = V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Registers common to OV511 / OV518 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define R51x_FIFO_PSIZE 0x30 /* 2 bytes wide w/ OV518(+) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define R51x_SYS_RESET 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Reset type flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define OV511_RESET_OMNICE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define R51x_SYS_INIT 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define R51x_SYS_SNAP 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define R51x_SYS_CUST_ID 0x5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define R51x_COMP_LUT_BEGIN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* OV511 Camera interface register numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define R511_CAM_DELAY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define R511_CAM_EDGE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define R511_CAM_PXCNT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define R511_CAM_LNCNT 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define R511_CAM_PXDIV 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define R511_CAM_LNDIV 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define R511_CAM_UV_EN 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define R511_CAM_LINE_MODE 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define R511_CAM_OPTS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define R511_SNAP_FRAME 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define R511_SNAP_PXCNT 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define R511_SNAP_LNCNT 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define R511_SNAP_PXDIV 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define R511_SNAP_LNDIV 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define R511_SNAP_UV_EN 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define R511_SNAP_OPTS 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define R511_DRAM_FLOW_CTL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define R511_FIFO_OPTS 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define R511_I2C_CTL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define R511_SYS_LED_CTL 0x55 /* OV511+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define R511_COMP_EN 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define R511_COMP_LUT_EN 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* OV518 Camera interface register numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define R518_GPIO_OUT 0x56 /* OV518(+) only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define R518_GPIO_CTL 0x57 /* OV518(+) only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* OV519 Camera interface register numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define OV519_R10_H_SIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define OV519_R11_V_SIZE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define OV519_R12_X_OFFSETL 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define OV519_R13_X_OFFSETH 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define OV519_R14_Y_OFFSETL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define OV519_R15_Y_OFFSETH 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define OV519_R16_DIVIDER 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define OV519_R20_DFR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define OV519_R25_FORMAT 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* OV519 System Controller register numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define OV519_R51_RESET1 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define OV519_R54_EN_CLK1 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define OV519_R57_SNAPSHOT 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define OV519_GPIO_DATA_OUT0 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define OV519_GPIO_IO_CTRL0 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*#define OV511_ENDPOINT_ADDRESS 1 * Isoc endpoint number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * The FX2 chip does not give us a zero length read at end of frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * It does, however, give a short read at the end of a frame, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * necessary, rather than run two frames together.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * By choosing the right bulk transfer size, we are guaranteed to always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * get a short read for the last read of each frame. Frame sizes are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * always a composite number (width * height, or a multiple) so if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * choose a prime number, we are guaranteed that the last read of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * frame will be short.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * But it isn't that easy: the 2.6 kernel requires a multiple of 4KB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * otherwise EOVERFLOW "babbling" errors occur. I have not been able
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * to figure out why. [PMiller]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * The constant (13 * 4096) is the largest "prime enough" number less than 64KB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * It isn't enough to know the number of bytes per frame, in case we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * have data dropouts or buffer overruns (even though the FX2 double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * buffers, there are some pretty strict real time constraints for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * isochronous transfer for larger frame sizes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /*jfm: this value does not work for 800x600 - see isoc_init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define OVFX2_BULK_SIZE (13 * 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* I2C registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define R51x_I2C_W_SID 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define R51x_I2C_SADDR_3 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define R51x_I2C_SADDR_2 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define R51x_I2C_R_SID 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define R51x_I2C_DATA 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define R518_I2C_CTL 0x47 /* OV518(+) only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define OVFX2_I2C_ADDR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* I2C ADDRESSES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define OV7xx0_SID 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define OV_HIRES_SID 0x60 /* OV9xxx / OV2xxx / OV3xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define OV8xx0_SID 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define OV6xx0_SID 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* OV7610 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define OV7610_REG_GAIN 0x00 /* gain setting (5:0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define OV7610_REG_BLUE 0x01 /* blue channel balance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define OV7610_REG_RED 0x02 /* red channel balance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define OV7610_REG_SAT 0x03 /* saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define OV8610_REG_HUE 0x04 /* 04 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define OV7610_REG_CNT 0x05 /* Y contrast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define OV7610_REG_BRT 0x06 /* Y brightness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define OV7610_REG_COM_C 0x14 /* misc common regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define OV7610_REG_ID_HIGH 0x1c /* manufacturer ID MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define OV7610_REG_ID_LOW 0x1d /* manufacturer ID LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define OV7610_REG_COM_I 0x29 /* misc settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* OV7660 and OV7670 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define OV7670_R00_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define OV7670_R01_BLUE 0x01 /* blue gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define OV7670_R02_RED 0x02 /* red gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define OV7670_R03_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define OV7670_R04_COM1 0x04 /* Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*#define OV7670_R07_AECHH 0x07 * AEC MS 5 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define OV7670_R0C_COM3 0x0c /* Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define OV7670_R0D_COM4 0x0d /* Control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define OV7670_R0E_COM5 0x0e /* All "reserved" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define OV7670_R0F_COM6 0x0f /* Control 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define OV7670_R10_AECH 0x10 /* More bits of AEC value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define OV7670_R11_CLKRC 0x11 /* Clock control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define OV7670_R12_COM7 0x12 /* Control 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define OV7670_COM7_FMT_VGA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*#define OV7670_COM7_YUV 0x00 * YUV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define OV7670_COM7_FMT_QVGA 0x10 /* QVGA format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define OV7670_COM7_FMT_MASK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define OV7670_COM7_RESET 0x80 /* Register reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define OV7670_R13_COM8 0x13 /* Control 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define OV7670_COM8_AEC 0x01 /* Auto exposure enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define OV7670_COM8_AWB 0x02 /* White balance enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define OV7670_COM8_AGC 0x04 /* Auto gain enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define OV7670_COM8_BFILT 0x20 /* Band filter enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define OV7670_COM8_AECSTEP 0x40 /* Unlimited AEC step size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define OV7670_COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define OV7670_R14_COM9 0x14 /* Control 9 - gain ceiling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define OV7670_R15_COM10 0x15 /* Control 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define OV7670_R17_HSTART 0x17 /* Horiz start high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define OV7670_R18_HSTOP 0x18 /* Horiz stop high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define OV7670_R19_VSTART 0x19 /* Vert start high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define OV7670_R1A_VSTOP 0x1a /* Vert stop high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define OV7670_R1E_MVFP 0x1e /* Mirror / vflip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define OV7670_MVFP_VFLIP 0x10 /* vertical flip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define OV7670_MVFP_MIRROR 0x20 /* Mirror image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define OV7670_R24_AEW 0x24 /* AGC upper limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define OV7670_R25_AEB 0x25 /* AGC lower limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define OV7670_R26_VPT 0x26 /* AGC/AEC fast mode op region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define OV7670_R32_HREF 0x32 /* HREF pieces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define OV7670_R3A_TSLB 0x3a /* lots of stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define OV7670_R3B_COM11 0x3b /* Control 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define OV7670_COM11_EXP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define OV7670_COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define OV7670_R3C_COM12 0x3c /* Control 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define OV7670_R3D_COM13 0x3d /* Control 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define OV7670_COM13_GAMMA 0x80 /* Gamma enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define OV7670_COM13_UVSAT 0x40 /* UV saturation auto adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define OV7670_R3E_COM14 0x3e /* Control 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define OV7670_R3F_EDGE 0x3f /* Edge enhancement factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define OV7670_R40_COM15 0x40 /* Control 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /*#define OV7670_COM15_R00FF 0xc0 * 00 to FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define OV7670_R41_COM16 0x41 /* Control 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define OV7670_COM16_AWBGAIN 0x08 /* AWB gain enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* end of ov7660 common registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define OV7670_R55_BRIGHT 0x55 /* Brightness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define OV7670_R56_CONTRAS 0x56 /* Contrast control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define OV7670_R69_GFIX 0x69 /* Fix gain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*#define OV7670_R8C_RGB444 0x8c * RGB 444 control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define OV7670_R9F_HAECC1 0x9f /* Hist AEC/AGC control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define OV7670_RA0_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define OV7670_RA5_BD50MAX 0xa5 /* 50hz banding step limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define OV7670_RA6_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define OV7670_RA7_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define OV7670_RA8_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define OV7670_RA9_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define OV7670_RAA_HAECC7 0xaa /* Hist AEC/AGC control 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define OV7670_RAB_BD60MAX 0xab /* 60hz banding step limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct ov_regvals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct ov_i2c_regvals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Settings for OV2610 camera chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const struct ov_i2c_regvals norm_2610[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { 0x12, 0x80 }, /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const struct ov_i2c_regvals norm_2610ae[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x12, 0x80}, /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x13, 0xcd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x09, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x0d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x11, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x12, 0x20}, /* 1600x1200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x33, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x35, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x36, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* ms-win traces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x11, 0x83}, /* clock / 3 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x2d, 0x00}, /* 60 Hz filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x24, 0xb0}, /* normal colors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x25, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x10, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static const struct ov_i2c_regvals norm_3620b[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * From the datasheet: "Note that after writing to register COMH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * (0x12) to change the sensor mode, registers related to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * sensor’s cropping window will be reset back to their default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * values."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * "wait 4096 external clock ... to make sure the sensor is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * stable and ready to access registers" i.e. 160us at 24MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) { 0x12, 0x80 }, /* COMH reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { 0x12, 0x00 }, /* QXGA, master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * 11 CLKRC "Clock Rate Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * [7] internal frequency doublers: on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * [6] video port mode: master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * [5:0] clock divider: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { 0x11, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * 13 COMI "Common Control I"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * = 192 (0xC0) 11000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * COMI[7] "AEC speed selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * = 1 (0x01) 1....... "Faster AEC correction"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * COMI[6] "AEC speed step selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * = 1 (0x01) .1...... "Big steps, fast"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * COMI[5] "Banding filter on off"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * = 0 (0x00) ..0..... "Off"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * COMI[4] "Banding filter option"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * = 0 (0x00) ...0.... "Main clock is 48 MHz and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * the PLL is ON"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * COMI[3] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * = 0 (0x00) ....0...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * COMI[2] "AGC auto manual control selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * = 0 (0x00) .....0.. "Manual"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * COMI[1] "AWB auto manual control selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * = 0 (0x00) ......0. "Manual"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * COMI[0] "Exposure control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * = 0 (0x00) .......0 "Manual"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { 0x13, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * 09 COMC "Common Control C"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * = 8 (0x08) 00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * COMC[7:5] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * = 0 (0x00) 000.....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * COMC[4] "Sleep Mode Enable"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * = 0 (0x00) ...0.... "Normal mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * COMC[3:2] "Sensor sampling reset timing selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * = 2 (0x02) ....10.. "Longer reset time"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * COMC[1:0] "Output drive current select"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * = 0 (0x00) ......00 "Weakest"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) { 0x09, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * 0C COMD "Common Control D"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * = 8 (0x08) 00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * COMD[7] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * = 0 (0x00) 0.......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * COMD[6] "Swap MSB and LSB at the output port"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * = 0 (0x00) .0...... "False"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * COMD[5:3] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * = 1 (0x01) ..001...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * COMD[2] "Output Average On Off"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * = 0 (0x00) .....0.. "Output Normal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * COMD[1] "Sensor precharge voltage selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * = 0 (0x00) ......0. "Selects internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * reference precharge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * voltage"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * COMD[0] "Snapshot option"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * = 0 (0x00) .......0 "Enable live video output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * after snapshot sequence"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) { 0x0c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * 0D COME "Common Control E"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * = 161 (0xA1) 10100001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * COME[7] "Output average option"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * = 1 (0x01) 1....... "Output average of 4 pixels"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * COME[6] "Anti-blooming control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * = 0 (0x00) .0...... "Off"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * COME[5:3] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * = 4 (0x04) ..100...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * COME[2] "Clock output power down pin status"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * = 0 (0x00) .....0.. "Tri-state data output pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * on power down"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * COME[1] "Data output pin status selection at power down"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * = 0 (0x00) ......0. "Tri-state VSYNC, PCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * HREF, and CHSYNC pins on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * power down"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * COME[0] "Auto zero circuit select"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * = 1 (0x01) .......1 "On"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) { 0x0d, 0xa1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * 0E COMF "Common Control F"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * = 112 (0x70) 01110000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * COMF[7] "System clock selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * = 0 (0x00) 0....... "Use 24 MHz system clock"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * COMF[6:4] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * = 7 (0x07) .111....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * COMF[3] "Manual auto negative offset canceling selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * = 0 (0x00) ....0... "Auto detect negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * offset and cancel it"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * COMF[2:0] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * = 0 (0x00) .....000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) { 0x0e, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * 0F COMG "Common Control G"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * = 66 (0x42) 01000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * COMG[7] "Optical black output selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * = 0 (0x00) 0....... "Disable"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * COMG[6] "Black level calibrate selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * = 1 (0x01) .1...... "Use optical black pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * to calibrate"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * COMG[5:4] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * = 0 (0x00) ..00....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * COMG[3] "Channel offset adjustment"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * = 0 (0x00) ....0... "Disable offset adjustment"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * COMG[2] "ADC black level calibration option"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * = 0 (0x00) .....0.. "Use B/G line and G/R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * line to calibrate each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * channel's black level"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * COMG[1] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * = 1 (0x01) ......1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * COMG[0] "ADC black level calibration enable"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * = 0 (0x00) .......0 "Disable"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) { 0x0f, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * 14 COMJ "Common Control J"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * = 198 (0xC6) 11000110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * COMJ[7:6] "AGC gain ceiling"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * = 3 (0x03) 11...... "8x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * COMJ[5:4] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * = 0 (0x00) ..00....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * COMJ[3] "Auto banding filter"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * = 0 (0x00) ....0... "Banding filter is always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * on off depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * COMI[5] setting"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * COMJ[2] "VSYNC drop option"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * = 1 (0x01) .....1.. "SYNC is dropped if frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * data is dropped"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * COMJ[1] "Frame data drop"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * = 1 (0x01) ......1. "Drop frame data if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * exposure is not within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * tolerance. In AEC mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * data is normally dropped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * when data is out of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * range."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * COMJ[0] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * = 0 (0x00) .......0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) { 0x14, 0xc6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * 15 COMK "Common Control K"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * = 2 (0x02) 00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * COMK[7] "CHSYNC pin output swap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * = 0 (0x00) 0....... "CHSYNC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * COMK[6] "HREF pin output swap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * = 0 (0x00) .0...... "HREF"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * COMK[5] "PCLK output selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * = 0 (0x00) ..0..... "PCLK always output"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * COMK[4] "PCLK edge selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * = 0 (0x00) ...0.... "Data valid on falling edge"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * COMK[3] "HREF output polarity"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * = 0 (0x00) ....0... "positive"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * COMK[2] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * = 0 (0x00) .....0..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * COMK[1] "VSYNC polarity"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * = 1 (0x01) ......1. "negative"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * COMK[0] "HSYNC polarity"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * = 0 (0x00) .......0 "positive"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) { 0x15, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * 33 CHLF "Current Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * = 9 (0x09) 00001001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * CHLF[7:6] "Sensor current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * = 0 (0x00) 00......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * CHLF[5] "Sensor current range control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * = 0 (0x00) ..0..... "normal range"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * CHLF[4] "Sensor current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * = 0 (0x00) ...0.... "normal current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * CHLF[3] "Sensor buffer current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * = 1 (0x01) ....1... "half current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * CHLF[2] "Column buffer current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * = 0 (0x00) .....0.. "normal current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * CHLF[1] "Analog DSP current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * = 0 (0x00) ......0. "normal current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * CHLF[1] "ADC current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * = 0 (0x00) ......0. "normal current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { 0x33, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * 34 VBLM "Blooming Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * = 80 (0x50) 01010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * VBLM[7] "Hard soft reset switch"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * = 0 (0x00) 0....... "Hard reset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * VBLM[6:4] "Blooming voltage selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * = 5 (0x05) .101....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * VBLM[3:0] "Sensor current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * = 0 (0x00) ....0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) { 0x34, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * 36 VCHG "Sensor Precharge Voltage Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * VCHG[7] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * = 0 (0x00) 0.......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * VCHG[6:4] "Sensor precharge voltage control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * = 0 (0x00) .000....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * VCHG[3:0] "Sensor array common reference"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * = 0 (0x00) ....0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) { 0x36, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * 37 ADC "ADC Reference Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * = 4 (0x04) 00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * ADC[7:4] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * = 0 (0x00) 0000....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * ADC[3] "ADC input signal range"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * = 0 (0x00) ....0... "Input signal 1.0x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * ADC[2:0] "ADC range control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * = 4 (0x04) .....100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) { 0x37, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * 38 ACOM "Analog Common Ground"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * = 82 (0x52) 01010010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * ACOM[7] "Analog gain control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * = 0 (0x00) 0....... "Gain 1x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * ACOM[6] "Analog black level calibration"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * = 1 (0x01) .1...... "On"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * ACOM[5:0] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * = 18 (0x12) ..010010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) { 0x38, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * 3A FREFA "Internal Reference Adjustment"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * FREFA[7:0] "Range"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) { 0x3a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * 3C FVOPT "Internal Reference Adjustment"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * = 31 (0x1F) 00011111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * FVOPT[7:0] "Range"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * = 31 (0x1F) 00011111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) { 0x3c, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * 44 Undocumented = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * 44[7:0] "It's a secret"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) { 0x44, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * 40 Undocumented = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * 40[7:0] "It's a secret"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) { 0x40, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * 41 Undocumented = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * 41[7:0] "It's a secret"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) { 0x41, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * 42 Undocumented = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * 42[7:0] "It's a secret"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) { 0x42, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * 43 Undocumented = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * 43[7:0] "It's a secret"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) { 0x43, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * 45 Undocumented = 128 (0x80) 10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * 45[7:0] "It's a secret"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * = 128 (0x80) 10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) { 0x45, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * 48 Undocumented = 192 (0xC0) 11000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * 48[7:0] "It's a secret"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * = 192 (0xC0) 11000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) { 0x48, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * 49 Undocumented = 25 (0x19) 00011001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * 49[7:0] "It's a secret"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * = 25 (0x19) 00011001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) { 0x49, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * 4B Undocumented = 128 (0x80) 10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * 4B[7:0] "It's a secret"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * = 128 (0x80) 10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) { 0x4b, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * 4D Undocumented = 196 (0xC4) 11000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * 4D[7:0] "It's a secret"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * = 196 (0xC4) 11000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) { 0x4d, 0xc4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * 35 VREF "Reference Voltage Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * = 76 (0x4c) 01001100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * VREF[7:5] "Column high reference control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * = 2 (0x02) 010..... "higher voltage"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * VREF[4:2] "Column low reference control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * = 3 (0x03) ...011.. "Highest voltage"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * VREF[1:0] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * = 0 (0x00) ......00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) { 0x35, 0x4c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * 3D Undocumented = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * 3D[7:0] "It's a secret"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) { 0x3d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * 3E Undocumented = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * 3E[7:0] "It's a secret"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) { 0x3e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * 3B FREFB "Internal Reference Adjustment"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * = 24 (0x18) 00011000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * FREFB[7:0] "Range"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * = 24 (0x18) 00011000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) { 0x3b, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * 33 CHLF "Current Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * = 25 (0x19) 00011001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * CHLF[7:6] "Sensor current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * = 0 (0x00) 00......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * CHLF[5] "Sensor current range control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * = 0 (0x00) ..0..... "normal range"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * CHLF[4] "Sensor current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * = 1 (0x01) ...1.... "double current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * CHLF[3] "Sensor buffer current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * = 1 (0x01) ....1... "half current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * CHLF[2] "Column buffer current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * = 0 (0x00) .....0.. "normal current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * CHLF[1] "Analog DSP current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * = 0 (0x00) ......0. "normal current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * CHLF[1] "ADC current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * = 0 (0x00) ......0. "normal current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) { 0x33, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * 34 VBLM "Blooming Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * = 90 (0x5A) 01011010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * VBLM[7] "Hard soft reset switch"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * = 0 (0x00) 0....... "Hard reset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * VBLM[6:4] "Blooming voltage selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * = 5 (0x05) .101....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * VBLM[3:0] "Sensor current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * = 10 (0x0A) ....1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) { 0x34, 0x5a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * 3B FREFB "Internal Reference Adjustment"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * FREFB[7:0] "Range"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) { 0x3b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * 33 CHLF "Current Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * = 9 (0x09) 00001001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * CHLF[7:6] "Sensor current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * = 0 (0x00) 00......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * CHLF[5] "Sensor current range control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * = 0 (0x00) ..0..... "normal range"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * CHLF[4] "Sensor current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * = 0 (0x00) ...0.... "normal current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * CHLF[3] "Sensor buffer current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * = 1 (0x01) ....1... "half current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * CHLF[2] "Column buffer current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * = 0 (0x00) .....0.. "normal current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * CHLF[1] "Analog DSP current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * = 0 (0x00) ......0. "normal current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * CHLF[1] "ADC current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * = 0 (0x00) ......0. "normal current"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) { 0x33, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * 34 VBLM "Blooming Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * = 80 (0x50) 01010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * VBLM[7] "Hard soft reset switch"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * = 0 (0x00) 0....... "Hard reset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * VBLM[6:4] "Blooming voltage selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * = 5 (0x05) .101....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * VBLM[3:0] "Sensor current control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * = 0 (0x00) ....0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) { 0x34, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * 12 COMH "Common Control H"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * = 64 (0x40) 01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * COMH[7] "SRST"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * = 0 (0x00) 0....... "No-op"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * COMH[6:4] "Resolution selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * = 4 (0x04) .100.... "XGA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * COMH[3] "Master slave selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * = 0 (0x00) ....0... "Master mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * COMH[2] "Internal B/R channel option"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * = 0 (0x00) .....0.. "B/R use same channel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * COMH[1] "Color bar test pattern"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * = 0 (0x00) ......0. "Off"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * COMH[0] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * = 0 (0x00) .......0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) { 0x12, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * 17 HREFST "Horizontal window start"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * = 31 (0x1F) 00011111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * HREFST[7:0] "Horizontal window start, 8 MSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * = 31 (0x1F) 00011111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) { 0x17, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * 18 HREFEND "Horizontal window end"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * = 95 (0x5F) 01011111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * HREFEND[7:0] "Horizontal Window End, 8 MSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * = 95 (0x5F) 01011111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) { 0x18, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * 19 VSTRT "Vertical window start"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * VSTRT[7:0] "Vertical Window Start, 8 MSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) { 0x19, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * 1A VEND "Vertical window end"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * = 96 (0x60) 01100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * VEND[7:0] "Vertical Window End, 8 MSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * = 96 (0x60) 01100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) { 0x1a, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * 32 COMM "Common Control M"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * = 18 (0x12) 00010010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * COMM[7:6] "Pixel clock divide option"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * = 0 (0x00) 00...... "/1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * COMM[5:3] "Horizontal window end position, 3 LSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * = 2 (0x02) ..010...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * COMM[2:0] "Horizontal window start position, 3 LSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * = 2 (0x02) .....010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) { 0x32, 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * 03 COMA "Common Control A"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * = 74 (0x4A) 01001010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * COMA[7:4] "AWB Update Threshold"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * = 4 (0x04) 0100....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * COMA[3:2] "Vertical window end line control 2 LSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * = 2 (0x02) ....10..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * COMA[1:0] "Vertical window start line control 2 LSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * = 2 (0x02) ......10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) { 0x03, 0x4a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * 11 CLKRC "Clock Rate Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * = 128 (0x80) 10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * CLKRC[7] "Internal frequency doublers on off seclection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * = 1 (0x01) 1....... "On"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * CLKRC[6] "Digital video master slave selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * = 0 (0x00) .0...... "Master mode, sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * provides PCLK"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * CLKRC[5:0] "Clock divider { CLK = PCLK/(1+CLKRC[5:0]) }"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * = 0 (0x00) ..000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) { 0x11, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * 12 COMH "Common Control H"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * COMH[7] "SRST"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * = 0 (0x00) 0....... "No-op"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * COMH[6:4] "Resolution selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * = 0 (0x00) .000.... "QXGA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * COMH[3] "Master slave selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * = 0 (0x00) ....0... "Master mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * COMH[2] "Internal B/R channel option"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * = 0 (0x00) .....0.. "B/R use same channel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * COMH[1] "Color bar test pattern"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * = 0 (0x00) ......0. "Off"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * COMH[0] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * = 0 (0x00) .......0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) { 0x12, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * 12 COMH "Common Control H"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * = 64 (0x40) 01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * COMH[7] "SRST"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * = 0 (0x00) 0....... "No-op"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * COMH[6:4] "Resolution selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * = 4 (0x04) .100.... "XGA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * COMH[3] "Master slave selection"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * = 0 (0x00) ....0... "Master mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * COMH[2] "Internal B/R channel option"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * = 0 (0x00) .....0.. "B/R use same channel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * COMH[1] "Color bar test pattern"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * = 0 (0x00) ......0. "Off"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * COMH[0] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * = 0 (0x00) .......0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) { 0x12, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * 17 HREFST "Horizontal window start"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * = 31 (0x1F) 00011111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * HREFST[7:0] "Horizontal window start, 8 MSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * = 31 (0x1F) 00011111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) { 0x17, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * 18 HREFEND "Horizontal window end"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * = 95 (0x5F) 01011111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * HREFEND[7:0] "Horizontal Window End, 8 MSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * = 95 (0x5F) 01011111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) { 0x18, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * 19 VSTRT "Vertical window start"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * VSTRT[7:0] "Vertical Window Start, 8 MSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * = 0 (0x00) 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) { 0x19, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * 1A VEND "Vertical window end"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * = 96 (0x60) 01100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * VEND[7:0] "Vertical Window End, 8 MSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * = 96 (0x60) 01100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) { 0x1a, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * 32 COMM "Common Control M"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * = 18 (0x12) 00010010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * COMM[7:6] "Pixel clock divide option"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * = 0 (0x00) 00...... "/1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * COMM[5:3] "Horizontal window end position, 3 LSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * = 2 (0x02) ..010...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * COMM[2:0] "Horizontal window start position, 3 LSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * = 2 (0x02) .....010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) { 0x32, 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * 03 COMA "Common Control A"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * = 74 (0x4A) 01001010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * COMA[7:4] "AWB Update Threshold"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * = 4 (0x04) 0100....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * COMA[3:2] "Vertical window end line control 2 LSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * = 2 (0x02) ....10..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * COMA[1:0] "Vertical window start line control 2 LSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * = 2 (0x02) ......10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) { 0x03, 0x4a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * 02 RED "Red Gain Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * = 175 (0xAF) 10101111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * RED[7] "Action"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * = 1 (0x01) 1....... "gain = 1/(1+bitrev([6:0]))"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * RED[6:0] "Value"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * = 47 (0x2F) .0101111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) { 0x02, 0xaf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * 2D ADDVSL "VSYNC Pulse Width"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * = 210 (0xD2) 11010010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * ADDVSL[7:0] "VSYNC pulse width, LSB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * = 210 (0xD2) 11010010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) { 0x2d, 0xd2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * 00 GAIN = 24 (0x18) 00011000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * GAIN[7:6] "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * = 0 (0x00) 00......
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * GAIN[5] "Double"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * = 0 (0x00) ..0..... "False"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * GAIN[4] "Double"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * = 1 (0x01) ...1.... "True"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * GAIN[3:0] "Range"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * = 8 (0x08) ....1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) { 0x00, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * 01 BLUE "Blue Gain Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * = 240 (0xF0) 11110000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * BLUE[7] "Action"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * = 1 (0x01) 1....... "gain = 1/(1+bitrev([6:0]))"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * BLUE[6:0] "Value"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * = 112 (0x70) .1110000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) { 0x01, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * 10 AEC "Automatic Exposure Control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * = 10 (0x0A) 00001010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * AEC[7:0] "Automatic Exposure Control, 8 MSBs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * = 10 (0x0A) 00001010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) { 0x10, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) { 0xe1, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) { 0xe3, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) { 0xe4, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) { 0xe5, 0x3e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) { 0xf8, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) { 0xff, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static const struct ov_i2c_regvals norm_6x20[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) { 0x12, 0x80 }, /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) { 0x11, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) { 0x03, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) { 0x05, 0x7f }, /* For when autoadjust is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) { 0x07, 0xa8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /* The ratio of 0x0c and 0x0d controls the white point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) { 0x0c, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) { 0x0d, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) { 0x0f, 0x15 }, /* COMS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) { 0x10, 0x75 }, /* AEC Exposure time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) { 0x12, 0x24 }, /* Enable AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) { 0x14, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* 0x16: 0x06 helps frame stability with moving objects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) { 0x16, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* { 0x20, 0x30 }, * Aperture correction enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) { 0x26, 0xb2 }, /* BLC enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* 0x28: 0x05 Selects RGB format if RGB on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) { 0x28, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) { 0x2a, 0x04 }, /* Disable framerate adjust */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* { 0x2b, 0xac }, * Framerate; Set 2a[7] first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) { 0x2d, 0x85 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) { 0x33, 0xa0 }, /* Color Processing Parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) { 0x34, 0xd2 }, /* Max A/D range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) { 0x38, 0x8b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) { 0x39, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) { 0x3c, 0x39 }, /* Enable AEC mode changing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) { 0x3c, 0x3c }, /* Change AEC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) { 0x3c, 0x24 }, /* Disable AEC mode changing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) { 0x3d, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* These next two registers (0x4a, 0x4b) are undocumented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * They control the color balance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) { 0x4a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) { 0x4b, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) { 0x4d, 0xd2 }, /* This reduces noise a bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) { 0x4e, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) { 0x4f, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* Do 50-53 have any effect? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* Toggle 0x12[2] off and on here? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static const struct ov_i2c_regvals norm_6x30[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) { 0x12, 0x80 }, /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) { 0x00, 0x1f }, /* Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) { 0x01, 0x99 }, /* Blue gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) { 0x02, 0x7c }, /* Red gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) { 0x03, 0xc0 }, /* Saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) { 0x05, 0x0a }, /* Contrast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) { 0x06, 0x95 }, /* Brightness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) { 0x07, 0x2d }, /* Sharpness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) { 0x0c, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) { 0x0d, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) { 0x0e, 0xa0 }, /* Was 0x20, bit7 enables a 2x gain which we need */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) { 0x0f, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) { 0x10, 0x9a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) { 0x11, 0x00 }, /* Pixel clock = fastest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) { 0x12, 0x24 }, /* Enable AGC and AWB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) { 0x13, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) { 0x14, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) { 0x15, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) { 0x16, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) { 0x17, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) { 0x18, 0xea },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) { 0x19, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) { 0x1a, 0x93 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) { 0x1b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) { 0x1e, 0xc4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) { 0x1f, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) { 0x20, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) { 0x21, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) { 0x22, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) { 0x23, 0xc0 }, /* Crystal circuit power level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) { 0x25, 0x9a }, /* Increase AEC black ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) { 0x26, 0xb2 }, /* BLC enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) { 0x27, 0xa2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) { 0x28, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) { 0x29, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) { 0x2a, 0x84 }, /* 60 Hz power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) { 0x2b, 0xa8 }, /* 60 Hz power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) { 0x2c, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) { 0x2d, 0x95 }, /* Enable auto-brightness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) { 0x2e, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) { 0x33, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) { 0x34, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) { 0x36, 0x8f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) { 0x37, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) { 0x38, 0x83 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) { 0x39, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) { 0x3a, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) { 0x3b, 0x3c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) { 0x3c, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) { 0x3d, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) { 0x3e, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) { 0x3f, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) { 0x40, 0x00 }, /* White bal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) { 0x41, 0x00 }, /* White bal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) { 0x42, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) { 0x43, 0x3f }, /* White bal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) { 0x44, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) { 0x45, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) { 0x46, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) { 0x47, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) { 0x48, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) { 0x49, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) { 0x4a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) { 0x4b, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) { 0x4c, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) { 0x4d, 0x10 }, /* U = 0.563u, V = 0.714v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) { 0x4e, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) { 0x4f, 0x07 }, /* UV avg., col. killer: max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) { 0x50, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) { 0x54, 0x23 }, /* Max AGC gain: 18dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) { 0x55, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) { 0x56, 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) { 0x57, 0x81 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) { 0x58, 0x75 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) { 0x59, 0x01 }, /* AGC dark current comp.: +1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) { 0x5a, 0x2c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) { 0x5b, 0x0f }, /* AWB chrominance levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) { 0x5c, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) { 0x3d, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) { 0x27, 0xa6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) { 0x12, 0x20 }, /* Toggle AWB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) { 0x12, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* Lawrence Glaister <lg@jfm.bc.ca> reports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) * Register 0x0f in the 7610 has the following effects:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * 0x85 (AEC method 1): Best overall, good contrast range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * 0x45 (AEC method 2): Very overexposed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * 0xa5 (spec sheet default): Ok, but the black level is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * shifted resulting in loss of contrast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * 0x05 (old driver setting): very overexposed, too much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) * contrast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static const struct ov_i2c_regvals norm_7610[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) { 0x10, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) { 0x16, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) { 0x28, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) { 0x2b, 0xac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) { 0x12, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) { 0x38, 0x81 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) { 0x28, 0x24 }, /* 0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) { 0x0f, 0x85 }, /* lg's setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) { 0x15, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) { 0x20, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) { 0x23, 0x2a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) { 0x24, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) { 0x25, 0x8a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) { 0x26, 0xa2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) { 0x27, 0xc2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) { 0x2a, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) { 0x2c, 0xfe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) { 0x2d, 0x93 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) { 0x30, 0x71 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) { 0x31, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) { 0x32, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) { 0x33, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) { 0x34, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) { 0x12, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) { 0x11, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) { 0x0c, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) { 0x0d, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static const struct ov_i2c_regvals norm_7620[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) { 0x12, 0x80 }, /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) { 0x00, 0x00 }, /* gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) { 0x01, 0x80 }, /* blue gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) { 0x02, 0x80 }, /* red gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) { 0x03, 0xc0 }, /* OV7670_R03_VREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) { 0x06, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) { 0x07, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) { 0x0c, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) { 0x0c, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) { 0x0d, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) { 0x11, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) { 0x12, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) { 0x13, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) { 0x14, 0x84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) { 0x15, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) { 0x16, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) { 0x17, 0x2f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) { 0x18, 0xcf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) { 0x19, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) { 0x1a, 0xf5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) { 0x1b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) { 0x20, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) { 0x21, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) { 0x22, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) { 0x23, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) { 0x26, 0xa2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) { 0x27, 0xea },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) { 0x28, 0x22 }, /* Was 0x20, bit1 enables a 2x gain which we need */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) { 0x29, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) { 0x2a, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) { 0x2b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) { 0x2c, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) { 0x2d, 0x91 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) { 0x2e, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) { 0x2f, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) { 0x60, 0x27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) { 0x61, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) { 0x62, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) { 0x63, 0xd5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) { 0x64, 0x57 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) { 0x65, 0x83 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) { 0x66, 0x55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) { 0x67, 0x92 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) { 0x68, 0xcf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) { 0x69, 0x76 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) { 0x6a, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) { 0x6b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) { 0x6c, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) { 0x6d, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) { 0x6e, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) { 0x6f, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) { 0x70, 0x8b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) { 0x71, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) { 0x72, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) { 0x73, 0x54 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) { 0x74, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) { 0x75, 0x8e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) { 0x76, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) { 0x77, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) { 0x78, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) { 0x79, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) { 0x7a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) { 0x7b, 0xe2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) { 0x7c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /* 7640 and 7648. The defaults should be OK for most registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static const struct ov_i2c_regvals norm_7640[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) { 0x12, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) { 0x12, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static const struct ov_regvals init_519_ov7660[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) { 0x5d, 0x03 }, /* Turn off suspend mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) { 0x53, 0x9b }, /* 0x9f enables the (unused) microcontroller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) { 0x54, 0x0f }, /* bit2 (jpeg enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) { 0xa2, 0x20 }, /* a2-a5 are undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) { 0xa3, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) { 0xa4, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) { 0xa5, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) { 0x37, 0x00 }, /* SetUsbInit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /* Enable both fields, YUV Input, disable defect comp (why?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) { 0x20, 0x0c }, /* 0x0d does U <-> V swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) { 0x21, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) { 0x22, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) { 0x17, 0x50 }, /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) { 0x37, 0x00 }, /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) { 0x40, 0xff }, /* I2C timeout counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) { 0x46, 0x00 }, /* I2C clock prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static const struct ov_i2c_regvals norm_7660[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) {OV7670_R12_COM7, OV7670_COM7_RESET},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) {OV7670_R11_CLKRC, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) {0x92, 0x00}, /* DM_LNL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) {0x93, 0x00}, /* DM_LNH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) {0x9d, 0x4c}, /* BD50ST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) {0x9e, 0x3f}, /* BD60ST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) {OV7670_R3B_COM11, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) {OV7670_R13_COM8, 0xf5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) {OV7670_R10_AECH, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {OV7670_R00_GAIN, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {OV7670_R01_BLUE, 0x7c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) {OV7670_R02_RED, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) {OV7670_R12_COM7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) {OV7670_R04_COM1, 00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {OV7670_R18_HSTOP, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) {OV7670_R17_HSTART, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) {OV7670_R32_HREF, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) {OV7670_R19_VSTART, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) {OV7670_R1A_VSTOP, 0x7a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {OV7670_R03_VREF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) {OV7670_R0E_COM5, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) {OV7670_R0F_COM6, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {OV7670_R15_COM10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) {0x16, 0x02}, /* RSVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) {0x1b, 0x00}, /* PSHFT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) {OV7670_R1E_MVFP, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) {0x29, 0x3c}, /* RSVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) {0x33, 0x00}, /* CHLF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) {0x34, 0x07}, /* ARBLM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) {0x35, 0x84}, /* RSVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {0x36, 0x00}, /* RSVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) {0x37, 0x04}, /* ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {0x39, 0x43}, /* OFON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) {OV7670_R3A_TSLB, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) {OV7670_R3C_COM12, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {OV7670_R3D_COM13, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) {OV7670_R3F_EDGE, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {OV7670_R40_COM15, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {OV7670_R41_COM16, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) {0x6b, 0x0a}, /* DBLV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) {0xa1, 0x08}, /* RSVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) {0x69, 0x80}, /* HV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {0x43, 0xf0}, /* RSVD.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) {0x44, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) {0x45, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) {0x46, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) {0x47, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) {0x48, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {0x59, 0xba},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) {0x5a, 0x9a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {0x5b, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {0x5c, 0xb9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {0x5d, 0x9b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) {0x5e, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) {0x5f, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) {0x60, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {0x61, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) {0x9f, 0x9d}, /* RSVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) {0xa0, 0xa0}, /* DSPC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) {0x4f, 0x60}, /* matrix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) {0x50, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {0x51, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {0x52, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) {0x53, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) {0x54, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {0x55, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) {0x56, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) {0x57, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {0x58, 0x0d}, /* matrix sign */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) {0x8b, 0xcc}, /* RSVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) {0x8c, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) {0x8d, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) {0x6c, 0x40}, /* gamma curve */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) {0x6d, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) {0x6e, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) {0x6f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) {0x70, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) {0x71, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) {0x72, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) {0x73, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) {0x74, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) {0x75, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {0x76, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) {0x77, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {0x78, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) {0x79, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) {0x7a, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) {0x7b, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) {0x7c, 0x04}, /* gamma curve */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {0x7d, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) {0x7e, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) {0x7f, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {0x80, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) {0x81, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) {0x82, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) {0x83, 0x7c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {0x84, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) {0x85, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) {0x86, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) {0x87, 0xab},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) {0x88, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) {0x89, 0xd1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) {0x8a, 0xe5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) {OV7670_R14_COM9, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {OV7670_R24_AEW, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) {OV7670_R25_AEB, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) {OV7670_R26_VPT, 0xb3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) {0x62, 0x80}, /* LCC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {0x63, 0x80}, /* LCC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) {0x64, 0x06}, /* LCC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {0x65, 0x00}, /* LCC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) {0x66, 0x01}, /* LCC5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) {0x94, 0x0e}, /* RSVD.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) {0x95, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) {OV7670_R13_COM8, OV7670_COM8_FASTAEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) | OV7670_COM8_AECSTEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) | OV7670_COM8_BFILT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) | 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) | OV7670_COM8_AGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) | OV7670_COM8_AWB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) | OV7670_COM8_AEC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) {0xa1, 0xc8}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static const struct ov_i2c_regvals norm_9600[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) {0x12, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) {0x0c, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) {0x11, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {0x13, 0xb5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {0x14, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) {0x1b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) {0x24, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) {0x25, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) {0x26, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) {0x35, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) {0x37, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) {0x38, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {0x01, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) {0x02, 0x85}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /* 7670. Defaults taken from OmniVision provided data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) * as provided by Jonathan Corbet of OLPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static const struct ov_i2c_regvals norm_7670[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) { OV7670_R12_COM7, OV7670_COM7_RESET },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) { OV7670_R3A_TSLB, 0x04 }, /* OV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) { OV7670_R12_COM7, OV7670_COM7_FMT_VGA }, /* VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) { OV7670_R11_CLKRC, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) * Set the hardware window. These values from OV don't entirely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) * make sense - hstop is less than hstart. But they work...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) { OV7670_R17_HSTART, 0x13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) { OV7670_R18_HSTOP, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) { OV7670_R32_HREF, 0xb6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) { OV7670_R19_VSTART, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) { OV7670_R1A_VSTOP, 0x7a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) { OV7670_R03_VREF, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) { OV7670_R0C_COM3, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) { OV7670_R3E_COM14, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) /* Mystery scaling numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) { 0x70, 0x3a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) { 0x71, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) { 0x72, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) { 0x73, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) { 0xa2, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) /* { OV7670_R15_COM10, 0x0 }, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) /* Gamma curve values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) { 0x7a, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) { 0x7b, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) { 0x7c, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) { 0x7d, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) { 0x7e, 0x5a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) { 0x7f, 0x69 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) { 0x80, 0x76 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) { 0x81, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) { 0x82, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) { 0x83, 0x8f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) { 0x84, 0x96 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) { 0x85, 0xa3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) { 0x86, 0xaf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) { 0x87, 0xc4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) { 0x88, 0xd7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) { 0x89, 0xe8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* AGC and AEC parameters. Note we start by disabling those features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) then turn them only after tweaking the values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) { OV7670_R13_COM8, OV7670_COM8_FASTAEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) | OV7670_COM8_AECSTEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) | OV7670_COM8_BFILT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) { OV7670_R00_GAIN, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) { OV7670_R10_AECH, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) { OV7670_R0D_COM4, 0x40 }, /* magic reserved bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) { OV7670_R14_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) { OV7670_RA5_BD50MAX, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) { OV7670_RAB_BD60MAX, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) { OV7670_R24_AEW, 0x95 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) { OV7670_R25_AEB, 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) { OV7670_R26_VPT, 0xe3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) { OV7670_R9F_HAECC1, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) { OV7670_RA0_HAECC2, 0x68 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) { 0xa1, 0x03 }, /* magic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) { OV7670_RA6_HAECC3, 0xd8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) { OV7670_RA7_HAECC4, 0xd8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) { OV7670_RA8_HAECC5, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) { OV7670_RA9_HAECC6, 0x90 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) { OV7670_RAA_HAECC7, 0x94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) { OV7670_R13_COM8, OV7670_COM8_FASTAEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) | OV7670_COM8_AECSTEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) | OV7670_COM8_BFILT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) | OV7670_COM8_AGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) | OV7670_COM8_AEC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* Almost all of these are magic "reserved" values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) { OV7670_R0E_COM5, 0x61 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) { OV7670_R0F_COM6, 0x4b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) { 0x16, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) { OV7670_R1E_MVFP, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) { 0x21, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) { 0x22, 0x91 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) { 0x29, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) { 0x33, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) { 0x35, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) { 0x37, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) { 0x38, 0x71 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) { 0x39, 0x2a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) { OV7670_R3C_COM12, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) { 0x4d, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) { 0x4e, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) { OV7670_R69_GFIX, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) { 0x6b, 0x4a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) { 0x74, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) { 0x8d, 0x4f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) { 0x8e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) { 0x8f, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) { 0x90, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) { 0x91, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) { 0x96, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) { 0x9a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) { 0xb0, 0x84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) { 0xb1, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) { 0xb2, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) { 0xb3, 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) { 0xb8, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /* More reserved magic, some of which tweaks white balance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) { 0x43, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) { 0x44, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) { 0x45, 0x34 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) { 0x46, 0x58 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) { 0x47, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) { 0x48, 0x3a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) { 0x59, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) { 0x5a, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) { 0x5b, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) { 0x5c, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) { 0x5d, 0x49 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) { 0x5e, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) { 0x6c, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) { 0x6d, 0x55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) { 0x6e, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) { 0x6f, 0x9f }, /* "9e for advance AWB" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) { 0x6a, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) { OV7670_R01_BLUE, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) { OV7670_R02_RED, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) { OV7670_R13_COM8, OV7670_COM8_FASTAEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) | OV7670_COM8_AECSTEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) | OV7670_COM8_BFILT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) | OV7670_COM8_AGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) | OV7670_COM8_AEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) | OV7670_COM8_AWB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) /* Matrix coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) { 0x4f, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) { 0x50, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) { 0x51, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) { 0x52, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) { 0x53, 0x5e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) { 0x54, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) { 0x58, 0x9e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) { OV7670_R41_COM16, OV7670_COM16_AWBGAIN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) { OV7670_R3F_EDGE, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) { 0x75, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) { 0x76, 0xe1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) { 0x4c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) { 0x77, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) { OV7670_R3D_COM13, OV7670_COM13_GAMMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) | OV7670_COM13_UVSAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) | 2}, /* was 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) { 0x4b, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) { 0xc9, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) { OV7670_R41_COM16, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) { 0x56, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) { 0x34, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) { OV7670_R3B_COM11, OV7670_COM11_EXP|OV7670_COM11_HZAUTO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) { 0xa4, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) { 0x96, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) { 0x97, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) { 0x98, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) { 0x99, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) { 0x9a, 0x84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) { 0x9b, 0x29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) { 0x9c, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) { 0x9d, 0x4c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) { 0x9e, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) { 0x78, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /* Extra-weird stuff. Some sort of multiplexor register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) { 0x79, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) { 0xc8, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) { 0x79, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) { 0xc8, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) { 0x79, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) { 0xc8, 0x7e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) { 0x79, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) { 0xc8, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) { 0x79, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) { 0xc8, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) { 0x79, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) { 0xc8, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) { 0x79, 0x0d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) { 0xc8, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) { 0x79, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) { 0xc8, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) { 0x79, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) { 0xc8, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) { 0x79, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) { 0xc8, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) { 0x79, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) { 0xc8, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) { 0x79, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) static const struct ov_i2c_regvals norm_8610[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) { 0x12, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) { 0x00, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) { 0x01, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) { 0x02, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) { 0x03, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) { 0x04, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) { 0x05, 0x30 }, /* was 0x10, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) { 0x06, 0x70 }, /* was 0x80, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) { 0x0a, 0x86 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) { 0x0b, 0xb0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) { 0x0c, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) { 0x0d, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) { 0x11, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) { 0x12, 0x25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) { 0x13, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) { 0x14, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) { 0x15, 0x01 }, /* Lin and Win think different about UV order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) { 0x16, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) { 0x17, 0x38 }, /* was 0x2f, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) { 0x18, 0xea }, /* was 0xcf, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) { 0x19, 0x02 }, /* was 0x06, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) { 0x1a, 0xf5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) { 0x1b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) { 0x20, 0xd0 }, /* was 0x90, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) { 0x23, 0xc0 }, /* was 0x00, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) { 0x24, 0x30 }, /* was 0x1d, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) { 0x25, 0x50 }, /* was 0x57, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) { 0x26, 0xa2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) { 0x27, 0xea },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) { 0x28, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) { 0x29, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) { 0x2a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) { 0x2b, 0xc8 }, /* was 0xcc, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) { 0x2c, 0xac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) { 0x2d, 0x45 }, /* was 0xd5, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) { 0x2e, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) { 0x2f, 0x14 }, /* was 0x01, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) { 0x4c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) { 0x4d, 0x30 }, /* was 0x10, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) { 0x60, 0x02 }, /* was 0x01, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) { 0x61, 0x00 }, /* was 0x09, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) { 0x62, 0x5f }, /* was 0xd7, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) { 0x63, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) { 0x64, 0x53 }, /* new windrv 090403 says 0x57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) * maybe that's wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) { 0x65, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) { 0x66, 0x55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) { 0x67, 0xb0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) { 0x68, 0xc0 }, /* was 0xaf, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) { 0x69, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) { 0x6a, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) { 0x6b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) { 0x6c, 0x99 }, /* was 0x80, old windrv says 0x00, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) * deleting bit7 colors the first images red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) { 0x6d, 0x11 }, /* was 0x00, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) { 0x6e, 0x11 }, /* was 0x00, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) { 0x6f, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) { 0x70, 0x8b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) { 0x71, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) { 0x72, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) { 0x73, 0x54 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) { 0x74, 0x00 },/* 0x60? - was 0x00, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) { 0x75, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) { 0x76, 0x02 }, /* was 0x02, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) { 0x77, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) { 0x78, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) { 0x79, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) { 0x7a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) { 0x7b, 0x10 }, /* was 0x13, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) { 0x7c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) { 0x7d, 0x08 }, /* was 0x09, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) { 0x7e, 0x08 }, /* was 0xc0, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) { 0x7f, 0xfb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) { 0x80, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) { 0x81, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) { 0x82, 0x23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) { 0x83, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) { 0x84, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) { 0x85, 0x62 }, /* was 0x61, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) { 0x86, 0xc9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) { 0x87, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) { 0x88, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) { 0x89, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) { 0x12, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) { 0x12, 0x25 }, /* was 0x24, new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) static unsigned char ov7670_abs_to_sm(unsigned char v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) if (v > 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) return v & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) return (128 - v) | 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /* Write a OV519 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) static void reg_w(struct sd *sd, u16 index, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) int ret, req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (sd->gspca_dev.usb_err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) /* Avoid things going to fast for the bridge with a xhci host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) req = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) case BRIDGE_OVFX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) req = 0x0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) case BRIDGE_W9968CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) gspca_dbg(gspca_dev, D_USBO, "SET %02x %04x %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) req, value, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) ret = usb_control_msg(sd->gspca_dev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) usb_sndctrlpipe(sd->gspca_dev.dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) value, index, NULL, 0, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) goto leave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) gspca_dbg(gspca_dev, D_USBO, "SET %02x 0000 %04x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) req, index, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) sd->gspca_dev.usb_buf[0] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) ret = usb_control_msg(sd->gspca_dev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) usb_sndctrlpipe(sd->gspca_dev.dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) 0, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) sd->gspca_dev.usb_buf, 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) leave:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) gspca_err(gspca_dev, "reg_w %02x failed %d\n", index, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) sd->gspca_dev.usb_err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* Read from a OV519 register, note not valid for the w9968cf!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) /* returns: negative is error, pos or zero is data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static int reg_r(struct sd *sd, u16 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) int req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (sd->gspca_dev.usb_err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) req = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) case BRIDGE_OVFX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) req = 0x0b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) /* Avoid things going to fast for the bridge with a xhci host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) ret = usb_control_msg(sd->gspca_dev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) 0, index, sd->gspca_dev.usb_buf, 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) ret = sd->gspca_dev.usb_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) gspca_dbg(gspca_dev, D_USBI, "GET %02x 0000 %04x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) req, index, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) gspca_err(gspca_dev, "reg_r %02x failed %d\n", index, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) sd->gspca_dev.usb_err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) * Make sure the result is zeroed to avoid uninitialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) * values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) gspca_dev->usb_buf[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /* Read 8 values from a OV519 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) static int reg_r8(struct sd *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) u16 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (sd->gspca_dev.usb_err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) /* Avoid things going to fast for the bridge with a xhci host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ret = usb_control_msg(sd->gspca_dev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) 1, /* REQ_IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) 0, index, sd->gspca_dev.usb_buf, 8, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) ret = sd->gspca_dev.usb_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) gspca_err(gspca_dev, "reg_r8 %02x failed %d\n", index, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) sd->gspca_dev.usb_err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) * Make sure the buffer is zeroed to avoid uninitialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) * values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) memset(gspca_dev->usb_buf, 0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) * Writes bits at positions specified by mask to an OV51x reg. Bits that are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) * the same position as 1's in "mask" are cleared and set to "value". Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) * that are in the same position as 0's in "mask" are preserved, regardless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) * of their respective state in "value".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) static void reg_w_mask(struct sd *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) u16 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) u8 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) u8 oldval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) if (mask != 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) value &= mask; /* Enforce mask on value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) ret = reg_r(sd, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) oldval = ret & ~mask; /* Clear the masked bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) value |= oldval; /* Set the desired bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) reg_w(sd, index, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) * Writes multiple (n) byte value to a single register. Only valid with certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) * registers (0x30 and 0xc4 - 0xce).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) static void ov518_reg_w32(struct sd *sd, u16 index, u32 value, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (sd->gspca_dev.usb_err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) *((__le32 *) sd->gspca_dev.usb_buf) = __cpu_to_le32(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) /* Avoid things going to fast for the bridge with a xhci host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) ret = usb_control_msg(sd->gspca_dev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) usb_sndctrlpipe(sd->gspca_dev.dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) 1 /* REG_IO */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) 0, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) sd->gspca_dev.usb_buf, n, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) gspca_err(gspca_dev, "reg_w32 %02x failed %d\n", index, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) sd->gspca_dev.usb_err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) static void ov511_i2c_w(struct sd *sd, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) int rc, retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) gspca_dbg(gspca_dev, D_USBO, "ov511_i2c_w %02x %02x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) /* Three byte write cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) for (retries = 6; ; ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) /* Select camera register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) reg_w(sd, R51x_I2C_SADDR_3, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) /* Write "value" to I2C data port of OV511 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) reg_w(sd, R51x_I2C_DATA, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) /* Initiate 3-byte write cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) reg_w(sd, R511_I2C_CTL, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) rc = reg_r(sd, R511_I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if ((rc & 2) == 0) /* Ack? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) if (--retries < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) gspca_dbg(gspca_dev, D_USBO, "i2c write retries exhausted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) static int ov511_i2c_r(struct sd *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) int rc, value, retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) /* Two byte write cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) for (retries = 6; ; ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) /* Select camera register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) reg_w(sd, R51x_I2C_SADDR_2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) /* Initiate 2-byte write cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) reg_w(sd, R511_I2C_CTL, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) rc = reg_r(sd, R511_I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) if ((rc & 2) == 0) /* Ack? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) /* I2C abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) reg_w(sd, R511_I2C_CTL, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (--retries < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) gspca_dbg(gspca_dev, D_USBI, "i2c write retries exhausted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) /* Two byte read cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) for (retries = 6; ; ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) /* Initiate 2-byte read cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) reg_w(sd, R511_I2C_CTL, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) rc = reg_r(sd, R511_I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) } while (rc > 0 && ((rc & 1) == 0)); /* Retry until idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if ((rc & 2) == 0) /* Ack? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) /* I2C abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) reg_w(sd, R511_I2C_CTL, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) if (--retries < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) gspca_dbg(gspca_dev, D_USBI, "i2c read retries exhausted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) value = reg_r(sd, R51x_I2C_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) gspca_dbg(gspca_dev, D_USBI, "ov511_i2c_r %02x %02x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) /* This is needed to make i2c_w() work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) reg_w(sd, R511_I2C_CTL, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) * The OV518 I2C I/O procedure is different, hence, this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) * This is normally only called from i2c_w(). Note that this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) * always succeeds regardless of whether the sensor is present and working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static void ov518_i2c_w(struct sd *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) gspca_dbg(gspca_dev, D_USBO, "ov518_i2c_w %02x %02x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) /* Select camera register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) reg_w(sd, R51x_I2C_SADDR_3, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) /* Write "value" to I2C data port of OV511 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) reg_w(sd, R51x_I2C_DATA, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) /* Initiate 3-byte write cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) reg_w(sd, R518_I2C_CTL, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) /* wait for write complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) msleep(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) reg_r8(sd, R518_I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) * returns: negative is error, pos or zero is data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) * The OV518 I2C I/O procedure is different, hence, this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) * This is normally only called from i2c_r(). Note that this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) * always succeeds regardless of whether the sensor is present and working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) static int ov518_i2c_r(struct sd *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) /* Select camera register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) reg_w(sd, R51x_I2C_SADDR_2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) /* Initiate 2-byte write cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) reg_w(sd, R518_I2C_CTL, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) reg_r8(sd, R518_I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) /* Initiate 2-byte read cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) reg_w(sd, R518_I2C_CTL, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) reg_r8(sd, R518_I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) value = reg_r(sd, R51x_I2C_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) gspca_dbg(gspca_dev, D_USBI, "ov518_i2c_r %02x %02x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) static void ovfx2_i2c_w(struct sd *sd, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) if (sd->gspca_dev.usb_err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) ret = usb_control_msg(sd->gspca_dev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) usb_sndctrlpipe(sd->gspca_dev.dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) (u16) value, (u16) reg, NULL, 0, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) gspca_err(gspca_dev, "ovfx2_i2c_w %02x failed %d\n", reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) sd->gspca_dev.usb_err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) gspca_dbg(gspca_dev, D_USBO, "ovfx2_i2c_w %02x %02x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) static int ovfx2_i2c_r(struct sd *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) if (sd->gspca_dev.usb_err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) ret = usb_control_msg(sd->gspca_dev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) 0, (u16) reg, sd->gspca_dev.usb_buf, 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) ret = sd->gspca_dev.usb_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) gspca_dbg(gspca_dev, D_USBI, "ovfx2_i2c_r %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) gspca_err(gspca_dev, "ovfx2_i2c_r %02x failed %d\n", reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) sd->gspca_dev.usb_err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static void i2c_w(struct sd *sd, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) if (sd->sensor_reg_cache[reg] == value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) ov511_i2c_w(sd, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) case BRIDGE_OV518:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) case BRIDGE_OV518PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) case BRIDGE_OV519:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) ov518_i2c_w(sd, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) case BRIDGE_OVFX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) ovfx2_i2c_w(sd, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) case BRIDGE_W9968CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) w9968cf_i2c_w(sd, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) if (sd->gspca_dev.usb_err >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) /* Up on sensor reset empty the register cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) if (reg == 0x12 && (value & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) memset(sd->sensor_reg_cache, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) sizeof(sd->sensor_reg_cache));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) sd->sensor_reg_cache[reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) static int i2c_r(struct sd *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) if (sd->sensor_reg_cache[reg] != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) return sd->sensor_reg_cache[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) ret = ov511_i2c_r(sd, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) case BRIDGE_OV518:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) case BRIDGE_OV518PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) case BRIDGE_OV519:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) ret = ov518_i2c_r(sd, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) case BRIDGE_OVFX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) ret = ovfx2_i2c_r(sd, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) case BRIDGE_W9968CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) ret = w9968cf_i2c_r(sd, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) sd->sensor_reg_cache[reg] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) /* Writes bits at positions specified by mask to an I2C reg. Bits that are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) * the same position as 1's in "mask" are cleared and set to "value". Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) * that are in the same position as 0's in "mask" are preserved, regardless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) * of their respective state in "value".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) static void i2c_w_mask(struct sd *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) u8 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) u8 oldval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) value &= mask; /* Enforce mask on value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) rc = i2c_r(sd, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) oldval = rc & ~mask; /* Clear the masked bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) value |= oldval; /* Set the desired bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) i2c_w(sd, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) /* Temporarily stops OV511 from functioning. Must do this before changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) * registers while the camera is streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) static inline void ov51x_stop(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) gspca_dbg(gspca_dev, D_STREAM, "stopping\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) sd->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) reg_w(sd, R51x_SYS_RESET, 0x3d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) case BRIDGE_OV518:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) case BRIDGE_OV518PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) reg_w_mask(sd, R51x_SYS_RESET, 0x3a, 0x3a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) case BRIDGE_OV519:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) reg_w(sd, OV519_R51_RESET1, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) reg_w(sd, OV519_R51_RESET1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) reg_w(sd, 0x22, 0x00); /* FRAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) case BRIDGE_OVFX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) reg_w_mask(sd, 0x0f, 0x00, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) case BRIDGE_W9968CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) reg_w(sd, 0x3c, 0x0a05); /* stop USB transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) /* Restarts OV511 after ov511_stop() is called. Has no effect if it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) * actually stopped (for performance). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) static inline void ov51x_restart(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) gspca_dbg(gspca_dev, D_STREAM, "restarting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) if (!sd->stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) sd->stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) /* Reinitialize the stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) reg_w(sd, R51x_SYS_RESET, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) case BRIDGE_OV518:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) case BRIDGE_OV518PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) reg_w(sd, 0x2f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) reg_w(sd, R51x_SYS_RESET, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) case BRIDGE_OV519:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) reg_w(sd, OV519_R51_RESET1, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) reg_w(sd, OV519_R51_RESET1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) reg_w(sd, 0x22, 0x1d); /* FRAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) case BRIDGE_OVFX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) reg_w_mask(sd, 0x0f, 0x02, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) case BRIDGE_W9968CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) reg_w(sd, 0x3c, 0x8a05); /* USB FIFO enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) static void ov51x_set_slave_ids(struct sd *sd, u8 slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) /* This does an initial reset of an OmniVision sensor and ensures that I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) * is synchronized. Returns <0 on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) static int init_ov_sensor(struct sd *sd, u8 slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) ov51x_set_slave_ids(sd, slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) /* Reset the sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) i2c_w(sd, 0x12, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* Wait for it to initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) for (i = 0; i < i2c_detect_tries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) if (i2c_r(sd, OV7610_REG_ID_HIGH) == 0x7f &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) i2c_r(sd, OV7610_REG_ID_LOW) == 0xa2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) gspca_dbg(gspca_dev, D_PROBE, "I2C synced in %d attempt(s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) /* Reset the sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) i2c_w(sd, 0x12, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) /* Wait for it to initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) /* Dummy read to sync I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) if (i2c_r(sd, 0x00) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) /* Set the read and write slave IDs. The "slave" argument is the write slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) * and the read slave will be set to (slave + 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) * This should not be called from outside the i2c I/O functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) * Sets I2C read and write slave IDs. Returns <0 for error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) static void ov51x_set_slave_ids(struct sd *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) u8 slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) case BRIDGE_OVFX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) reg_w(sd, OVFX2_I2C_ADDR, slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) case BRIDGE_W9968CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) sd->sensor_addr = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) reg_w(sd, R51x_I2C_W_SID, slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) reg_w(sd, R51x_I2C_R_SID, slave + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static void write_regvals(struct sd *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) const struct ov_regvals *regvals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) while (--n >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) reg_w(sd, regvals->reg, regvals->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) regvals++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) static void write_i2c_regvals(struct sd *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) const struct ov_i2c_regvals *regvals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) while (--n >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) i2c_w(sd, regvals->reg, regvals->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) regvals++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) * OV511 and sensor configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) /* This initializes the OV2x10 / OV3610 / OV3620 / OV9600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) static void ov_hires_configure(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) int high, low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) if (sd->bridge != BRIDGE_OVFX2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) gspca_err(gspca_dev, "error hires sensors only supported with ovfx2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) gspca_dbg(gspca_dev, D_PROBE, "starting ov hires configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) /* Detect sensor (sub)type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) high = i2c_r(sd, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) low = i2c_r(sd, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) /* info("%x, %x", high, low); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) switch (high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) case 0x96:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) switch (low) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) case 0x40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) gspca_dbg(gspca_dev, D_PROBE, "Sensor is a OV2610\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) sd->sensor = SEN_OV2610;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) case 0x41:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) gspca_dbg(gspca_dev, D_PROBE, "Sensor is a OV2610AE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) sd->sensor = SEN_OV2610AE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) case 0xb1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) gspca_dbg(gspca_dev, D_PROBE, "Sensor is a OV9600\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) sd->sensor = SEN_OV9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) case 0x36:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) if ((low & 0x0f) == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) gspca_dbg(gspca_dev, D_PROBE, "Sensor is a OV3610\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) sd->sensor = SEN_OV3610;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) gspca_err(gspca_dev, "Error unknown sensor type: %02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) high, low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) /* This initializes the OV8110, OV8610 sensor. The OV8110 uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) * the same register settings as the OV8610, since they are very similar.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) static void ov8xx0_configure(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) gspca_dbg(gspca_dev, D_PROBE, "starting ov8xx0 configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) /* Detect sensor (sub)type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) rc = i2c_r(sd, OV7610_REG_COM_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) gspca_err(gspca_dev, "Error detecting sensor type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) if ((rc & 3) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) sd->sensor = SEN_OV8610;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) gspca_err(gspca_dev, "Unknown image sensor version: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) rc & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) /* This initializes the OV7610, OV7620, or OV76BE sensor. The OV76BE uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) * the same register settings as the OV7610, since they are very similar.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) static void ov7xx0_configure(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) int rc, high, low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) gspca_dbg(gspca_dev, D_PROBE, "starting OV7xx0 configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) /* Detect sensor (sub)type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) rc = i2c_r(sd, OV7610_REG_COM_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) /* add OV7670 here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) * it appears to be wrongly detected as a 7610 by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) gspca_err(gspca_dev, "Error detecting sensor type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) if ((rc & 3) == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) /* quick hack to make OV7670s work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) high = i2c_r(sd, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) low = i2c_r(sd, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) /* info("%x, %x", high, low); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) if (high == 0x76 && (low & 0xf0) == 0x70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV76%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) sd->sensor = SEN_OV7670;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV7610\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) sd->sensor = SEN_OV7610;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) } else if ((rc & 3) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) /* I don't know what's different about the 76BE yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) if (i2c_r(sd, 0x15) & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV7620AE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) sd->sensor = SEN_OV7620AE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV76BE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) sd->sensor = SEN_OV76BE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) } else if ((rc & 3) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) /* try to read product id registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) high = i2c_r(sd, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) if (high < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) gspca_err(gspca_dev, "Error detecting camera chip PID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) low = i2c_r(sd, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) if (low < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) gspca_err(gspca_dev, "Error detecting camera chip VER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) if (high == 0x76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) switch (low) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) case 0x30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) gspca_err(gspca_dev, "Sensor is an OV7630/OV7635\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) gspca_err(gspca_dev, "7630 is not supported by this driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) case 0x40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV7645\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) sd->sensor = SEN_OV7640; /* FIXME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) case 0x45:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV7645B\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) sd->sensor = SEN_OV7640; /* FIXME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) case 0x48:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV7648\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) sd->sensor = SEN_OV7648;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) case 0x60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) gspca_dbg(gspca_dev, D_PROBE, "Sensor is a OV7660\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) sd->sensor = SEN_OV7660;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) gspca_err(gspca_dev, "Unknown sensor: 0x76%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV7620\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) sd->sensor = SEN_OV7620;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) gspca_err(gspca_dev, "Unknown image sensor version: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) rc & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) /* This initializes the OV6620, OV6630, OV6630AE, or OV6630AF sensor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) static void ov6xx0_configure(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) gspca_dbg(gspca_dev, D_PROBE, "starting OV6xx0 configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) /* Detect sensor (sub)type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) rc = i2c_r(sd, OV7610_REG_COM_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) gspca_err(gspca_dev, "Error detecting sensor type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) /* Ugh. The first two bits are the version bits, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) * the entire register value must be used. I guess OVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) * underestimated how many variants they would make. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) switch (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) sd->sensor = SEN_OV6630;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) pr_warn("WARNING: Sensor is an OV66308. Your camera may have been misdetected in previous driver versions.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) sd->sensor = SEN_OV6620;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV6620\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) sd->sensor = SEN_OV6630;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV66308AE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) sd->sensor = SEN_OV66308AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) gspca_dbg(gspca_dev, D_PROBE, "Sensor is an OV66308AF\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) case 0x90:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) sd->sensor = SEN_OV6630;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) pr_warn("WARNING: Sensor is an OV66307. Your camera may have been misdetected in previous driver versions.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) gspca_err(gspca_dev, "FATAL: Unknown sensor version: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) /* Set sensor-specific vars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) sd->sif = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) /* Turns on or off the LED. Only has an effect with OV511+/OV518(+)/OV519 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) static void ov51x_led_control(struct sd *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) if (sd->invert_led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) on = !on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) /* OV511 has no LED control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) reg_w(sd, R511_SYS_LED_CTL, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) case BRIDGE_OV518:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) case BRIDGE_OV518PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) reg_w_mask(sd, R518_GPIO_OUT, 0x02 * on, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) case BRIDGE_OV519:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) reg_w_mask(sd, OV519_GPIO_DATA_OUT0, on, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) static void sd_reset_snapshot(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) if (!sd->snapshot_needs_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) /* Note it is important that we clear sd->snapshot_needs_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) before actually clearing the snapshot state in the bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) otherwise we might race with the pkt_scan interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) sd->snapshot_needs_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) reg_w(sd, R51x_SYS_SNAP, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) reg_w(sd, R51x_SYS_SNAP, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) case BRIDGE_OV518:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) case BRIDGE_OV518PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) reg_w(sd, R51x_SYS_SNAP, 0x02); /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) reg_w(sd, R51x_SYS_SNAP, 0x01); /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) case BRIDGE_OV519:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) reg_w(sd, R51x_SYS_RESET, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) reg_w(sd, R51x_SYS_RESET, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) static void ov51x_upload_quan_tables(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) static const unsigned char yQuanTable511[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) 0, 1, 1, 2, 2, 3, 3, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) 1, 1, 1, 2, 2, 3, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) 1, 1, 2, 2, 3, 4, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) 2, 2, 2, 3, 4, 4, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) 2, 2, 3, 4, 4, 5, 5, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) 3, 3, 4, 4, 5, 5, 5, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) 3, 4, 4, 4, 5, 5, 5, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) 4, 4, 4, 4, 5, 5, 5, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) static const unsigned char uvQuanTable511[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) 0, 2, 2, 3, 4, 4, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) 2, 2, 2, 4, 4, 4, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) 2, 2, 3, 4, 4, 4, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) 3, 4, 4, 4, 4, 4, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) 4, 4, 4, 4, 4, 4, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) 4, 4, 4, 4, 4, 4, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) 4, 4, 4, 4, 4, 4, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) 4, 4, 4, 4, 4, 4, 4, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) /* OV518 quantization tables are 8x4 (instead of 8x8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) static const unsigned char yQuanTable518[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) 5, 4, 5, 6, 6, 7, 7, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) 5, 5, 5, 5, 6, 7, 7, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) 6, 6, 6, 6, 7, 7, 7, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) 7, 7, 6, 7, 7, 7, 8, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) static const unsigned char uvQuanTable518[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) 6, 6, 6, 7, 7, 7, 7, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) 6, 6, 6, 7, 7, 7, 7, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) 6, 6, 6, 7, 7, 7, 7, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) 7, 7, 7, 7, 7, 7, 8, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) const unsigned char *pYTable, *pUVTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) unsigned char val0, val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) int i, size, reg = R51x_COMP_LUT_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) gspca_dbg(gspca_dev, D_PROBE, "Uploading quantization tables\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) if (sd->bridge == BRIDGE_OV511 || sd->bridge == BRIDGE_OV511PLUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) pYTable = yQuanTable511;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) pUVTable = uvQuanTable511;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) size = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) pYTable = yQuanTable518;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) pUVTable = uvQuanTable518;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) size = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) val0 = *pYTable++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) val1 = *pYTable++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) val0 &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) val1 &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) val0 |= val1 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) reg_w(sd, reg, val0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) val0 = *pUVTable++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) val1 = *pUVTable++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) val0 &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) val1 &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) val0 |= val1 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) reg_w(sd, reg + size, val0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) reg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) /* This initializes the OV511/OV511+ and the sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) static void ov511_configure(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) /* For 511 and 511+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) static const struct ov_regvals init_511[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) { R51x_SYS_RESET, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) { R51x_SYS_INIT, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) { R51x_SYS_RESET, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) { R51x_SYS_INIT, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) { R51x_SYS_RESET, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) { R51x_SYS_INIT, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) { R51x_SYS_RESET, 0x3d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) static const struct ov_regvals norm_511[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) { R511_DRAM_FLOW_CTL, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) { R51x_SYS_SNAP, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) { R51x_SYS_SNAP, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) { R51x_SYS_SNAP, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) { R511_FIFO_OPTS, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) { R511_COMP_EN, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) { R511_COMP_LUT_EN, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) static const struct ov_regvals norm_511_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) { R511_DRAM_FLOW_CTL, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) { R51x_SYS_SNAP, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) { R51x_SYS_SNAP, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) { R51x_SYS_SNAP, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) { R511_FIFO_OPTS, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) { R511_COMP_EN, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) { R511_COMP_LUT_EN, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) static const struct ov_regvals compress_511[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) { 0x70, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) { 0x71, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) { 0x72, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) { 0x73, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) { 0x74, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) { 0x75, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) { 0x76, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) { 0x77, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) gspca_dbg(gspca_dev, D_PROBE, "Device custom id %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) reg_r(sd, R51x_SYS_CUST_ID));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) write_regvals(sd, init_511, ARRAY_SIZE(init_511));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) write_regvals(sd, norm_511, ARRAY_SIZE(norm_511));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) write_regvals(sd, norm_511_p, ARRAY_SIZE(norm_511_p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) /* Init compression */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) write_regvals(sd, compress_511, ARRAY_SIZE(compress_511));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) ov51x_upload_quan_tables(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) /* This initializes the OV518/OV518+ and the sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) static void ov518_configure(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) /* For 518 and 518+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) static const struct ov_regvals init_518[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) { R51x_SYS_RESET, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) { R51x_SYS_INIT, 0xe1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) { R51x_SYS_RESET, 0x3e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) { R51x_SYS_INIT, 0xe1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) { R51x_SYS_RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) { R51x_SYS_INIT, 0xe1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) { 0x46, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) { 0x5d, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) static const struct ov_regvals norm_518[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) { R51x_SYS_SNAP, 0x02 }, /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) { R51x_SYS_SNAP, 0x01 }, /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) { 0x31, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) { 0x5d, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) { 0x24, 0x9f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) { 0x25, 0x90 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) { 0x20, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) { 0x51, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) { 0x71, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) { 0x2f, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) static const struct ov_regvals norm_518_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) { R51x_SYS_SNAP, 0x02 }, /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) { R51x_SYS_SNAP, 0x01 }, /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) { 0x31, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) { 0x5d, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) { 0x24, 0x9f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) { 0x25, 0x90 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) { 0x20, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) { 0x51, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) { 0x71, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) { 0x40, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) { 0x41, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) { 0x46, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) { 0x33, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) { 0x21, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) { 0x3f, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) { 0x2f, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) /* First 5 bits of custom ID reg are a revision ID on OV518 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) sd->revision = reg_r(sd, R51x_SYS_CUST_ID) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) gspca_dbg(gspca_dev, D_PROBE, "Device revision %d\n", sd->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) write_regvals(sd, init_518, ARRAY_SIZE(init_518));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) /* Set LED GPIO pin to output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) reg_w_mask(sd, R518_GPIO_CTL, 0x00, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) case BRIDGE_OV518:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) write_regvals(sd, norm_518, ARRAY_SIZE(norm_518));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) case BRIDGE_OV518PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) write_regvals(sd, norm_518_p, ARRAY_SIZE(norm_518_p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) ov51x_upload_quan_tables(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) reg_w(sd, 0x2f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) static void ov519_configure(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) static const struct ov_regvals init_519[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) { 0x5a, 0x6d }, /* EnableSystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) { 0x53, 0x9b }, /* don't enable the microcontroller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) { OV519_R54_EN_CLK1, 0xff }, /* set bit2 to enable jpeg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) { 0x5d, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) { 0x49, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) { 0x48, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) /* Set LED pin to output mode. Bit 4 must be cleared or sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) * detection will fail. This deserves further investigation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) { OV519_GPIO_IO_CTRL0, 0xee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) { OV519_R51_RESET1, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) { OV519_R51_RESET1, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) { 0x22, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) /* windows reads 0x55 at this point*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) write_regvals(sd, init_519, ARRAY_SIZE(init_519));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) static void ovfx2_configure(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) static const struct ov_regvals init_fx2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) { 0x00, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) { 0x02, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) { 0x0f, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) { 0xe9, 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) { 0xea, 0xc7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) { 0xeb, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) { 0xec, 0xf6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) sd->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) write_regvals(sd, init_fx2, ARRAY_SIZE(init_fx2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) /* set the mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) /* This function works for ov7660 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static void ov519_set_mode(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) static const struct ov_regvals bridge_ov7660[2][10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) {{0x10, 0x14}, {0x11, 0x1e}, {0x12, 0x00}, {0x13, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) {0x14, 0x00}, {0x15, 0x00}, {0x16, 0x00}, {0x20, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) {0x25, 0x01}, {0x26, 0x00}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) {{0x10, 0x28}, {0x11, 0x3c}, {0x12, 0x00}, {0x13, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) {0x14, 0x00}, {0x15, 0x00}, {0x16, 0x00}, {0x20, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) {0x25, 0x03}, {0x26, 0x00}}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) static const struct ov_i2c_regvals sensor_ov7660[2][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) {{0x12, 0x00}, {0x24, 0x00}, {0x0c, 0x0c}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) {{0x12, 0x00}, {0x04, 0x00}, {0x0c, 0x00}}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) static const struct ov_i2c_regvals sensor_ov7660_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) {OV7670_R17_HSTART, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) {OV7670_R18_HSTOP, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) {OV7670_R32_HREF, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) {OV7670_R19_VSTART, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) {OV7670_R1A_VSTOP, 0x7a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) {OV7670_R03_VREF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) /* {0x33, 0x00}, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) /* {0x34, 0x07}, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) /* {0x36, 0x00}, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) /* {0x6b, 0x0a}, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) write_regvals(sd, bridge_ov7660[sd->gspca_dev.curr_mode],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) ARRAY_SIZE(bridge_ov7660[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) write_i2c_regvals(sd, sensor_ov7660[sd->gspca_dev.curr_mode],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) ARRAY_SIZE(sensor_ov7660[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) write_i2c_regvals(sd, sensor_ov7660_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) ARRAY_SIZE(sensor_ov7660_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) /* set the frame rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) /* This function works for sensors ov7640, ov7648 ov7660 and ov7670 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) static void ov519_set_fr(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) int fr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) u8 clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) /* frame rate table with indices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) * - mode = 0: 320x240, 1: 640x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) * - fr rate = 0: 30, 1: 25, 2: 20, 3: 15, 4: 10, 5: 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) * - reg = 0: bridge a4, 1: bridge 23, 2: sensor 11 (clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) static const u8 fr_tb[2][6][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) {{0x04, 0xff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) {0x04, 0x1f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) {0x04, 0x1b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) {0x04, 0x15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) {0x04, 0x09, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) {0x04, 0x01, 0x00}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) {{0x0c, 0xff, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) {0x0c, 0x1f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) {0x0c, 0x1b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) {0x04, 0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) {0x04, 0x1f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) {0x04, 0x1b, 0x01}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) if (frame_rate > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) sd->frame_rate = frame_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) if (sd->frame_rate >= 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) fr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) else if (sd->frame_rate >= 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) fr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) else if (sd->frame_rate >= 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) fr = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) else if (sd->frame_rate >= 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) fr = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) else if (sd->frame_rate >= 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) fr = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) fr = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) reg_w(sd, 0xa4, fr_tb[sd->gspca_dev.curr_mode][fr][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) reg_w(sd, 0x23, fr_tb[sd->gspca_dev.curr_mode][fr][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) clock = fr_tb[sd->gspca_dev.curr_mode][fr][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) if (sd->sensor == SEN_OV7660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) clock |= 0x80; /* enable double clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) ov518_i2c_w(sd, OV7670_R11_CLKRC, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) static void setautogain(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) i2c_w_mask(sd, 0x13, val ? 0x05 : 0x00, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) /* this function is called at probe time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) static int sd_config(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) const struct usb_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) struct cam *cam = &gspca_dev->cam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) sd->bridge = id->driver_info & BRIDGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) sd->invert_led = (id->driver_info & BRIDGE_INVERT_LED) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) cam->cam_mode = ov511_vga_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) cam->nmodes = ARRAY_SIZE(ov511_vga_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) case BRIDGE_OV518:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) case BRIDGE_OV518PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) cam->cam_mode = ov518_vga_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) cam->nmodes = ARRAY_SIZE(ov518_vga_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) case BRIDGE_OV519:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) cam->cam_mode = ov519_vga_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) case BRIDGE_OVFX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) cam->cam_mode = ov519_vga_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) cam->bulk_size = OVFX2_BULK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) cam->bulk_nurbs = MAX_NURBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) cam->bulk = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) case BRIDGE_W9968CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) cam->cam_mode = w9968cf_vga_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) cam->nmodes = ARRAY_SIZE(w9968cf_vga_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) sd->frame_rate = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) /* this function is called at probe and resume time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) static int sd_init(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) struct cam *cam = &gspca_dev->cam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) ov511_configure(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) case BRIDGE_OV518:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) case BRIDGE_OV518PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) ov518_configure(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) case BRIDGE_OV519:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) ov519_configure(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) case BRIDGE_OVFX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) ovfx2_configure(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) case BRIDGE_W9968CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) w9968cf_configure(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) /* The OV519 must be more aggressive about sensor detection since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) * I2C write will never fail if the sensor is not present. We have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) * to try to initialize the sensor to detect its presence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) sd->sensor = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) /* Test for 76xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) if (init_ov_sensor(sd, OV7xx0_SID) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) ov7xx0_configure(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) /* Test for 6xx0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) } else if (init_ov_sensor(sd, OV6xx0_SID) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) ov6xx0_configure(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) /* Test for 8xx0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) } else if (init_ov_sensor(sd, OV8xx0_SID) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) ov8xx0_configure(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) /* Test for 3xxx / 2xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) } else if (init_ov_sensor(sd, OV_HIRES_SID) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) ov_hires_configure(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) gspca_err(gspca_dev, "Can't determine sensor slave IDs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) if (sd->sensor < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) ov51x_led_control(sd, 0); /* turn LED off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) if (sd->sif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) cam->cam_mode = ov511_sif_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) cam->nmodes = ARRAY_SIZE(ov511_sif_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) case BRIDGE_OV518:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) case BRIDGE_OV518PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) if (sd->sif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) cam->cam_mode = ov518_sif_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) cam->nmodes = ARRAY_SIZE(ov518_sif_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) case BRIDGE_OV519:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) if (sd->sif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) cam->cam_mode = ov519_sif_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) case BRIDGE_OVFX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) case SEN_OV2610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) case SEN_OV2610AE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) cam->cam_mode = ovfx2_ov2610_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) cam->nmodes = ARRAY_SIZE(ovfx2_ov2610_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) case SEN_OV3610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) cam->cam_mode = ovfx2_ov3610_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) cam->nmodes = ARRAY_SIZE(ovfx2_ov3610_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) case SEN_OV9600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) cam->cam_mode = ovfx2_ov9600_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) cam->nmodes = ARRAY_SIZE(ovfx2_ov9600_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) if (sd->sif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) cam->cam_mode = ov519_sif_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) case BRIDGE_W9968CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) if (sd->sif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) cam->nmodes = ARRAY_SIZE(w9968cf_vga_mode) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) /* w9968cf needs initialisation once the sensor is known */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) w9968cf_init(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) /* initialize the sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) case SEN_OV2610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) write_i2c_regvals(sd, norm_2610, ARRAY_SIZE(norm_2610));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) /* Enable autogain, autoexpo, awb, bandfilter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) i2c_w_mask(sd, 0x13, 0x27, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) case SEN_OV2610AE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) write_i2c_regvals(sd, norm_2610ae, ARRAY_SIZE(norm_2610ae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) /* enable autoexpo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) i2c_w_mask(sd, 0x13, 0x05, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) case SEN_OV3610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) write_i2c_regvals(sd, norm_3620b, ARRAY_SIZE(norm_3620b));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) /* Enable autogain, autoexpo, awb, bandfilter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) i2c_w_mask(sd, 0x13, 0x27, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) case SEN_OV6620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) write_i2c_regvals(sd, norm_6x20, ARRAY_SIZE(norm_6x20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) case SEN_OV6630:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) case SEN_OV66308AF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) write_i2c_regvals(sd, norm_6x30, ARRAY_SIZE(norm_6x30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) /* case SEN_OV7610: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) /* case SEN_OV76BE: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) write_i2c_regvals(sd, norm_7610, ARRAY_SIZE(norm_7610));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) i2c_w_mask(sd, 0x0e, 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) case SEN_OV7620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) case SEN_OV7620AE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) write_i2c_regvals(sd, norm_7620, ARRAY_SIZE(norm_7620));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) case SEN_OV7640:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) case SEN_OV7648:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) write_i2c_regvals(sd, norm_7640, ARRAY_SIZE(norm_7640));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) case SEN_OV7660:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) i2c_w(sd, OV7670_R12_COM7, OV7670_COM7_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) msleep(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) reg_w(sd, OV519_R57_SNAPSHOT, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) write_regvals(sd, init_519_ov7660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) ARRAY_SIZE(init_519_ov7660));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) write_i2c_regvals(sd, norm_7660, ARRAY_SIZE(norm_7660));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) sd->gspca_dev.curr_mode = 1; /* 640x480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) ov519_set_mode(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) ov519_set_fr(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) sd_reset_snapshot(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) ov51x_restart(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) ov51x_stop(sd); /* not in win traces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) ov51x_led_control(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) case SEN_OV7670:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) write_i2c_regvals(sd, norm_7670, ARRAY_SIZE(norm_7670));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) case SEN_OV8610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) write_i2c_regvals(sd, norm_8610, ARRAY_SIZE(norm_8610));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) case SEN_OV9600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) write_i2c_regvals(sd, norm_9600, ARRAY_SIZE(norm_9600));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) /* enable autoexpo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) /* i2c_w_mask(sd, 0x13, 0x05, 0x05); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) return gspca_dev->usb_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) gspca_err(gspca_dev, "OV519 Config failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) /* function called at start time before URB creation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) static int sd_isoc_init(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) case BRIDGE_OVFX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) if (gspca_dev->pixfmt.width != 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) gspca_dev->cam.bulk_size = OVFX2_BULK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) gspca_dev->cam.bulk_size = 7 * 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) /* Set up the OV511/OV511+ with the given image parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) * Do not put any sensor-specific code in here (including I2C I/O functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) static void ov511_mode_init_regs(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) int hsegs, vsegs, packet_size, fps, needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) int interlaced = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) struct usb_host_interface *alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) struct usb_interface *intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) if (!alt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) gspca_err(gspca_dev, "Couldn't get altsetting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) sd->gspca_dev.usb_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) if (alt->desc.bNumEndpoints < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) sd->gspca_dev.usb_err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) reg_w(sd, R51x_FIFO_PSIZE, packet_size >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) reg_w(sd, R511_CAM_UV_EN, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) reg_w(sd, R511_SNAP_UV_EN, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) reg_w(sd, R511_SNAP_OPTS, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) /* Here I'm assuming that snapshot size == image size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) * I hope that's always true. --claudio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) hsegs = (sd->gspca_dev.pixfmt.width >> 3) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) vsegs = (sd->gspca_dev.pixfmt.height >> 3) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) reg_w(sd, R511_CAM_PXCNT, hsegs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) reg_w(sd, R511_CAM_LNCNT, vsegs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) reg_w(sd, R511_CAM_PXDIV, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) reg_w(sd, R511_CAM_LNDIV, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) /* YUV420, low pass filter on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) reg_w(sd, R511_CAM_OPTS, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) /* Snapshot additions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) reg_w(sd, R511_SNAP_PXCNT, hsegs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) reg_w(sd, R511_SNAP_LNCNT, vsegs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) reg_w(sd, R511_SNAP_PXDIV, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) reg_w(sd, R511_SNAP_LNDIV, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) /******** Set the framerate ********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) if (frame_rate > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) sd->frame_rate = frame_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) case SEN_OV6620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) /* No framerate control, doesn't like higher rates yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) sd->clockdiv = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) /* Note once the FIXME's in mode_init_ov_sensor_regs() are fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) for more sensors we need to do this for them too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) case SEN_OV7620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) case SEN_OV7620AE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) case SEN_OV7640:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) case SEN_OV7648:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) case SEN_OV76BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) if (sd->gspca_dev.pixfmt.width == 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) interlaced = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) case SEN_OV6630:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) case SEN_OV7610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) case SEN_OV7670:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) switch (sd->frame_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) case 30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) case 25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) /* Not enough bandwidth to do 640x480 @ 30 fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) if (sd->gspca_dev.pixfmt.width != 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) sd->clockdiv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) /* For 640x480 case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) /* case 20: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) /* case 15: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) sd->clockdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) sd->clockdiv = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) sd->clockdiv = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) if (interlaced) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) sd->clockdiv = (sd->clockdiv + 1) * 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) /* Higher then 10 does not work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) if (sd->clockdiv > 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) sd->clockdiv = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) case SEN_OV8610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) /* No framerate control ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) sd->clockdiv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) /* Check if we have enough bandwidth to disable compression */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) fps = (interlaced ? 60 : 30) / (sd->clockdiv + 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) needed = fps * sd->gspca_dev.pixfmt.width *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) sd->gspca_dev.pixfmt.height * 3 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) /* 1000 isoc packets/sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) if (needed > 1000 * packet_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) /* Enable Y and UV quantization and compression */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) reg_w(sd, R511_COMP_EN, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) reg_w(sd, R511_COMP_LUT_EN, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) reg_w(sd, R511_COMP_EN, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) reg_w(sd, R511_COMP_LUT_EN, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) reg_w(sd, R51x_SYS_RESET, OV511_RESET_OMNICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) reg_w(sd, R51x_SYS_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) /* Sets up the OV518/OV518+ with the given image parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) * OV518 needs a completely different approach, until we can figure out what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) * the individual registers do. Also, only 15 FPS is supported now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) * Do not put any sensor-specific code in here (including I2C I/O functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) static void ov518_mode_init_regs(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) int hsegs, vsegs, packet_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) struct usb_host_interface *alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) struct usb_interface *intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) if (!alt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) gspca_err(gspca_dev, "Couldn't get altsetting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) sd->gspca_dev.usb_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) if (alt->desc.bNumEndpoints < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) sd->gspca_dev.usb_err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) ov518_reg_w32(sd, R51x_FIFO_PSIZE, packet_size & ~7, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) /******** Set the mode ********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) reg_w(sd, 0x2b, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) reg_w(sd, 0x2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) reg_w(sd, 0x2d, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) reg_w(sd, 0x2e, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) reg_w(sd, 0x3b, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) reg_w(sd, 0x3c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) reg_w(sd, 0x3d, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) reg_w(sd, 0x3e, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) if (sd->bridge == BRIDGE_OV518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) /* Set 8-bit (YVYU) input format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) reg_w_mask(sd, 0x20, 0x08, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) /* Set 12-bit (4:2:0) output format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) reg_w_mask(sd, 0x28, 0x80, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) reg_w_mask(sd, 0x38, 0x80, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) reg_w(sd, 0x28, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) reg_w(sd, 0x38, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) hsegs = sd->gspca_dev.pixfmt.width / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) vsegs = sd->gspca_dev.pixfmt.height / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) reg_w(sd, 0x29, hsegs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) reg_w(sd, 0x2a, vsegs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) reg_w(sd, 0x39, hsegs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) reg_w(sd, 0x3a, vsegs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) /* Windows driver does this here; who knows why */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) reg_w(sd, 0x2f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) /******** Set the framerate ********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) if (sd->bridge == BRIDGE_OV518PLUS && sd->revision == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) sd->sensor == SEN_OV7620AE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) sd->clockdiv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) sd->clockdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) /* Mode independent, but framerate dependent, regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) /* 0x51: Clock divider; Only works on some cams which use 2 crystals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) reg_w(sd, 0x51, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) reg_w(sd, 0x22, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) reg_w(sd, 0x23, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) if (sd->bridge == BRIDGE_OV518PLUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) case SEN_OV7620AE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) * HdG: 640x480 needs special handling on device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) * revision 2, we check for device revision > 0 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) * avoid regressions, as we don't know the correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) * thing todo for revision 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) * Also this likely means we don't need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) * differentiate between the OV7620 and OV7620AE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) * earlier testing hitting this same problem likely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) * happened to be with revision < 2 cams using an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) * OV7620 and revision 2 cams using an OV7620AE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) if (sd->revision > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) sd->gspca_dev.pixfmt.width == 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) reg_w(sd, 0x20, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) reg_w(sd, 0x21, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) reg_w(sd, 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) reg_w(sd, 0x21, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) case SEN_OV7620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) reg_w(sd, 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) reg_w(sd, 0x21, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) reg_w(sd, 0x21, 0x19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) reg_w(sd, 0x71, 0x17); /* Compression-related? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) /* FIXME: Sensor-specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) /* Bit 5 is what matters here. Of course, it is "reserved" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) i2c_w(sd, 0x54, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) reg_w(sd, 0x2f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) if (sd->bridge == BRIDGE_OV518PLUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) reg_w(sd, 0x24, 0x94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) reg_w(sd, 0x25, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) ov518_reg_w32(sd, 0xc4, 400, 2); /* 190h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) ov518_reg_w32(sd, 0xc6, 540, 2); /* 21ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) ov518_reg_w32(sd, 0xc7, 540, 2); /* 21ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) ov518_reg_w32(sd, 0xc8, 108, 2); /* 6ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) ov518_reg_w32(sd, 0xca, 131098, 3); /* 2001ah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) ov518_reg_w32(sd, 0xcb, 532, 2); /* 214h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) ov518_reg_w32(sd, 0xcc, 2400, 2); /* 960h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) ov518_reg_w32(sd, 0xcd, 32, 2); /* 20h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) ov518_reg_w32(sd, 0xce, 608, 2); /* 260h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) reg_w(sd, 0x24, 0x9f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) reg_w(sd, 0x25, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) ov518_reg_w32(sd, 0xc4, 400, 2); /* 190h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) ov518_reg_w32(sd, 0xc6, 381, 2); /* 17dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) ov518_reg_w32(sd, 0xc7, 381, 2); /* 17dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) ov518_reg_w32(sd, 0xc8, 128, 2); /* 80h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) ov518_reg_w32(sd, 0xca, 183331, 3); /* 2cc23h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) ov518_reg_w32(sd, 0xcb, 746, 2); /* 2eah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) ov518_reg_w32(sd, 0xcc, 1750, 2); /* 6d6h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) ov518_reg_w32(sd, 0xcd, 45, 2); /* 2dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) ov518_reg_w32(sd, 0xce, 851, 2); /* 353h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) reg_w(sd, 0x2f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) /* Sets up the OV519 with the given image parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) * OV519 needs a completely different approach, until we can figure out what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) * the individual registers do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) * Do not put any sensor-specific code in here (including I2C I/O functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) static void ov519_mode_init_regs(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) static const struct ov_regvals mode_init_519_ov7670[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) { 0x5d, 0x03 }, /* Turn off suspend mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) { 0x53, 0x9f }, /* was 9b in 1.65-1.08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) { OV519_R54_EN_CLK1, 0x0f }, /* bit2 (jpeg enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) { 0xa2, 0x20 }, /* a2-a5 are undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) { 0xa3, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) { 0xa4, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) { 0xa5, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) { 0x37, 0x00 }, /* SetUsbInit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) /* Enable both fields, YUV Input, disable defect comp (why?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) { 0x20, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) { 0x21, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) { 0x22, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) { 0x17, 0x50 }, /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) { 0x37, 0x00 }, /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) { 0x40, 0xff }, /* I2C timeout counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) { 0x46, 0x00 }, /* I2C clock prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) { 0x59, 0x04 }, /* new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) { 0xff, 0x00 }, /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) /* windows reads 0x55 at this point, why? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) static const struct ov_regvals mode_init_519[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) { 0x5d, 0x03 }, /* Turn off suspend mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) { 0x53, 0x9f }, /* was 9b in 1.65-1.08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) { OV519_R54_EN_CLK1, 0x0f }, /* bit2 (jpeg enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) { 0xa2, 0x20 }, /* a2-a5 are undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) { 0xa3, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) { 0xa4, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) { 0xa5, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) { 0x37, 0x00 }, /* SetUsbInit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) { 0x55, 0x02 }, /* 4.096 Mhz audio clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) /* Enable both fields, YUV Input, disable defect comp (why?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) { 0x22, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) { 0x17, 0x50 }, /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) { 0x37, 0x00 }, /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) { 0x40, 0xff }, /* I2C timeout counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) { 0x46, 0x00 }, /* I2C clock prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) { 0x59, 0x04 }, /* new from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) { 0xff, 0x00 }, /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) /* windows reads 0x55 at this point, why? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) /******** Set the mode ********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) write_regvals(sd, mode_init_519, ARRAY_SIZE(mode_init_519));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) if (sd->sensor == SEN_OV7640 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) sd->sensor == SEN_OV7648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) /* Select 8-bit input mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) reg_w_mask(sd, OV519_R20_DFR, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) case SEN_OV7660:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) return; /* done by ov519_set_mode/fr() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) case SEN_OV7670:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) write_regvals(sd, mode_init_519_ov7670,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) ARRAY_SIZE(mode_init_519_ov7670));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) reg_w(sd, OV519_R10_H_SIZE, sd->gspca_dev.pixfmt.width >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) reg_w(sd, OV519_R11_V_SIZE, sd->gspca_dev.pixfmt.height >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) if (sd->sensor == SEN_OV7670 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) reg_w(sd, OV519_R12_X_OFFSETL, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) else if (sd->sensor == SEN_OV7648 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) sd->gspca_dev.cam.cam_mode[sd->gspca_dev.curr_mode].priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) reg_w(sd, OV519_R12_X_OFFSETL, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) reg_w(sd, OV519_R12_X_OFFSETL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) reg_w(sd, OV519_R13_X_OFFSETH, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) reg_w(sd, OV519_R14_Y_OFFSETL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) reg_w(sd, OV519_R15_Y_OFFSETH, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) reg_w(sd, OV519_R16_DIVIDER, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) reg_w(sd, OV519_R25_FORMAT, 0x03); /* YUV422 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) reg_w(sd, 0x26, 0x00); /* Undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) /******** Set the framerate ********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) if (frame_rate > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) sd->frame_rate = frame_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) /* FIXME: These are only valid at the max resolution. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) sd->clockdiv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) case SEN_OV7640:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) case SEN_OV7648:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) switch (sd->frame_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) /* case 30: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) reg_w(sd, 0xa4, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) reg_w(sd, 0x23, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) case 25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) reg_w(sd, 0xa4, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) reg_w(sd, 0x23, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) case 20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) reg_w(sd, 0xa4, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) reg_w(sd, 0x23, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) reg_w(sd, 0xa4, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) reg_w(sd, 0x23, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) sd->clockdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) reg_w(sd, 0xa4, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) reg_w(sd, 0x23, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) sd->clockdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) reg_w(sd, 0xa4, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) reg_w(sd, 0x23, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) sd->clockdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) case SEN_OV8610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) switch (sd->frame_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) default: /* 15 fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) /* case 15: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) reg_w(sd, 0xa4, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) reg_w(sd, 0x23, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) reg_w(sd, 0xa4, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) reg_w(sd, 0x23, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) reg_w(sd, 0xa4, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) reg_w(sd, 0x23, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) case SEN_OV7670: /* guesses, based on 7640 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) gspca_dbg(gspca_dev, D_STREAM, "Setting framerate to %d fps\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) (sd->frame_rate == 0) ? 15 : sd->frame_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) reg_w(sd, 0xa4, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) switch (sd->frame_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) case 30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) reg_w(sd, 0x23, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) case 20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) reg_w(sd, 0x23, 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) /* case 15: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) reg_w(sd, 0x23, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) sd->clockdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) static void mode_init_ov_sensor_regs(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) struct gspca_dev *gspca_dev = (struct gspca_dev *)sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) int qvga, xstart, xend, ystart, yend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) qvga = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) /******** Mode (VGA/QVGA) and sensor specific regs ********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) case SEN_OV2610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) i2c_w(sd, 0x24, qvga ? 0x20 : 0x3a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) i2c_w(sd, 0x25, qvga ? 0x30 : 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) i2c_w_mask(sd, 0x67, qvga ? 0xf0 : 0x90, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) case SEN_OV2610AE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) /* frame rates:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) * 10fps / 5 fps for 1600x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) * 40fps / 20fps for 800x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) v = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) if (qvga) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) if (sd->frame_rate < 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) v = 0x81;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) if (sd->frame_rate < 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) v = 0x81;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) i2c_w(sd, 0x11, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) i2c_w(sd, 0x12, qvga ? 0x60 : 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) case SEN_OV3610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) if (qvga) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) xstart = (1040 - gspca_dev->pixfmt.width) / 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) (0x1f << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) ystart = (776 - gspca_dev->pixfmt.height) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) xstart = (2076 - gspca_dev->pixfmt.width) / 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) (0x10 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) ystart = (1544 - gspca_dev->pixfmt.height) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) xend = xstart + gspca_dev->pixfmt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) yend = ystart + gspca_dev->pixfmt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) /* Writing to the COMH register resets the other windowing regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) to their default values, so we must do this first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) i2c_w_mask(sd, 0x12, qvga ? 0x40 : 0x00, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) i2c_w_mask(sd, 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) (((xend >> 1) & 7) << 3) | ((xstart >> 1) & 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) i2c_w_mask(sd, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) (((yend >> 1) & 3) << 2) | ((ystart >> 1) & 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) i2c_w(sd, 0x17, xstart >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) i2c_w(sd, 0x18, xend >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) i2c_w(sd, 0x19, ystart >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) i2c_w(sd, 0x1a, yend >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) case SEN_OV8610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) /* For OV8610 qvga means qsvga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) i2c_w_mask(sd, OV7610_REG_COM_C, qvga ? (1 << 5) : 0, 1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) i2c_w_mask(sd, 0x2d, 0x00, 0x40); /* from windrv 090403 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) i2c_w_mask(sd, 0x28, 0x20, 0x20); /* progressive mode on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) case SEN_OV7610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) i2c_w(sd, 0x35, qvga ? 0x1e : 0x9e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) case SEN_OV7620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) case SEN_OV7620AE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) case SEN_OV76BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) i2c_w(sd, 0x24, qvga ? 0x20 : 0x3a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) i2c_w(sd, 0x25, qvga ? 0x30 : 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) i2c_w_mask(sd, 0x67, qvga ? 0xb0 : 0x90, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) if (sd->sensor == SEN_OV76BE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) i2c_w(sd, 0x35, qvga ? 0x1e : 0x9e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) case SEN_OV7640:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) case SEN_OV7648:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) i2c_w_mask(sd, 0x28, qvga ? 0x00 : 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) /* Setting this undocumented bit in qvga mode removes a very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) annoying vertical shaking of the image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) i2c_w_mask(sd, 0x2d, qvga ? 0x40 : 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) /* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) i2c_w_mask(sd, 0x67, qvga ? 0xf0 : 0x90, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) /* Allow higher automatic gain (to allow higher framerates) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) i2c_w_mask(sd, 0x74, qvga ? 0x20 : 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) i2c_w_mask(sd, 0x12, 0x04, 0x04); /* AWB: 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) case SEN_OV7670:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) /* set COM7_FMT_VGA or COM7_FMT_QVGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) * do we need to set anything else?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) * HSTART etc are set in set_ov_sensor_window itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) i2c_w_mask(sd, OV7670_R12_COM7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) qvga ? OV7670_COM7_FMT_QVGA : OV7670_COM7_FMT_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) OV7670_COM7_FMT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_AWB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) OV7670_COM8_AWB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) if (qvga) { /* QVGA from ov7670.c by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) * Jonathan Corbet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) xstart = 164;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) xend = 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) ystart = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) yend = 494;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) } else { /* VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) xstart = 158;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) xend = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) ystart = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) yend = 490;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) /* OV7670 hardware window registers are split across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) * multiple locations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) i2c_w(sd, OV7670_R17_HSTART, xstart >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) i2c_w(sd, OV7670_R18_HSTOP, xend >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) v = i2c_r(sd, OV7670_R32_HREF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) v = (v & 0xc0) | ((xend & 0x7) << 3) | (xstart & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) msleep(10); /* need to sleep between read and write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) * same reg! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) i2c_w(sd, OV7670_R32_HREF, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) i2c_w(sd, OV7670_R19_VSTART, ystart >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) i2c_w(sd, OV7670_R1A_VSTOP, yend >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) v = i2c_r(sd, OV7670_R03_VREF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) v = (v & 0xc0) | ((yend & 0x3) << 2) | (ystart & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) msleep(10); /* need to sleep between read and write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) * same reg! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) i2c_w(sd, OV7670_R03_VREF, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) case SEN_OV6620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) i2c_w_mask(sd, 0x13, 0x00, 0x20); /* Select 16 bit data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) case SEN_OV6630:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) case SEN_OV66308AF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) i2c_w_mask(sd, 0x12, 0x04, 0x06); /* AWB: 1 Test pattern: 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) case SEN_OV9600: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) const struct ov_i2c_regvals *vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) static const struct ov_i2c_regvals sxga_15[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) {0x11, 0x80}, {0x14, 0x3e}, {0x24, 0x85}, {0x25, 0x75}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) static const struct ov_i2c_regvals sxga_7_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) {0x11, 0x81}, {0x14, 0x3e}, {0x24, 0x85}, {0x25, 0x75}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) static const struct ov_i2c_regvals vga_30[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) {0x11, 0x81}, {0x14, 0x7e}, {0x24, 0x70}, {0x25, 0x60}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) static const struct ov_i2c_regvals vga_15[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) {0x11, 0x83}, {0x14, 0x3e}, {0x24, 0x80}, {0x25, 0x70}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) /* frame rates:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) * 15fps / 7.5 fps for 1280x1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) * 30fps / 15fps for 640x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) i2c_w_mask(sd, 0x12, qvga ? 0x40 : 0x00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) if (qvga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) vals = sd->frame_rate < 30 ? vga_15 : vga_30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) vals = sd->frame_rate < 15 ? sxga_7_5 : sxga_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) write_i2c_regvals(sd, vals, ARRAY_SIZE(sxga_15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) /******** Clock programming ********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) i2c_w(sd, 0x11, sd->clockdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) /* this function works for bridge ov519 and sensors ov7660 and ov7670 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) static void sethvflip(struct gspca_dev *gspca_dev, s32 hflip, s32 vflip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) if (sd->gspca_dev.streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) reg_w(sd, OV519_R51_RESET1, 0x0f); /* block stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) i2c_w_mask(sd, OV7670_R1E_MVFP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) OV7670_MVFP_MIRROR * hflip | OV7670_MVFP_VFLIP * vflip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) OV7670_MVFP_MIRROR | OV7670_MVFP_VFLIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) if (sd->gspca_dev.streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) reg_w(sd, OV519_R51_RESET1, 0x00); /* restart stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) static void set_ov_sensor_window(struct sd *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) struct gspca_dev *gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) int qvga, crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) int hwsbase, hwebase, vwsbase, vwebase, hwscale, vwscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) /* mode setup is fully handled in mode_init_ov_sensor_regs for these */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) case SEN_OV2610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) case SEN_OV2610AE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) case SEN_OV3610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) case SEN_OV7670:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) case SEN_OV9600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) mode_init_ov_sensor_regs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) case SEN_OV7660:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) ov519_set_mode(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) ov519_set_fr(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) gspca_dev = &sd->gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) qvga = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) crop = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv & 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) /* The different sensor ICs handle setting up of window differently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) * IF YOU SET IT WRONG, YOU WILL GET ALL ZERO ISOC DATA FROM OV51x!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) case SEN_OV8610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) hwsbase = 0x1e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) hwebase = 0x1e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) vwsbase = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) vwebase = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) case SEN_OV7610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) case SEN_OV76BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) hwsbase = 0x38;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) hwebase = 0x3a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) vwsbase = vwebase = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) case SEN_OV6620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) case SEN_OV6630:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) case SEN_OV66308AF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) hwsbase = 0x38;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) hwebase = 0x3a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) vwsbase = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) vwebase = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) if (sd->sensor == SEN_OV66308AF && qvga)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) /* HDG: this fixes U and V getting swapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) hwsbase++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) if (crop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) hwsbase += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) hwebase += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) vwsbase += 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) vwebase += 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) case SEN_OV7620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) case SEN_OV7620AE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) hwsbase = 0x2f; /* From 7620.SET (spec is wrong) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) hwebase = 0x2f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) vwsbase = vwebase = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) case SEN_OV7640:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) case SEN_OV7648:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) hwsbase = 0x1a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) hwebase = 0x1a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) vwsbase = vwebase = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) case SEN_OV6620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) case SEN_OV6630:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) case SEN_OV66308AF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) if (qvga) { /* QCIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) hwscale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) vwscale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) } else { /* CIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) hwscale = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) vwscale = 1; /* The datasheet says 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) * it's wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) case SEN_OV8610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) if (qvga) { /* QSVGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) hwscale = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) vwscale = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) } else { /* SVGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) hwscale = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) vwscale = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) default: /* SEN_OV7xx0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) if (qvga) { /* QVGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) hwscale = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) vwscale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) } else { /* VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) hwscale = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) vwscale = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) mode_init_ov_sensor_regs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) i2c_w(sd, 0x17, hwsbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) i2c_w(sd, 0x18, hwebase + (sd->sensor_width >> hwscale));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) i2c_w(sd, 0x19, vwsbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) i2c_w(sd, 0x1a, vwebase + (sd->sensor_height >> vwscale));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) /* -- start the camera -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) static int sd_start(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) /* Default for most bridges, allow bridge_mode_init_regs to override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) sd->sensor_width = sd->gspca_dev.pixfmt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) sd->sensor_height = sd->gspca_dev.pixfmt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) ov511_mode_init_regs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) case BRIDGE_OV518:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) case BRIDGE_OV518PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) ov518_mode_init_regs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) case BRIDGE_OV519:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) ov519_mode_init_regs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) /* case BRIDGE_OVFX2: nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) case BRIDGE_W9968CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) w9968cf_mode_init_regs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) set_ov_sensor_window(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) /* Force clear snapshot state in case the snapshot button was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) pressed while we weren't streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) sd->snapshot_needs_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) sd_reset_snapshot(gspca_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) sd->first_frame = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) ov51x_restart(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) ov51x_led_control(sd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) return gspca_dev->usb_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) static void sd_stopN(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) ov51x_stop(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) ov51x_led_control(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) static void sd_stop0(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) if (!sd->gspca_dev.present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) if (sd->bridge == BRIDGE_W9968CF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) w9968cf_stop0(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) #if IS_ENABLED(CONFIG_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) /* If the last button state is pressed, release it now! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) if (sd->snapshot_pressed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) input_report_key(gspca_dev->input_dev, KEY_CAMERA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) input_sync(gspca_dev->input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) sd->snapshot_pressed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) if (sd->bridge == BRIDGE_OV519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) reg_w(sd, OV519_R57_SNAPSHOT, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) static void ov51x_handle_button(struct gspca_dev *gspca_dev, u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) if (sd->snapshot_pressed != state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) #if IS_ENABLED(CONFIG_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) input_report_key(gspca_dev->input_dev, KEY_CAMERA, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) input_sync(gspca_dev->input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) sd->snapshot_needs_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) sd->snapshot_pressed = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) /* On the ov511 / ov519 we need to reset the button state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) multiple times, as resetting does not work as long as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) button stays pressed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) case BRIDGE_OV519:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) sd->snapshot_needs_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) static void ov511_pkt_scan(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) u8 *in, /* isoc packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) int len) /* iso packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) /* SOF/EOF packets have 1st to 8th bytes zeroed and the 9th
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) * byte non-zero. The EOF packet has image width/height in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) * 10th and 11th bytes. The 9th byte is given as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) * bit 7: EOF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) * 6: compression enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) * 5: 422/420/400 modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) * 4: 422/420/400 modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) * 3: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) * 2: snapshot button on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) * 1: snapshot frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) * 0: even/odd field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) if (!(in[0] | in[1] | in[2] | in[3] | in[4] | in[5] | in[6] | in[7]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) (in[8] & 0x08)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) ov51x_handle_button(gspca_dev, (in[8] >> 2) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) if (in[8] & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) /* Frame end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) if ((in[9] + 1) * 8 != gspca_dev->pixfmt.width ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) (in[10] + 1) * 8 != gspca_dev->pixfmt.height) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) gspca_err(gspca_dev, "Invalid frame size, got: %dx%d, requested: %dx%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) (in[9] + 1) * 8, (in[10] + 1) * 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) gspca_dev->pixfmt.width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) gspca_dev->pixfmt.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) gspca_dev->last_packet_type = DISCARD_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) /* Add 11 byte footer to frame, might be useful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) gspca_frame_add(gspca_dev, LAST_PACKET, in, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) /* Frame start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) gspca_frame_add(gspca_dev, FIRST_PACKET, in, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) sd->packet_nr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) /* Ignore the packet number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) /* intermediate packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) gspca_frame_add(gspca_dev, INTER_PACKET, in, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) static void ov518_pkt_scan(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) u8 *data, /* isoc packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) int len) /* iso packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) /* A false positive here is likely, until OVT gives me
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) * the definitive SOF/EOF format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) if ((!(data[0] | data[1] | data[2] | data[3] | data[5])) && data[6]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) ov51x_handle_button(gspca_dev, (data[6] >> 1) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) sd->packet_nr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) if (gspca_dev->last_packet_type == DISCARD_PACKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) /* Does this device use packet numbers ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) if (len & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) if (sd->packet_nr == data[len])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) sd->packet_nr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) /* The last few packets of the frame (which are all 0's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) except that they may contain part of the footer), are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) numbered 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) else if (sd->packet_nr == 0 || data[len]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) gspca_err(gspca_dev, "Invalid packet nr: %d (expect: %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) (int)data[len], (int)sd->packet_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) gspca_dev->last_packet_type = DISCARD_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) /* intermediate packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) static void ov519_pkt_scan(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) u8 *data, /* isoc packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) int len) /* iso packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) /* Header of ov519 is 16 bytes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) * Byte Value Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) * 0 0xff magic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) * 1 0xff magic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) * 2 0xff magic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) * 3 0xXX 0x50 = SOF, 0x51 = EOF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) * 9 0xXX 0x01 initial frame without data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) * 0x00 standard frame with image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) * 14 Lo in EOF: length of image data / 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) * 15 Hi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) switch (data[3]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) case 0x50: /* start of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) /* Don't check the button state here, as the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) usually (always ?) changes at EOF and checking it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) here leads to unnecessary snapshot state resets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) #define HDRSZ 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) data += HDRSZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) len -= HDRSZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) #undef HDRSZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) if (data[0] == 0xff || data[1] == 0xd8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) gspca_frame_add(gspca_dev, FIRST_PACKET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) gspca_dev->last_packet_type = DISCARD_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) case 0x51: /* end of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) ov51x_handle_button(gspca_dev, data[11] & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) if (data[9] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) gspca_dev->last_packet_type = DISCARD_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) gspca_frame_add(gspca_dev, LAST_PACKET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) /* intermediate packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) static void ovfx2_pkt_scan(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) u8 *data, /* isoc packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) int len) /* iso packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) gspca_frame_add(gspca_dev, INTER_PACKET, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) /* A short read signals EOF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) if (len < gspca_dev->cam.bulk_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) /* If the frame is short, and it is one of the first ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) the sensor and bridge are still syncing, so drop it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) if (sd->first_frame) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) sd->first_frame--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) if (gspca_dev->image_len <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) sd->gspca_dev.pixfmt.width *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) sd->gspca_dev.pixfmt.height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) gspca_dev->last_packet_type = DISCARD_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) static void sd_pkt_scan(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) u8 *data, /* isoc packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) int len) /* iso packet length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) switch (sd->bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) case BRIDGE_OV511:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) case BRIDGE_OV511PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) ov511_pkt_scan(gspca_dev, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) case BRIDGE_OV518:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) case BRIDGE_OV518PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) ov518_pkt_scan(gspca_dev, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) case BRIDGE_OV519:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) ov519_pkt_scan(gspca_dev, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) case BRIDGE_OVFX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) ovfx2_pkt_scan(gspca_dev, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) case BRIDGE_W9968CF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) w9968cf_pkt_scan(gspca_dev, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) /* -- management routines -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) static void setbrightness(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) static const struct ov_i2c_regvals brit_7660[][7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) {{0x0f, 0x6a}, {0x24, 0x40}, {0x25, 0x2b}, {0x26, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) {0x27, 0xe0}, {0x28, 0xe0}, {0x2c, 0xe0}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) {{0x0f, 0x6a}, {0x24, 0x50}, {0x25, 0x40}, {0x26, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) {0x27, 0xc0}, {0x28, 0xc0}, {0x2c, 0xc0}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) {{0x0f, 0x6a}, {0x24, 0x68}, {0x25, 0x58}, {0x26, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) {0x27, 0xa0}, {0x28, 0xa0}, {0x2c, 0xa0}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) {{0x0f, 0x6a}, {0x24, 0x70}, {0x25, 0x68}, {0x26, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) {0x27, 0x80}, {0x28, 0x80}, {0x2c, 0x80}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) {{0x0f, 0x6a}, {0x24, 0x80}, {0x25, 0x70}, {0x26, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) {0x27, 0x20}, {0x28, 0x20}, {0x2c, 0x20}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) {{0x0f, 0x6a}, {0x24, 0x88}, {0x25, 0x78}, {0x26, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) {0x27, 0x40}, {0x28, 0x40}, {0x2c, 0x40}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) {{0x0f, 0x6a}, {0x24, 0x90}, {0x25, 0x80}, {0x26, 0xd4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) {0x27, 0x60}, {0x28, 0x60}, {0x2c, 0x60}}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) case SEN_OV8610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) case SEN_OV7610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) case SEN_OV76BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) case SEN_OV6620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) case SEN_OV6630:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) case SEN_OV66308AF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) case SEN_OV7640:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) case SEN_OV7648:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) i2c_w(sd, OV7610_REG_BRT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) case SEN_OV7620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) case SEN_OV7620AE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) i2c_w(sd, OV7610_REG_BRT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) case SEN_OV7660:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) write_i2c_regvals(sd, brit_7660[val],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) ARRAY_SIZE(brit_7660[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) case SEN_OV7670:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) /*win trace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) * i2c_w_mask(sd, OV7670_R13_COM8, 0, OV7670_COM8_AEC); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) i2c_w(sd, OV7670_R55_BRIGHT, ov7670_abs_to_sm(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) static void setcontrast(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) static const struct ov_i2c_regvals contrast_7660[][31] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf8}, {0x6f, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) {0x70, 0x58}, {0x71, 0x38}, {0x72, 0x30}, {0x73, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) {0x74, 0x28}, {0x75, 0x28}, {0x76, 0x24}, {0x77, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) {0x78, 0x22}, {0x79, 0x28}, {0x7a, 0x2a}, {0x7b, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3d}, {0x7f, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) {0x80, 0x70}, {0x81, 0x77}, {0x82, 0x7d}, {0x83, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) {0x84, 0x88}, {0x85, 0x8d}, {0x86, 0x96}, {0x87, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) {0x88, 0xb0}, {0x89, 0xc4}, {0x8a, 0xd9}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf8}, {0x6f, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) {0x70, 0x58}, {0x71, 0x40}, {0x72, 0x30}, {0x73, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) {0x74, 0x30}, {0x75, 0x30}, {0x76, 0x2c}, {0x77, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) {0x78, 0x22}, {0x79, 0x28}, {0x7a, 0x2a}, {0x7b, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3d}, {0x7f, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) {0x80, 0x6d}, {0x81, 0x75}, {0x82, 0x7b}, {0x83, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) {0x84, 0x87}, {0x85, 0x8d}, {0x86, 0x98}, {0x87, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) {0x88, 0xb2}, {0x89, 0xc6}, {0x8a, 0xdb}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf0}, {0x6f, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) {0x70, 0x58}, {0x71, 0x48}, {0x72, 0x40}, {0x73, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) {0x74, 0x28}, {0x75, 0x28}, {0x76, 0x28}, {0x77, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) {0x78, 0x26}, {0x79, 0x28}, {0x7a, 0x28}, {0x7b, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3c}, {0x7f, 0x5d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) {0x80, 0x68}, {0x81, 0x71}, {0x82, 0x79}, {0x83, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) {0x84, 0x86}, {0x85, 0x8b}, {0x86, 0x95}, {0x87, 0x9e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) {0x88, 0xb1}, {0x89, 0xc5}, {0x8a, 0xd9}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) {{0x6c, 0xf0}, {0x6d, 0xf0}, {0x6e, 0xf0}, {0x6f, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) {0x70, 0x58}, {0x71, 0x58}, {0x72, 0x48}, {0x73, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) {0x74, 0x38}, {0x75, 0x40}, {0x76, 0x34}, {0x77, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) {0x78, 0x2e}, {0x79, 0x28}, {0x7a, 0x24}, {0x7b, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) {0x7c, 0x0f}, {0x7d, 0x1e}, {0x7e, 0x3c}, {0x7f, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) {0x80, 0x63}, {0x81, 0x6e}, {0x82, 0x77}, {0x83, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) {0x84, 0x87}, {0x85, 0x8f}, {0x86, 0x9c}, {0x87, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) {0x88, 0xc0}, {0x89, 0xd4}, {0x8a, 0xe6}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) {{0x6c, 0xa0}, {0x6d, 0xf0}, {0x6e, 0x90}, {0x6f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) {0x70, 0x70}, {0x71, 0x80}, {0x72, 0x60}, {0x73, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) {0x74, 0x58}, {0x75, 0x60}, {0x76, 0x4c}, {0x77, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) {0x78, 0x38}, {0x79, 0x2a}, {0x7a, 0x20}, {0x7b, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) {0x7c, 0x0a}, {0x7d, 0x14}, {0x7e, 0x26}, {0x7f, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) {0x80, 0x54}, {0x81, 0x64}, {0x82, 0x70}, {0x83, 0x7c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) {0x84, 0x87}, {0x85, 0x93}, {0x86, 0xa6}, {0x87, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) {0x88, 0xd0}, {0x89, 0xe5}, {0x8a, 0xf5}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) {{0x6c, 0x60}, {0x6d, 0x80}, {0x6e, 0x60}, {0x6f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) {0x70, 0x80}, {0x71, 0x80}, {0x72, 0x88}, {0x73, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) {0x74, 0x70}, {0x75, 0x68}, {0x76, 0x64}, {0x77, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) {0x78, 0x3c}, {0x79, 0x22}, {0x7a, 0x10}, {0x7b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) {0x7c, 0x06}, {0x7d, 0x0e}, {0x7e, 0x1a}, {0x7f, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) {0x80, 0x4a}, {0x81, 0x5a}, {0x82, 0x6b}, {0x83, 0x7b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) {0x84, 0x89}, {0x85, 0x96}, {0x86, 0xaf}, {0x87, 0xc3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) {0x88, 0xe1}, {0x89, 0xf2}, {0x8a, 0xfa}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) {{0x6c, 0x20}, {0x6d, 0x40}, {0x6e, 0x20}, {0x6f, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) {0x70, 0x88}, {0x71, 0xc8}, {0x72, 0xc0}, {0x73, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) {0x74, 0xa8}, {0x75, 0xb8}, {0x76, 0x80}, {0x77, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) {0x78, 0x26}, {0x79, 0x10}, {0x7a, 0x08}, {0x7b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) {0x7c, 0x02}, {0x7d, 0x06}, {0x7e, 0x0a}, {0x7f, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) {0x80, 0x33}, {0x81, 0x4c}, {0x82, 0x64}, {0x83, 0x7b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) {0x84, 0x90}, {0x85, 0xa7}, {0x86, 0xc7}, {0x87, 0xde},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) {0x88, 0xf1}, {0x89, 0xf9}, {0x8a, 0xfd}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) case SEN_OV7610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) case SEN_OV6620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) i2c_w(sd, OV7610_REG_CNT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) case SEN_OV6630:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) case SEN_OV66308AF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) i2c_w_mask(sd, OV7610_REG_CNT, val >> 4, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) case SEN_OV8610: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) static const u8 ctab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) 0x03, 0x09, 0x0b, 0x0f, 0x53, 0x6f, 0x35, 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) /* Use Y gamma control instead. Bit 0 enables it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) i2c_w(sd, 0x64, ctab[val >> 5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) case SEN_OV7620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) case SEN_OV7620AE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) static const u8 ctab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) 0x01, 0x05, 0x09, 0x11, 0x15, 0x35, 0x37, 0x57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) 0x5b, 0xa5, 0xa7, 0xc7, 0xc9, 0xcf, 0xef, 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) /* Use Y gamma control instead. Bit 0 enables it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) i2c_w(sd, 0x64, ctab[val >> 4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) case SEN_OV7660:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) write_i2c_regvals(sd, contrast_7660[val],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) ARRAY_SIZE(contrast_7660[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) case SEN_OV7670:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) /* check that this isn't just the same as ov7610 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) i2c_w(sd, OV7670_R56_CONTRAS, val >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) static void setexposure(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) i2c_w(sd, 0x10, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) static void setcolors(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) static const struct ov_i2c_regvals colors_7660[][6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) {{0x4f, 0x28}, {0x50, 0x2a}, {0x51, 0x02}, {0x52, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) {0x53, 0x19}, {0x54, 0x23}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) {{0x4f, 0x47}, {0x50, 0x4a}, {0x51, 0x03}, {0x52, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) {0x53, 0x2c}, {0x54, 0x3e}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) {{0x4f, 0x66}, {0x50, 0x6b}, {0x51, 0x05}, {0x52, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) {0x53, 0x40}, {0x54, 0x59}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) {{0x4f, 0x84}, {0x50, 0x8b}, {0x51, 0x06}, {0x52, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) {0x53, 0x53}, {0x54, 0x73}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) {{0x4f, 0xa3}, {0x50, 0xab}, {0x51, 0x08}, {0x52, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) {0x53, 0x66}, {0x54, 0x8e}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) switch (sd->sensor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) case SEN_OV8610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) case SEN_OV7610:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) case SEN_OV76BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) case SEN_OV6620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) case SEN_OV6630:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) case SEN_OV66308AF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) i2c_w(sd, OV7610_REG_SAT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) case SEN_OV7620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) case SEN_OV7620AE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) /* Use UV gamma control instead. Bits 0 & 7 are reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) /* rc = ov_i2c_write(sd->dev, 0x62, (val >> 9) & 0x7e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) goto out; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) i2c_w(sd, OV7610_REG_SAT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) case SEN_OV7640:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) case SEN_OV7648:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) i2c_w(sd, OV7610_REG_SAT, val & 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) case SEN_OV7660:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) write_i2c_regvals(sd, colors_7660[val],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) ARRAY_SIZE(colors_7660[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) case SEN_OV7670:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) /* supported later once I work out how to do it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) * transparently fail now! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) /* set REG_COM13 values for UV sat auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) static void setautobright(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) i2c_w_mask(sd, 0x2d, val ? 0x10 : 0x00, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) static void setfreq_i(struct sd *sd, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) if (sd->sensor == SEN_OV7660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) || sd->sensor == SEN_OV7670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) case 0: /* Banding filter disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) i2c_w_mask(sd, OV7670_R13_COM8, 0, OV7670_COM8_BFILT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) case 1: /* 50 hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_BFILT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) OV7670_COM8_BFILT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) i2c_w_mask(sd, OV7670_R3B_COM11, 0x08, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) case 2: /* 60 hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_BFILT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) OV7670_COM8_BFILT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) i2c_w_mask(sd, OV7670_R3B_COM11, 0x00, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) case 3: /* Auto hz - ov7670 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) i2c_w_mask(sd, OV7670_R13_COM8, OV7670_COM8_BFILT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) OV7670_COM8_BFILT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) i2c_w_mask(sd, OV7670_R3B_COM11, OV7670_COM11_HZAUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) case 0: /* Banding filter disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) i2c_w_mask(sd, 0x2d, 0x00, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) i2c_w_mask(sd, 0x2a, 0x00, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) case 1: /* 50 hz (filter on and framerate adj) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) i2c_w_mask(sd, 0x2d, 0x04, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) i2c_w_mask(sd, 0x2a, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) /* 20 fps -> 16.667 fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) if (sd->sensor == SEN_OV6620 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) sd->sensor == SEN_OV6630 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) sd->sensor == SEN_OV66308AF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) i2c_w(sd, 0x2b, 0x5e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) i2c_w(sd, 0x2b, 0xac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) case 2: /* 60 hz (filter on, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) i2c_w_mask(sd, 0x2d, 0x04, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) if (sd->sensor == SEN_OV6620 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) sd->sensor == SEN_OV6630 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) sd->sensor == SEN_OV66308AF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) /* 20 fps -> 15 fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) i2c_w_mask(sd, 0x2a, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) i2c_w(sd, 0x2b, 0xa8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) /* no framerate adj. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) i2c_w_mask(sd, 0x2a, 0x00, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) static void setfreq(struct gspca_dev *gspca_dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) setfreq_i(sd, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) /* Ugly but necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) if (sd->bridge == BRIDGE_W9968CF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) w9968cf_set_crop_window(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) static int sd_get_jcomp(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) struct v4l2_jpegcompression *jcomp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) if (sd->bridge != BRIDGE_W9968CF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) memset(jcomp, 0, sizeof *jcomp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) jcomp->quality = v4l2_ctrl_g_ctrl(sd->jpegqual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) jcomp->jpeg_markers = V4L2_JPEG_MARKER_DHT | V4L2_JPEG_MARKER_DQT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) V4L2_JPEG_MARKER_DRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) static int sd_set_jcomp(struct gspca_dev *gspca_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) const struct v4l2_jpegcompression *jcomp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) struct sd *sd = (struct sd *) gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) if (sd->bridge != BRIDGE_W9968CF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) v4l2_ctrl_s_ctrl(sd->jpegqual, jcomp->quality);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) static int sd_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) struct gspca_dev *gspca_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) container_of(ctrl->handler, struct gspca_dev, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) struct sd *sd = (struct sd *)gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) gspca_dev->usb_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) case V4L2_CID_AUTOGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) gspca_dev->exposure->val = i2c_r(sd, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) static int sd_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) struct gspca_dev *gspca_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) container_of(ctrl->handler, struct gspca_dev, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) struct sd *sd = (struct sd *)gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) gspca_dev->usb_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) if (!gspca_dev->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) setbrightness(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) setcontrast(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) case V4L2_CID_POWER_LINE_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) setfreq(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) case V4L2_CID_AUTOBRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) if (ctrl->is_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) setautobright(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) if (!ctrl->val && sd->brightness->is_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) setbrightness(gspca_dev, sd->brightness->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) setcolors(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) sethvflip(gspca_dev, ctrl->val, sd->vflip->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) case V4L2_CID_AUTOGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) if (ctrl->is_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) setautogain(gspca_dev, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) if (!ctrl->val && gspca_dev->exposure->is_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) setexposure(gspca_dev, gspca_dev->exposure->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) case V4L2_CID_JPEG_COMPRESSION_QUALITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) return -EBUSY; /* Should never happen, as we grab the ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) return gspca_dev->usb_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) static const struct v4l2_ctrl_ops sd_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) .g_volatile_ctrl = sd_g_volatile_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) .s_ctrl = sd_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) static int sd_init_controls(struct gspca_dev *gspca_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) struct sd *sd = (struct sd *)gspca_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) struct v4l2_ctrl_handler *hdl = &gspca_dev->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) gspca_dev->vdev.ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) v4l2_ctrl_handler_init(hdl, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) if (valid_controls[sd->sensor].has_brightness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) sd->brightness = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) V4L2_CID_BRIGHTNESS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) sd->sensor == SEN_OV7660 ? 6 : 255, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) sd->sensor == SEN_OV7660 ? 3 : 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) if (valid_controls[sd->sensor].has_contrast) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) if (sd->sensor == SEN_OV7660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) V4L2_CID_CONTRAST, 0, 6, 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) V4L2_CID_CONTRAST, 0, 255, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) (sd->sensor == SEN_OV6630 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) sd->sensor == SEN_OV66308AF) ? 200 : 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) if (valid_controls[sd->sensor].has_sat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) V4L2_CID_SATURATION, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) sd->sensor == SEN_OV7660 ? 4 : 255, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) sd->sensor == SEN_OV7660 ? 2 : 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) if (valid_controls[sd->sensor].has_exposure)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) gspca_dev->exposure = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) V4L2_CID_EXPOSURE, 0, 255, 1, 127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) if (valid_controls[sd->sensor].has_hvflip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) sd->hflip = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) sd->vflip = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) if (valid_controls[sd->sensor].has_autobright)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) sd->autobright = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) V4L2_CID_AUTOBRIGHTNESS, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) if (valid_controls[sd->sensor].has_autogain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) gspca_dev->autogain = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) if (valid_controls[sd->sensor].has_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) if (sd->sensor == SEN_OV7670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) sd->freq = v4l2_ctrl_new_std_menu(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) V4L2_CID_POWER_LINE_FREQUENCY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) sd->freq = v4l2_ctrl_new_std_menu(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) V4L2_CID_POWER_LINE_FREQUENCY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) V4L2_CID_POWER_LINE_FREQUENCY_60HZ, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) if (sd->bridge == BRIDGE_W9968CF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) sd->jpegqual = v4l2_ctrl_new_std(hdl, &sd_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) V4L2_CID_JPEG_COMPRESSION_QUALITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) QUALITY_MIN, QUALITY_MAX, 1, QUALITY_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) gspca_err(gspca_dev, "Could not initialize controls\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) if (gspca_dev->autogain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) v4l2_ctrl_auto_cluster(3, &gspca_dev->autogain, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) if (sd->autobright)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) v4l2_ctrl_auto_cluster(2, &sd->autobright, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) if (sd->hflip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) v4l2_ctrl_cluster(2, &sd->hflip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) /* sub-driver description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) static const struct sd_desc sd_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) .name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) .config = sd_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) .init = sd_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) .init_controls = sd_init_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) .isoc_init = sd_isoc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) .start = sd_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) .stopN = sd_stopN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) .stop0 = sd_stop0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) .pkt_scan = sd_pkt_scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) .dq_callback = sd_reset_snapshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) .get_jcomp = sd_get_jcomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) .set_jcomp = sd_set_jcomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) #if IS_ENABLED(CONFIG_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) .other_input = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) /* -- module initialisation -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) static const struct usb_device_id device_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) {USB_DEVICE(0x041e, 0x4003), .driver_info = BRIDGE_W9968CF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) {USB_DEVICE(0x041e, 0x4052),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) {USB_DEVICE(0x041e, 0x405f), .driver_info = BRIDGE_OV519 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) {USB_DEVICE(0x041e, 0x4060), .driver_info = BRIDGE_OV519 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) {USB_DEVICE(0x041e, 0x4061), .driver_info = BRIDGE_OV519 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) {USB_DEVICE(0x041e, 0x4064), .driver_info = BRIDGE_OV519 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) {USB_DEVICE(0x041e, 0x4067), .driver_info = BRIDGE_OV519 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) {USB_DEVICE(0x041e, 0x4068), .driver_info = BRIDGE_OV519 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) {USB_DEVICE(0x045e, 0x028c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) {USB_DEVICE(0x054c, 0x0154), .driver_info = BRIDGE_OV519 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) {USB_DEVICE(0x054c, 0x0155), .driver_info = BRIDGE_OV519 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) {USB_DEVICE(0x05a9, 0x0511), .driver_info = BRIDGE_OV511 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) {USB_DEVICE(0x05a9, 0x0518), .driver_info = BRIDGE_OV518 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) {USB_DEVICE(0x05a9, 0x0519),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) {USB_DEVICE(0x05a9, 0x0530),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) .driver_info = BRIDGE_OV519 | BRIDGE_INVERT_LED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) {USB_DEVICE(0x05a9, 0x2800), .driver_info = BRIDGE_OVFX2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) {USB_DEVICE(0x05a9, 0x4519), .driver_info = BRIDGE_OV519 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) {USB_DEVICE(0x05a9, 0x8519), .driver_info = BRIDGE_OV519 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) {USB_DEVICE(0x05a9, 0xa511), .driver_info = BRIDGE_OV511PLUS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) {USB_DEVICE(0x05a9, 0xa518), .driver_info = BRIDGE_OV518PLUS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) {USB_DEVICE(0x0813, 0x0002), .driver_info = BRIDGE_OV511PLUS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) {USB_DEVICE(0x0b62, 0x0059), .driver_info = BRIDGE_OVFX2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) {USB_DEVICE(0x0e96, 0xc001), .driver_info = BRIDGE_OVFX2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) {USB_DEVICE(0x1046, 0x9967), .driver_info = BRIDGE_W9968CF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) {USB_DEVICE(0x8020, 0xef04), .driver_info = BRIDGE_OVFX2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) MODULE_DEVICE_TABLE(usb, device_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) /* -- device connect -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) static int sd_probe(struct usb_interface *intf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) const struct usb_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) return gspca_dev_probe(intf, id, &sd_desc, sizeof(struct sd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) static struct usb_driver sd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) .name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) .id_table = device_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) .probe = sd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) .disconnect = gspca_disconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) .suspend = gspca_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) .resume = gspca_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) .reset_resume = gspca_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) module_usb_driver(sd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) module_param(frame_rate, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) MODULE_PARM_DESC(frame_rate, "Frame rate (5, 10, 15, 20 or 30 fps)");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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