Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * em28xx-reg.h - Register definitions for em28xx driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define EM_GPIO_0  ((unsigned char)BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define EM_GPIO_1  ((unsigned char)BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define EM_GPIO_2  ((unsigned char)BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define EM_GPIO_3  ((unsigned char)BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define EM_GPIO_4  ((unsigned char)BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define EM_GPIO_5  ((unsigned char)BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define EM_GPIO_6  ((unsigned char)BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define EM_GPIO_7  ((unsigned char)BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define EM_GPO_0   ((unsigned char)BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define EM_GPO_1   ((unsigned char)BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define EM_GPO_2   ((unsigned char)BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define EM_GPO_3   ((unsigned char)BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* em28xx endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* 0x82:   (always ?) analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define EM28XX_EP_AUDIO		0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* 0x84:   digital or analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* em2800 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define EM2800_R08_AUDIOSRC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* em28xx registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define EM28XX_R00_CHIPCFG	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* em28xx Chip Configuration 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define EM2860_CHIPCFG_VENDOR_AUDIO		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define EM2860_CHIPCFG_I2S_VOLUME_CAPABLE	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define EM2820_CHIPCFG_I2S_3_SAMPRATES		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define EM2860_CHIPCFG_I2S_5_SAMPRATES		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define EM2820_CHIPCFG_I2S_1_SAMPRATE		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define EM2860_CHIPCFG_I2S_3_SAMPRATES		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define EM28XX_CHIPCFG_AC97			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define EM28XX_CHIPCFG_AUDIOMASK		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define EM28XX_R01_CHIPCFG2	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* em28xx Chip Configuration 2 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define EM28XX_CHIPCFG2_TS_PRESENT		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_MASK	0x0c /* bits 3-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_1MF	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_2MF	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_4MF	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_8MF	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK	0x03 /* bits 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define EM28XX_CHIPCFG2_TS_PACKETSIZE_188	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define EM28XX_CHIPCFG2_TS_PACKETSIZE_376	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define EM28XX_CHIPCFG2_TS_PACKETSIZE_564	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define EM28XX_CHIPCFG2_TS_PACKETSIZE_752	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* GPIO/GPO registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define EM2880_R04_GPO		0x04    /* em2880-em2883 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define EM2820_R08_GPIO_CTRL	0x08	/* em2820-em2873/83 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define EM2820_R09_GPIO_STATE	0x09	/* em2820-em2873/83 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define EM28XX_R06_I2C_CLK	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* em28xx I2C Clock Register (0x06) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define EM28XX_I2C_CLK_ACK_LAST_READ	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define EM28XX_I2C_CLK_WAIT_ENABLE	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define EM28XX_I2C_EEPROM_ON_BOARD	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define EM28XX_I2C_EEPROM_KEY_VALID	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define EM2874_I2C_SECONDARY_BUS_SELECT	0x04 /* em2874 has two i2c buses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define EM28XX_I2C_FREQ_1_5_MHZ		0x03 /* bus frequency (bits [1-0]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define EM28XX_I2C_FREQ_25_KHZ		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define EM28XX_I2C_FREQ_400_KHZ		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define EM28XX_I2C_FREQ_100_KHZ		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define EM28XX_R0A_CHIPID	0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define EM28XX_R0C_USBSUSP	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define   EM28XX_R0C_USBSUSP_SNAPSHOT	0x20 /* 1=button pressed, needs reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define EM28XX_R0E_AUDIOSRC	0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define EM28XX_R0F_XCLK	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* em28xx XCLK Register (0x0f) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define EM28XX_XCLK_AUDIO_UNMUTE	0x80 /* otherwise audio muted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define EM28XX_XCLK_I2S_MSB_TIMING	0x40 /* otherwise standard timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define EM28XX_XCLK_IR_RC5_MODE		0x20 /* otherwise NEC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define EM28XX_XCLK_IR_NEC_CHK_PARITY	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define EM28XX_XCLK_FREQUENCY_30MHZ	0x00 /* Freq. select (bits [3-0]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define EM28XX_XCLK_FREQUENCY_15MHZ	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define EM28XX_XCLK_FREQUENCY_10MHZ	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define EM28XX_XCLK_FREQUENCY_7_5MHZ	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define EM28XX_XCLK_FREQUENCY_6MHZ	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define EM28XX_XCLK_FREQUENCY_5MHZ	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define EM28XX_XCLK_FREQUENCY_4_3MHZ	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define EM28XX_XCLK_FREQUENCY_12MHZ	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define EM28XX_XCLK_FREQUENCY_20MHZ	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define EM28XX_XCLK_FREQUENCY_20MHZ_2	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define EM28XX_XCLK_FREQUENCY_48MHZ	0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define EM28XX_XCLK_FREQUENCY_24MHZ	0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define EM28XX_R10_VINMODE	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	  /* used by all non-camera devices: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define   EM28XX_VINMODE_YUV422_CbYCrY  0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	  /* used by camera devices: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define   EM28XX_VINMODE_YUV422_YUYV    0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define   EM28XX_VINMODE_YUV422_YVYU    0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define   EM28XX_VINMODE_YUV422_UYVY    0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define   EM28XX_VINMODE_YUV422_VYUY    0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define   EM28XX_VINMODE_RGB8_BGGR      0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define   EM28XX_VINMODE_RGB8_GRBG      0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define   EM28XX_VINMODE_RGB8_GBRG      0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define   EM28XX_VINMODE_RGB8_RGGB      0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	  /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	   * apparently:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	   *   bit 0: swap component 1+2 with 3+4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	   *                 => e.g.: YUYV => YVYU, BGGR => GRBG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	   *   bit 1: swap component 1 with 2 and 3 with 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	   *                 => e.g.: YUYV => UYVY, BGGR => GBRG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define EM28XX_R11_VINCTRL	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* em28xx Video Input Control Register 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EM28XX_VINCTRL_VBI_SLICED	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EM28XX_VINCTRL_VBI_RAW		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EM28XX_VINCTRL_VOUT_MODE_IN	0x20 /* HREF,VREF,VACT in output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define EM28XX_VINCTRL_CCIR656_ENABLE	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define EM28XX_VINCTRL_VBI_16BIT_RAW	0x08 /* otherwise 8-bit raw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define EM28XX_VINCTRL_FID_ON_HREF	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define EM28XX_VINCTRL_DUAL_EDGE_STROBE	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EM28XX_VINCTRL_INTERLACED	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define EM28XX_R12_VINENABLE	0x12	/* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define EM28XX_R14_GAMMA	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define EM28XX_R15_RGAIN	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define EM28XX_R16_GGAIN	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define EM28XX_R17_BGAIN	0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EM28XX_R18_ROFFSET	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define EM28XX_R19_GOFFSET	0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EM28XX_R1A_BOFFSET	0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EM28XX_R1B_OFLOW	0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define EM28XX_R1C_HSTART	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EM28XX_R1D_VSTART	0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define EM28XX_R1E_CWIDTH	0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EM28XX_R1F_CHEIGHT	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define EM28XX_R20_YGAIN	0x20 /* contrast [0:4]   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define   CONTRAST_DEFAULT	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define EM28XX_R21_YOFFSET	0x21 /* brightness       */	/* signed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define   BRIGHTNESS_DEFAULT	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EM28XX_R22_UVGAIN	0x22 /* saturation [0:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define   SATURATION_DEFAULT	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define EM28XX_R23_UOFFSET	0x23 /* blue balance     */	/* signed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define   BLUE_BALANCE_DEFAULT	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EM28XX_R24_VOFFSET	0x24 /* red balance      */	/* signed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define   RED_BALANCE_DEFAULT	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define EM28XX_R25_SHARPNESS	0x25 /* sharpness [0:4]  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define   SHARPNESS_DEFAULT	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EM28XX_R26_COMPR	0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EM28XX_R27_OUTFMT	0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* em28xx Output Format Register (0x27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define EM28XX_OUTFMT_RGB_8_RGRG	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define EM28XX_OUTFMT_RGB_8_GRGR	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EM28XX_OUTFMT_RGB_8_GBGB	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define EM28XX_OUTFMT_RGB_8_BGBG	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EM28XX_OUTFMT_RGB_16_656	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define EM28XX_OUTFMT_RGB_8_BAYER	0x08 /* Pattern in Reg 0x10[1-0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define EM28XX_OUTFMT_YUV211		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define EM28XX_OUTFMT_YUV422_Y0UY1V	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define EM28XX_OUTFMT_YUV422_Y1UY0V	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EM28XX_OUTFMT_YUV411		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define EM28XX_R28_XMIN	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define EM28XX_R29_XMAX	0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define EM28XX_R2A_YMIN	0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define EM28XX_R2B_YMAX	0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define EM28XX_R30_HSCALELOW	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define EM28XX_R31_HSCALEHIGH	0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define EM28XX_R32_VSCALELOW	0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define EM28XX_R33_VSCALEHIGH	0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define   EM28XX_HVSCALE_MAX	0x3fff /* => 20% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define EM28XX_R34_VBI_START_H	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define EM28XX_R35_VBI_START_V	0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  * NOTE: the EM276x (and EM25xx, EM277x/8x ?) (camera bridges) use these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * registers for a different unknown purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  *   => register 0x34 is set to capture width / 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  *   => register 0x35 is set to capture height / 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define EM28XX_R36_VBI_WIDTH	0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define EM28XX_R37_VBI_HEIGHT	0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define EM28XX_R40_AC97LSB	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define EM28XX_R41_AC97MSB	0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define EM28XX_R42_AC97ADDR	0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define EM28XX_R43_AC97BUSY	0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define EM28XX_R45_IR		0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 * 0x45  bit 7    - parity bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 *	 bits 6-0 - count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 * 0x46  IR brand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 *  0x47  IR data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* em2874 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define EM2874_R50_IR_CONFIG    0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define EM2874_R51_IR           0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define EM2874_R5D_TS1_PKT_SIZE 0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define EM2874_R5E_TS2_PKT_SIZE 0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	 * For both TS1 and TS2, In isochronous mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	 *  0x01  188 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 *  0x02  376 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 *  0x03  564 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 *  0x04  752 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 *  0x05  940 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 * In bulk mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 *  0x01..0xff  total packet count in 188-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define EM2874_R5F_TS_ENABLE    0x5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* em2874/174/84, em25xx, em276x/7x/8x GPIO registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * NOTE: not all ports are bonded out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * Some ports are multiplexed with special function I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define EM2874_R80_GPIO_P0_CTRL    0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define EM2874_R81_GPIO_P1_CTRL    0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define EM2874_R82_GPIO_P2_CTRL    0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define EM2874_R83_GPIO_P3_CTRL    0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define EM2874_R84_GPIO_P0_STATE   0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define EM2874_R85_GPIO_P1_STATE   0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define EM2874_R86_GPIO_P2_STATE   0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define EM2874_R87_GPIO_P3_STATE   0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* em2874 IR config register (0x50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define EM2874_IR_NEC           0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define EM2874_IR_NEC_NO_PARITY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define EM2874_IR_RC5           0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define EM2874_IR_RC6_MODE_0    0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define EM2874_IR_RC6_MODE_6A   0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* em2874 Transport Stream Enable Register (0x5f) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define EM2874_TS1_CAPTURE_ENABLE ((unsigned char)BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define EM2874_TS1_FILTER_ENABLE  ((unsigned char)BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define EM2874_TS1_NULL_DISCARD   ((unsigned char)BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define EM2874_TS2_CAPTURE_ENABLE ((unsigned char)BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define EM2874_TS2_FILTER_ENABLE  ((unsigned char)BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define EM2874_TS2_NULL_DISCARD   ((unsigned char)BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* register settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define EM2800_AUDIO_SRC_TUNER  0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define EM2800_AUDIO_SRC_LINE   0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define EM28XX_AUDIO_SRC_TUNER	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define EM28XX_AUDIO_SRC_LINE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* FIXME: Need to be populated with the other chip ID's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) enum em28xx_chip_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	CHIP_ID_EM2800 = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	CHIP_ID_EM2710 = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	CHIP_ID_EM2820 = 18,	/* Also used by some em2710 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	CHIP_ID_EM2840 = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	CHIP_ID_EM2750 = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	CHIP_ID_EM2860 = 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	CHIP_ID_EM2870 = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	CHIP_ID_EM2883 = 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	CHIP_ID_EM2765 = 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	CHIP_ID_EM2874 = 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	CHIP_ID_EM2884 = 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	CHIP_ID_EM28174 = 113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	CHIP_ID_EM28178 = 114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  * Registers used by em202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* EMP202 vendor registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define EM202_EXT_MODEM_CTRL     0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define EM202_GPIO_CONF          0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define EM202_GPIO_POLARITY      0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define EM202_GPIO_STICKY        0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define EM202_GPIO_MASK          0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define EM202_GPIO_STATUS        0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define EM202_SPDIF_OUT_SEL      0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define EM202_ANTIPOP            0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define EM202_EAPD_GPIO_ACCESS   0x74