^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // em28xx-i2c.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Markus Rechberger <mrechberger@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Mauro Carvalho Chehab <mchehab@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Sascha Sommer <saschasommer@freenet.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Copyright (C) 2013 Frank Schäfer <fschaefer.oss@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) // This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) // it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) // the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) // (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) // This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) // but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) // GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "em28xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "tuner-xc2028.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/tuner.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static unsigned int i2c_scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) module_param(i2c_scan, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static unsigned int i2c_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) module_param(i2c_debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MODULE_PARM_DESC(i2c_debug, "i2c debug message level (1: normal debug, 2: show I2C transfers)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define dprintk(level, fmt, arg...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (i2c_debug > level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) dev_printk(KERN_DEBUG, &dev->intf->dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "i2c: %s: " fmt, __func__, ## arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Time in msecs to wait for i2c xfers to finish.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 35ms is the maximum time a SMBUS device could wait when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * clock stretching is used. As the transfer itself will take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * some time to happen, set it to 35 ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Ok, I2C doesn't specify any limit. So, eventually, we may need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * to increase this timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EM28XX_I2C_XFER_TIMEOUT 35 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int em28xx_i2c_timeout(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int time = EM28XX_I2C_XFER_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) switch (dev->i2c_speed & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) case EM28XX_I2C_FREQ_25_KHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) time += 4; /* Assume 4 ms for transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case EM28XX_I2C_FREQ_100_KHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) case EM28XX_I2C_FREQ_400_KHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) time += 1; /* Assume 1 ms for transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) default: /* EM28XX_I2C_FREQ_1_5_MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return msecs_to_jiffies(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * em2800_i2c_send_bytes()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * send up to 4 bytes to the em2800 i2c device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int em2800_i2c_send_bytes(struct em28xx *dev, u8 addr, u8 *buf, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long timeout = jiffies + em28xx_i2c_timeout(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 b2[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (len < 1 || len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) b2[5] = 0x80 + len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) b2[4] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) b2[3] = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (len > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) b2[2] = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (len > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) b2[1] = buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (len > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) b2[0] = buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* trigger write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = dev->em28xx_write_regs(dev, 4 - len, &b2[4 - len], 2 + len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret != 2 + len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "failed to trigger write to i2c address 0x%x (error=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return (ret < 0) ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) while (time_is_after_jiffies(timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = dev->em28xx_read_reg(dev, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (ret == 0x80 + len - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret == 0x94 + len - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dprintk(1, "R05 returned 0x%02x: I2C ACK error\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "failed to get i2c transfer status from bridge register (error=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dprintk(0, "write to i2c device at 0x%x timed out\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * em2800_i2c_recv_bytes()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * read up to 4 bytes from the em2800 i2c device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int em2800_i2c_recv_bytes(struct em28xx *dev, u8 addr, u8 *buf, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long timeout = jiffies + em28xx_i2c_timeout(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 buf2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (len < 1 || len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* trigger read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) buf2[1] = 0x84 + len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) buf2[0] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = dev->em28xx_write_regs(dev, 0x04, buf2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "failed to trigger read from i2c address 0x%x (error=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return (ret < 0) ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) while (time_is_after_jiffies(timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = dev->em28xx_read_reg(dev, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (ret == 0x84 + len - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret == 0x94 + len - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dprintk(1, "R05 returned 0x%02x: I2C ACK error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "failed to get i2c transfer status from bridge register (error=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret != 0x84 + len - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dprintk(0, "read from i2c device at 0x%x timed out\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* get the received message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = dev->em28xx_read_reg_req_len(dev, 0x00, 4 - len, buf2, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret != len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "reading from i2c device at 0x%x failed: couldn't get the received message from the bridge (error=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return (ret < 0) ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) buf[i] = buf2[len - 1 - i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * em2800_i2c_check_for_device()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * check if there is an i2c device at the supplied address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int em2800_i2c_check_for_device(struct em28xx *dev, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = em2800_i2c_recv_bytes(dev, addr, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return (ret < 0) ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * em28xx_i2c_send_bytes()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int em28xx_i2c_send_bytes(struct em28xx *dev, u16 addr, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u16 len, int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned long timeout = jiffies + em28xx_i2c_timeout(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (len < 1 || len > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * NOTE: limited by the USB ctrl message constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Zero length reads always succeed, even if no device is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Write to i2c device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = dev->em28xx_write_regs_req(dev, stop ? 2 : 3, addr, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret != len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "writing to i2c device at 0x%x failed (error=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "%i bytes write to i2c device at 0x%x requested, but %i bytes written\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) len, addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) while (time_is_after_jiffies(timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret = dev->em28xx_read_reg(dev, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (ret == 0) /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret == 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dprintk(1, "I2C ACK error on writing to addr 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "failed to get i2c transfer status from bridge register (error=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * NOTE: do we really have to wait for success ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Never seen anything else than 0x00 or 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * (even with high payload) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret == 0x02 || ret == 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* NOTE: these errors seem to be related to clock stretching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dprintk(0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "write to i2c device at 0x%x timed out (status=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "write to i2c device at 0x%x failed with unknown error (status=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * em28xx_i2c_recv_bytes()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * read a byte from the i2c device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int em28xx_i2c_recv_bytes(struct em28xx *dev, u16 addr, u8 *buf, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (len < 1 || len > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * NOTE: limited by the USB ctrl message constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Zero length reads always succeed, even if no device is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Read data from i2c device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = dev->em28xx_read_reg_req_len(dev, 2, addr, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "reading from i2c device at 0x%x failed (error=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * NOTE: some devices with two i2c buses have the bad habit to return 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * bytes if we are on bus B AND there was no write attempt to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * specified slave address before AND no device is present at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * requested slave address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Anyway, the next check will fail with -ENXIO in this case, so avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * spamming the system log on device probing and do nothing here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Check success of the i2c operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = dev->em28xx_read_reg(dev, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret == 0) /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "failed to get i2c transfer status from bridge register (error=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (ret == 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dprintk(1, "I2C ACK error on writing to addr 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret == 0x02 || ret == 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* NOTE: these errors seem to be related to clock stretching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dprintk(0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "write to i2c device at 0x%x timed out (status=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "write to i2c device at 0x%x failed with unknown error (status=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * em28xx_i2c_check_for_device()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * check if there is a i2c_device at the supplied address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int em28xx_i2c_check_for_device(struct em28xx *dev, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = em28xx_i2c_recv_bytes(dev, addr, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return (ret < 0) ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * em25xx_bus_B_send_bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * write bytes to the i2c device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int em25xx_bus_B_send_bytes(struct em28xx *dev, u16 addr, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (len < 1 || len > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * NOTE: limited by the USB ctrl message constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Zero length reads always succeed, even if no device is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Set register and write value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = dev->em28xx_write_regs_req(dev, 0x06, addr, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret != len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "writing to i2c device at 0x%x failed (error=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "%i bytes write to i2c device at 0x%x requested, but %i bytes written\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) len, addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Check success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = dev->em28xx_read_reg_req(dev, 0x08, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * NOTE: the only error we've seen so far is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * 0x01 when the slave device is not present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dprintk(1, "Bus B R08 returned 0x%02x: I2C ACK error\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * NOTE: With chip types (other chip IDs) which actually don't support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * this operation, it seems to succeed ALWAYS ! (even if there is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * slave device or even no second i2c bus provided)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * em25xx_bus_B_recv_bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * read bytes from the i2c device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int em25xx_bus_B_recv_bytes(struct em28xx *dev, u16 addr, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (len < 1 || len > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * NOTE: limited by the USB ctrl message constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Zero length reads always succeed, even if no device is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Read value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = dev->em28xx_read_reg_req_len(dev, 0x06, addr, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "reading from i2c device at 0x%x failed (error=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * NOTE: some devices with two i2c buses have the bad habit to return 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * bytes if we are on bus B AND there was no write attempt to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * specified slave address before AND no device is present at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * requested slave address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * Anyway, the next check will fail with -ENXIO in this case, so avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * spamming the system log on device probing and do nothing here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Check success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = dev->em28xx_read_reg_req(dev, 0x08, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * NOTE: the only error we've seen so far is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * 0x01 when the slave device is not present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (ret > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dprintk(1, "Bus B R08 returned 0x%02x: I2C ACK error\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * NOTE: With chip types (other chip IDs) which actually don't support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * this operation, it seems to succeed ALWAYS ! (even if there is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * slave device or even no second i2c bus provided)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * em25xx_bus_B_check_for_device()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * check if there is a i2c device at the supplied address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int em25xx_bus_B_check_for_device(struct em28xx *dev, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = em25xx_bus_B_recv_bytes(dev, addr, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * NOTE: With chips which do not support this operation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * it seems to succeed ALWAYS ! (even if no device connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static inline int i2c_check_for_device(struct em28xx_i2c_bus *i2c_bus, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct em28xx *dev = i2c_bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int rc = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (i2c_bus->algo_type == EM28XX_I2C_ALGO_EM28XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) rc = em28xx_i2c_check_for_device(dev, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) else if (i2c_bus->algo_type == EM28XX_I2C_ALGO_EM2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) rc = em2800_i2c_check_for_device(dev, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else if (i2c_bus->algo_type == EM28XX_I2C_ALGO_EM25XX_BUS_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) rc = em25xx_bus_B_check_for_device(dev, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static inline int i2c_recv_bytes(struct em28xx_i2c_bus *i2c_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct i2c_msg msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct em28xx *dev = i2c_bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u16 addr = msg.addr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int rc = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (i2c_bus->algo_type == EM28XX_I2C_ALGO_EM28XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) rc = em28xx_i2c_recv_bytes(dev, addr, msg.buf, msg.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) else if (i2c_bus->algo_type == EM28XX_I2C_ALGO_EM2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) rc = em2800_i2c_recv_bytes(dev, addr, msg.buf, msg.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) else if (i2c_bus->algo_type == EM28XX_I2C_ALGO_EM25XX_BUS_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) rc = em25xx_bus_B_recv_bytes(dev, addr, msg.buf, msg.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static inline int i2c_send_bytes(struct em28xx_i2c_bus *i2c_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct i2c_msg msg, int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct em28xx *dev = i2c_bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u16 addr = msg.addr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int rc = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (i2c_bus->algo_type == EM28XX_I2C_ALGO_EM28XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) rc = em28xx_i2c_send_bytes(dev, addr, msg.buf, msg.len, stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) else if (i2c_bus->algo_type == EM28XX_I2C_ALGO_EM2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) rc = em2800_i2c_send_bytes(dev, addr, msg.buf, msg.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) else if (i2c_bus->algo_type == EM28XX_I2C_ALGO_EM25XX_BUS_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) rc = em25xx_bus_B_send_bytes(dev, addr, msg.buf, msg.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * em28xx_i2c_xfer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * the main i2c transfer function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int em28xx_i2c_xfer(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct em28xx_i2c_bus *i2c_bus = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct em28xx *dev = i2c_bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned int bus = i2c_bus->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int addr, rc, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * prevent i2c xfer attempts after device is disconnected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * some fe's try to do i2c writes/reads from their release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * interfaces when called in disconnect path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (dev->disconnected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (!rt_mutex_trylock(&dev->i2c_bus_lock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Switch I2C bus if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (bus != dev->cur_i2c_bus &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) i2c_bus->algo_type == EM28XX_I2C_ALGO_EM28XX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (bus == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) reg = EM2874_I2C_SECONDARY_BUS_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) em28xx_write_reg_bits(dev, EM28XX_R06_I2C_CLK, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) EM2874_I2C_SECONDARY_BUS_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev->cur_i2c_bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) addr = msgs[i].addr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!msgs[i].len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * no len: check only for device presence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * This code is only called during device probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) rc = i2c_check_for_device(i2c_bus, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (rc == -ENXIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) } else if (msgs[i].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* read bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) rc = i2c_recv_bytes(i2c_bus, msgs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* write bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) rc = i2c_send_bytes(i2c_bus, msgs[i], i == num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dprintk(2, "%s %s addr=%02x len=%d: %*ph\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) (msgs[i].flags & I2C_M_RD) ? "read" : "write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) i == num - 1 ? "stop" : "nonstop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) addr, msgs[i].len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) msgs[i].len, msgs[i].buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) rt_mutex_unlock(&dev->i2c_bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dprintk(2, "%s %s addr=%02x len=%d: %sERROR: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) (msgs[i].flags & I2C_M_RD) ? "read" : "write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) i == num - 1 ? "stop" : "nonstop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) addr, msgs[i].len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) (rc == -ENODEV) ? "no device " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rt_mutex_unlock(&dev->i2c_bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * based on linux/sunrpc/svcauth.h and linux/hash.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * The original hash function returns a different value, if arch is x86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * or i386.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static inline unsigned long em28xx_hash_mem(char *buf, int length, int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned long hash = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) unsigned long l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) unsigned char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (len == length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) c = (char)len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) len = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) c = *buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) l = (l << 8) | c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if ((len & (32 / 8 - 1)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) hash = ((hash ^ l) * 0x9e370001UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) } while (len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return (hash >> (32 - bits)) & 0xffffffffUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * Helper function to read data blocks from i2c clients with 8 or 16 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * address width, 8 bit register width and auto incrementation been activated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static int em28xx_i2c_read_block(struct em28xx *dev, unsigned int bus, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) bool addr_w16, u16 len, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int remain = len, rsize, rsize_max, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (addr + remain > (addr_w16 * 0xff00 + 0xff + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Select address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) buf[0] = addr >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) buf[1] = addr & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ret = i2c_master_send(&dev->i2c_client[bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) buf + !addr_w16, 1 + addr_w16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Read data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (dev->board.is_em2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) rsize_max = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) rsize_max = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) while (remain > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (remain > rsize_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) rsize = rsize_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) rsize = remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ret = i2c_master_recv(&dev->i2c_client[bus], data, rsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) remain -= rsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) data += rsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static int em28xx_i2c_eeprom(struct em28xx *dev, unsigned int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u8 **eedata, u16 *eedata_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) const u16 len = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * FIXME common length/size for bytes to read, to display, hash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * calculation and returned device dataset. Simplifies the code a lot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * but we might have to deal with multiple sizes in the future !
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct em28xx_eeprom *dev_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u8 buf, *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) *eedata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) *eedata_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* EEPROM is always on i2c bus 0 on all known devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev->i2c_client[bus].addr = 0xa0 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Check if board has eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) err = i2c_master_recv(&dev->i2c_client[bus], &buf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_info(&dev->intf->dev, "board has no eeprom\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) data = kzalloc(len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* Read EEPROM content */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) err = em28xx_i2c_read_block(dev, bus, 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev->eeprom_addrwidth_16bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) len, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (err != len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev_err(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "failed to read eeprom (err=%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (i2c_debug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Display eeprom content */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) print_hex_dump(KERN_DEBUG, "em28xx eeprom ", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 16, 1, data, len, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (dev->eeprom_addrwidth_16bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "eeprom %06x: ... (skipped)\n", 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (dev->eeprom_addrwidth_16bit &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) data[0] == 0x26 && data[3] == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* new eeprom format; size 4-64kb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u16 mc_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u16 hwconf_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev->hash = em28xx_hash_mem(data, len, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) mc_start = (data[1] << 8) + 4; /* usually 0x0004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "EEPROM ID = %4ph, EEPROM hash = 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) data, dev->hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "EEPROM info:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "\tmicrocode start address = 0x%04x, boot configuration = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) mc_start, data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * boot configuration (address 0x0002):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * [0] microcode download speed: 1 = 400 kHz; 0 = 100 kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * [1] always selects 12 kb RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * [2] USB device speed: 1 = force Full Speed; 0 = auto detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * [4] 1 = force fast mode and no suspend for device testing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * [5:7] USB PHY tuning registers; determined by device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * characterization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * Read hardware config dataset offset from address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * (microcode start + 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) err = em28xx_i2c_read_block(dev, bus, mc_start + 46, 1, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (err != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_err(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) "failed to read hardware configuration data from eeprom (err=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* Calculate hardware config dataset start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) hwconf_offset = mc_start + data[0] + (data[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Read hardware config dataset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * NOTE: the microcode copy can be multiple pages long, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * we assume the hardware config dataset is the same as in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * the old eeprom and not longer than 256 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * tveeprom is currently also limited to 256 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) err = em28xx_i2c_read_block(dev, bus, hwconf_offset, 1, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (err != len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dev_err(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) "failed to read hardware configuration data from eeprom (err=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Verify hardware config dataset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* NOTE: not all devices provide this type of dataset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (data[0] != 0x1a || data[1] != 0xeb ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) data[2] != 0x67 || data[3] != 0x95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "\tno hardware configuration dataset found in eeprom\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * TODO: decrypt eeprom data for camera bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * (em25xx, em276x+)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) } else if (!dev->eeprom_addrwidth_16bit &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) data[0] == 0x1a && data[1] == 0xeb &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) data[2] == 0x67 && data[3] == 0x95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dev->hash = em28xx_hash_mem(data, len, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "EEPROM ID = %4ph, EEPROM hash = 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) data, dev->hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "EEPROM info:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "unknown eeprom format or eeprom corrupted !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) *eedata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) *eedata_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev_config = (void *)*eedata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) switch (le16_to_cpu(dev_config->chip_conf) >> 4 & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev_info(&dev->intf->dev, "\tNo audio on board.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_info(&dev->intf->dev, "\tAC97 audio (5 sample rates)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (dev->chip_id < CHIP_ID_EM2860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "\tI2S audio, sample rate=32k\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "\tI2S audio, 3 sample rates\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (dev->chip_id < CHIP_ID_EM2860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "\tI2S audio, 3 sample rates\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "\tI2S audio, 5 sample rates\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (le16_to_cpu(dev_config->chip_conf) & 1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dev_info(&dev->intf->dev, "\tUSB Remote wakeup capable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (le16_to_cpu(dev_config->chip_conf) & 1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dev_info(&dev->intf->dev, "\tUSB Self power capable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) switch (le16_to_cpu(dev_config->chip_conf) & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dev_info(&dev->intf->dev, "\t500mA max power\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dev_info(&dev->intf->dev, "\t400mA max power\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dev_info(&dev->intf->dev, "\t300mA max power\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dev_info(&dev->intf->dev, "\t200mA max power\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) "\tTable at offset 0x%02x, strings=0x%04x, 0x%04x, 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_config->string_idx_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) le16_to_cpu(dev_config->string1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) le16_to_cpu(dev_config->string2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) le16_to_cpu(dev_config->string3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * functionality()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static u32 functionality(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct em28xx_i2c_bus *i2c_bus = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (i2c_bus->algo_type == EM28XX_I2C_ALGO_EM28XX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) i2c_bus->algo_type == EM28XX_I2C_ALGO_EM25XX_BUS_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) } else if (i2c_bus->algo_type == EM28XX_I2C_ALGO_EM2800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ~I2C_FUNC_SMBUS_WRITE_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) WARN(1, "Unknown i2c bus algorithm.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static const struct i2c_algorithm em28xx_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .master_xfer = em28xx_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .functionality = functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static const struct i2c_adapter em28xx_adap_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .name = "em28xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .algo = &em28xx_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const struct i2c_client em28xx_client_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .name = "em28xx internal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * i2c_devs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * incomplete list of known devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static char *i2c_devs[128] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) [0x1c >> 1] = "lgdt330x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) [0x3e >> 1] = "remote IR sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) [0x4a >> 1] = "saa7113h",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) [0x52 >> 1] = "drxk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) [0x60 >> 1] = "remote IR sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) [0x8e >> 1] = "remote IR sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) [0x86 >> 1] = "tda9887",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) [0x80 >> 1] = "msp34xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) [0x88 >> 1] = "msp34xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) [0xa0 >> 1] = "eeprom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) [0xb0 >> 1] = "tda9874",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) [0xb8 >> 1] = "tvp5150a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) [0xba >> 1] = "webcam sensor or tvp5150a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) [0xc0 >> 1] = "tuner (analog)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) [0xc2 >> 1] = "tuner (analog)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) [0xc4 >> 1] = "tuner (analog)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) [0xc6 >> 1] = "tuner (analog)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * do_i2c_scan()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * check i2c address range for devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) void em28xx_do_i2c_scan(struct em28xx *dev, unsigned int bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) u8 i2c_devicelist[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) unsigned char buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) memset(i2c_devicelist, 0, sizeof(i2c_devicelist));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) for (i = 0; i < ARRAY_SIZE(i2c_devs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) dev->i2c_client[bus].addr = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) rc = i2c_master_recv(&dev->i2c_client[bus], &buf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) i2c_devicelist[i] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) dev_info(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) "found i2c device @ 0x%x on bus %d [%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) i << 1, bus, i2c_devs[i] ? i2c_devs[i] : "???");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (bus == dev->def_i2c_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev->i2c_hash = em28xx_hash_mem(i2c_devicelist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) sizeof(i2c_devicelist), 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * em28xx_i2c_register()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * register i2c bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) int em28xx_i2c_register(struct em28xx *dev, unsigned int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) enum em28xx_i2c_algo_type algo_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (WARN_ON(!dev->em28xx_write_regs || !dev->em28xx_read_reg ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) !dev->em28xx_write_regs_req || !dev->em28xx_read_reg_req))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (bus >= NUM_I2C_BUSES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev->i2c_adap[bus] = em28xx_adap_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) dev->i2c_adap[bus].dev.parent = &dev->intf->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) strscpy(dev->i2c_adap[bus].name, dev_name(&dev->intf->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) sizeof(dev->i2c_adap[bus].name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dev->i2c_bus[bus].bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) dev->i2c_bus[bus].algo_type = algo_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) dev->i2c_bus[bus].dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dev->i2c_adap[bus].algo_data = &dev->i2c_bus[bus];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) retval = i2c_add_adapter(&dev->i2c_adap[bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) dev_err(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "%s: i2c_add_adapter failed! retval [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) __func__, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dev->i2c_client[bus] = em28xx_client_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) dev->i2c_client[bus].adapter = &dev->i2c_adap[bus];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* Up to now, all eeproms are at bus 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (!bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) retval = em28xx_i2c_eeprom(dev, bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) &dev->eedata, &dev->eedata_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (retval < 0 && retval != -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev_err(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) "%s: em28xx_i2_eeprom failed! retval [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) __func__, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (i2c_scan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) em28xx_do_i2c_scan(dev, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * em28xx_i2c_unregister()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * unregister i2c_bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) int em28xx_i2c_unregister(struct em28xx *dev, unsigned int bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (bus >= NUM_I2C_BUSES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) i2c_del_adapter(&dev->i2c_adap[bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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