^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // DVB device driver for em28xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // (c) 2008-2011 Mauro Carvalho Chehab <mchehab@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // (c) 2008 Devin Heitmueller <devin.heitmueller@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // - Fixes for the driver to properly work with HVR-950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // - Fixes for the driver to properly work with Pinnacle PCTV HD Pro Stick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // - Fixes for the driver to properly work with AMD ATI TV Wonder HD 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) // (c) 2008 Aidan Thornton <makosoft@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) // (c) 2012 Frank Schäfer <fschaefer.oss@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) // Based on cx88-dvb, saa7134-dvb and videobuf-dvb originally written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) // (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) // (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) // This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) // it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) // the Free Software Foundation version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "em28xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/dvb_demux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/dvb_net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/dmxdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/tuner.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "tuner-simple.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "lgdt330x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "lgdt3305.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "lgdt3306a.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "zl10353.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "s5h1409.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "mt2060.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "mt352.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "mt352_priv.h" /* FIXME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "tda1002x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "drx39xyj/drx39xxj.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "tda18271.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "s921.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "drxd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include "cxd2820r.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "tda18271c2dd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "drxk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "tda10071.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include "tda18212.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include "a8293.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include "qt1010.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "mb86a20s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include "m88ds3103.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include "ts2020.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include "si2168.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include "si2157.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include "tc90522.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include "qm1d1c0042.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MODULE_DESCRIPTION(DRIVER_DESC " - digital TV interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MODULE_VERSION(EM28XX_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static unsigned int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MODULE_PARM_DESC(debug, "enable debug messages [dvb]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define dprintk(level, fmt, arg...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (debug >= level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dev_printk(KERN_DEBUG, &dev->intf->dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "dvb: " fmt, ## arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct em28xx_dvb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct dvb_frontend *fe[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* feed count management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int nfeeds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* general boilerplate stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct dvb_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct dvb_demux demux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct dmxdev dmxdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct dmx_frontend fe_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct dmx_frontend fe_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct dvb_net net;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Due to DRX-K - probably need changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int (*gate_ctrl)(struct dvb_frontend *fe, int gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct semaphore pll_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bool dont_attach_fe1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int lna_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct i2c_client *i2c_client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct i2c_client *i2c_client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct i2c_client *i2c_client_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void print_err_status(struct em28xx *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int packet, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) char *errmsg = "Unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case -ENOENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) errmsg = "unlinked synchronously";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case -ECONNRESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) errmsg = "unlinked asynchronously";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case -ENOSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) errmsg = "Buffer error (overrun)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case -EPIPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) errmsg = "Stalled (device not responding)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case -EOVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) errmsg = "Babble (bad cable?)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case -EPROTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) errmsg = "Bit-stuff error (bad cable?)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case -EILSEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) errmsg = "CRC/Timeout (could be anything)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case -ETIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) errmsg = "Device does not respond";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (packet < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dprintk(1, "URB status %d [%s].\n", status, errmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dprintk(1, "URB packet %d, status %d [%s].\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) packet, status, errmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static inline int em28xx_dvb_urb_data_copy(struct em28xx *dev, struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int xfer_bulk, num_packets, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (dev->disconnected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (urb->status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) print_err_status(dev, -1, urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) xfer_bulk = usb_pipebulk(urb->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (xfer_bulk) /* bulk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) num_packets = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else /* isoc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) num_packets = urb->number_of_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) for (i = 0; i < num_packets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (xfer_bulk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (urb->status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) print_err_status(dev, i, urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (urb->status != -EPROTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!urb->actual_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dvb_dmx_swfilter(&dev->dvb->demux, urb->transfer_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) urb->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (urb->iso_frame_desc[i].status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) print_err_status(dev, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) urb->iso_frame_desc[i].status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (urb->iso_frame_desc[i].status != -EPROTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!urb->iso_frame_desc[i].actual_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dvb_dmx_swfilter(&dev->dvb->demux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) urb->transfer_buffer +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) urb->iso_frame_desc[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) urb->iso_frame_desc[i].actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int em28xx_start_streaming(struct em28xx_dvb *dvb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct em28xx_i2c_bus *i2c_bus = dvb->adapter.priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct em28xx *dev = i2c_bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct usb_device *udev = interface_to_usbdev(dev->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int dvb_max_packet_size, packet_multiplier, dvb_alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (dev->dvb_xfer_bulk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!dev->dvb_ep_bulk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dvb_max_packet_size = 512; /* USB 2.0 spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) packet_multiplier = EM28XX_DVB_BULK_PACKET_MULTIPLIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dvb_alt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } else { /* isoc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!dev->dvb_ep_isoc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dvb_max_packet_size = dev->dvb_max_pkt_size_isoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (dvb_max_packet_size < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return dvb_max_packet_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) packet_multiplier = EM28XX_DVB_NUM_ISOC_PACKETS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dvb_alt = dev->dvb_alt_isoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!dev->board.has_dual_ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) usb_set_interface(udev, dev->ifnum, dvb_alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rc = em28xx_set_mode(dev, EM28XX_DIGITAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dprintk(1, "Using %d buffers each with %d x %d bytes, alternate %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) EM28XX_DVB_NUM_BUFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) packet_multiplier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dvb_max_packet_size, dvb_alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return em28xx_init_usb_xfer(dev, EM28XX_DIGITAL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev->dvb_xfer_bulk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) EM28XX_DVB_NUM_BUFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dvb_max_packet_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) packet_multiplier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) em28xx_dvb_urb_data_copy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int em28xx_stop_streaming(struct em28xx_dvb *dvb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct em28xx_i2c_bus *i2c_bus = dvb->adapter.priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct em28xx *dev = i2c_bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) em28xx_stop_urbs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int em28xx_start_feed(struct dvb_demux_feed *feed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct dvb_demux *demux = feed->demux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct em28xx_dvb *dvb = demux->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int rc, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!demux->dmx.frontend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mutex_lock(&dvb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dvb->nfeeds++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) rc = dvb->nfeeds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (dvb->nfeeds == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = em28xx_start_streaming(dvb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) rc = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mutex_unlock(&dvb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int em28xx_stop_feed(struct dvb_demux_feed *feed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct dvb_demux *demux = feed->demux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct em28xx_dvb *dvb = demux->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mutex_lock(&dvb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dvb->nfeeds--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!dvb->nfeeds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) err = em28xx_stop_streaming(dvb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mutex_unlock(&dvb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int em28xx_dvb_bus_ctrl(struct dvb_frontend *fe, int acquire)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct em28xx_i2c_bus *i2c_bus = fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct em28xx *dev = i2c_bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (acquire)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return em28xx_set_mode(dev, EM28XX_DIGITAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return em28xx_set_mode(dev, EM28XX_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct lgdt330x_config em2880_lgdt3303_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .demod_chip = LGDT3303,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static struct lgdt3305_config em2870_lgdt3304_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .i2c_addr = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .demod_chip = LGDT3304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .spectral_inversion = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .deny_i2c_rptr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .mpeg_mode = LGDT3305_MPEG_PARALLEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .vsb_if_khz = 3250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .qam_if_khz = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static struct lgdt3305_config em2874_lgdt3305_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .i2c_addr = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .demod_chip = LGDT3305,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .spectral_inversion = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .deny_i2c_rptr = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .mpeg_mode = LGDT3305_MPEG_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .vsb_if_khz = 3250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .qam_if_khz = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct lgdt3305_config em2874_lgdt3305_nogate_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .i2c_addr = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .demod_chip = LGDT3305,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .spectral_inversion = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .deny_i2c_rptr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .mpeg_mode = LGDT3305_MPEG_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .vsb_if_khz = 3600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .qam_if_khz = 3600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct s921_config sharp_isdbt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .demod_address = 0x30 >> 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct zl10353_config em28xx_zl10353_with_xc3028 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .demod_address = (0x1e >> 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .no_tuner = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .parallel_ts = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .if2 = 45600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct s5h1409_config em28xx_s5h1409_with_xc3028 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .demod_address = 0x32 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .output_mode = S5H1409_PARALLEL_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .gpio = S5H1409_GPIO_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .inversion = S5H1409_INVERSION_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .status_mode = S5H1409_DEMODLOCKING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct tda18271_std_map kworld_a340_std_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .if_lvl = 1, .rfagc_top = 0x37, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .if_lvl = 1, .rfagc_top = 0x37, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct tda18271_config kworld_a340_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .std_map = &kworld_a340_std_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static struct tda18271_config kworld_ub435q_v2_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .std_map = &kworld_a340_std_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .gate = TDA18271_GATE_DIGITAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static struct tda18212_config kworld_ub435q_v3_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .if_atsc_vsb = 3600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .if_atsc_qam = 3600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static struct zl10353_config em28xx_zl10353_xc3028_no_i2c_gate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .demod_address = (0x1e >> 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .no_tuner = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .disable_i2c_gate_ctrl = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .parallel_ts = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .if2 = 45600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct drxd_config em28xx_drxd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .demod_address = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .demod_revision = 0xa2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .pll_type = DRXD_PLL_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .clock = 12000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .insert_rs_byte = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .IF = 42800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .disable_i2c_gate_ctrl = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static struct drxk_config terratec_h5_drxk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .adr = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .single_master = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .no_i2c_bridge = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .microcode_name = "dvb-usb-terratec-h5-drxk.fw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .qam_demod_parameter_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct drxk_config hauppauge_930c_drxk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .adr = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .single_master = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .no_i2c_bridge = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .microcode_name = "dvb-usb-hauppauge-hvr930c-drxk.fw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .chunk_size = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .qam_demod_parameter_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static struct drxk_config terratec_htc_stick_drxk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .adr = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .single_master = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .no_i2c_bridge = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .microcode_name = "dvb-usb-terratec-htc-stick-drxk.fw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .chunk_size = 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .qam_demod_parameter_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Required for the antenna_gpio to disable LNA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .antenna_dvbt = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* The windows driver uses the same. This will disable LNA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .antenna_gpio = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static struct drxk_config maxmedia_ub425_tc_drxk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .adr = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .single_master = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .no_i2c_bridge = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .microcode_name = "dvb-demod-drxk-01.fw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .chunk_size = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .qam_demod_parameter_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static struct drxk_config pctv_520e_drxk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .adr = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .single_master = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .microcode_name = "dvb-demod-drxk-pctv.fw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .qam_demod_parameter_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .chunk_size = 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .antenna_dvbt = true, /* disable LNA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .antenna_gpio = (1 << 2), /* disable LNA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct em28xx_dvb *dvb = fe->sec_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!dvb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) down(&dvb->pll_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) status = dvb->gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) status = dvb->gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) up(&dvb->pll_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void hauppauge_hvr930c_init(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const struct em28xx_reg_seq hauppauge_hvr930c_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {EM2874_R80_GPIO_P0_CTRL, 0xff, 0xff, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {EM2874_R80_GPIO_P0_CTRL, 0xfb, 0xff, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {EM2874_R80_GPIO_P0_CTRL, 0xff, 0xff, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { -1, -1, -1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct em28xx_reg_seq hauppauge_hvr930c_end[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {EM2874_R80_GPIO_P0_CTRL, 0xef, 0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {EM2874_R80_GPIO_P0_CTRL, 0xaf, 0xff, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {EM2874_R80_GPIO_P0_CTRL, 0xef, 0xff, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {EM2874_R80_GPIO_P0_CTRL, 0xef, 0xff, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {EM2874_R80_GPIO_P0_CTRL, 0xcf, 0xff, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {EM2874_R80_GPIO_P0_CTRL, 0xef, 0xff, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {EM2874_R80_GPIO_P0_CTRL, 0xcf, 0xff, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {EM2874_R80_GPIO_P0_CTRL, 0xef, 0xff, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {EM2874_R80_GPIO_P0_CTRL, 0xcf, 0xff, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {EM2874_R80_GPIO_P0_CTRL, 0xef, 0xff, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { -1, -1, -1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned char r[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) } regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {{ 0x06, 0x02, 0x00, 0x31 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {{ 0x01, 0x02 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {{ 0x01, 0x02, 0x00, 0xc6 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {{ 0x01, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {{ 0x01, 0x00, 0xff, 0xaf }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {{ 0x01, 0x00, 0x03, 0xa0 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {{ 0x01, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {{ 0x01, 0x00, 0x73, 0xaf }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {{ 0x04, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {{ 0x00, 0x04 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {{ 0x00, 0x04, 0x00, 0x0a }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {{ 0x04, 0x14 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {{ 0x04, 0x14, 0x00, 0x00 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) em28xx_gpio_set(dev, hauppauge_hvr930c_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev->i2c_client[dev->def_i2c_bus].addr = 0x82 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) for (i = 0; i < ARRAY_SIZE(regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) i2c_master_send(&dev->i2c_client[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) regs[i].r, regs[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) em28xx_gpio_set(dev, hauppauge_hvr930c_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void terratec_h5_init(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const struct em28xx_reg_seq terratec_h5_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {EM2820_R08_GPIO_CTRL, 0xff, 0xff, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {EM2874_R80_GPIO_P0_CTRL, 0xf6, 0xff, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {EM2874_R80_GPIO_P0_CTRL, 0xf2, 0xff, 50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {EM2874_R80_GPIO_P0_CTRL, 0xf6, 0xff, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { -1, -1, -1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const struct em28xx_reg_seq terratec_h5_end[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {EM2874_R80_GPIO_P0_CTRL, 0xe6, 0xff, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {EM2874_R80_GPIO_P0_CTRL, 0xa6, 0xff, 50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {EM2874_R80_GPIO_P0_CTRL, 0xe6, 0xff, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { -1, -1, -1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned char r[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) } regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {{ 0x06, 0x02, 0x00, 0x31 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {{ 0x01, 0x02 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {{ 0x01, 0x02, 0x00, 0xc6 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {{ 0x01, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {{ 0x01, 0x00, 0xff, 0xaf }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {{ 0x01, 0x00, 0x03, 0xa0 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {{ 0x01, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {{ 0x01, 0x00, 0x73, 0xaf }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {{ 0x04, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {{ 0x00, 0x04 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {{ 0x00, 0x04, 0x00, 0x0a }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {{ 0x04, 0x14 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {{ 0x04, 0x14, 0x00, 0x00 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) em28xx_gpio_set(dev, terratec_h5_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev->i2c_client[dev->def_i2c_bus].addr = 0x82 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) for (i = 0; i < ARRAY_SIZE(regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) i2c_master_send(&dev->i2c_client[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) regs[i].r, regs[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) em28xx_gpio_set(dev, terratec_h5_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void terratec_htc_stick_init(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * GPIO configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * 0xff: unknown (does not affect DVB-T).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * 0xf6: DRX-K (demodulator).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * 0xe6: unknown (does not affect DVB-T).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * 0xb6: unknown (does not affect DVB-T).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const struct em28xx_reg_seq terratec_htc_stick_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {EM2820_R08_GPIO_CTRL, 0xff, 0xff, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {EM2874_R80_GPIO_P0_CTRL, 0xf6, 0xff, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {EM2874_R80_GPIO_P0_CTRL, 0xe6, 0xff, 50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {EM2874_R80_GPIO_P0_CTRL, 0xf6, 0xff, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { -1, -1, -1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static const struct em28xx_reg_seq terratec_htc_stick_end[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {EM2874_R80_GPIO_P0_CTRL, 0xb6, 0xff, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {EM2874_R80_GPIO_P0_CTRL, 0xf6, 0xff, 50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { -1, -1, -1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * Init the analog decoder (not yet supported), but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * it's probably still a good idea.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) unsigned char r[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) } regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {{ 0x06, 0x02, 0x00, 0x31 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {{ 0x01, 0x02 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {{ 0x01, 0x02, 0x00, 0xc6 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {{ 0x01, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {{ 0x01, 0x00, 0xff, 0xaf }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) em28xx_gpio_set(dev, terratec_htc_stick_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev->i2c_client[dev->def_i2c_bus].addr = 0x82 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) for (i = 0; i < ARRAY_SIZE(regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) i2c_master_send(&dev->i2c_client[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) regs[i].r, regs[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) em28xx_gpio_set(dev, terratec_htc_stick_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void terratec_htc_usb_xs_init(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const struct em28xx_reg_seq terratec_htc_usb_xs_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {EM2820_R08_GPIO_CTRL, 0xff, 0xff, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {EM2874_R80_GPIO_P0_CTRL, 0xb2, 0xff, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {EM2874_R80_GPIO_P0_CTRL, 0xb2, 0xff, 50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {EM2874_R80_GPIO_P0_CTRL, 0xb6, 0xff, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { -1, -1, -1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const struct em28xx_reg_seq terratec_htc_usb_xs_end[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {EM2874_R80_GPIO_P0_CTRL, 0xa6, 0xff, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {EM2874_R80_GPIO_P0_CTRL, 0xa6, 0xff, 50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {EM2874_R80_GPIO_P0_CTRL, 0xe6, 0xff, 100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { -1, -1, -1, -1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * Init the analog decoder (not yet supported), but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * it's probably still a good idea.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned char r[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) } regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {{ 0x06, 0x02, 0x00, 0x31 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {{ 0x01, 0x02 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {{ 0x01, 0x02, 0x00, 0xc6 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {{ 0x01, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {{ 0x01, 0x00, 0xff, 0xaf }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {{ 0x01, 0x00, 0x03, 0xa0 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {{ 0x01, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {{ 0x01, 0x00, 0x73, 0xaf }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {{ 0x04, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {{ 0x00, 0x04 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {{ 0x00, 0x04, 0x00, 0x0a }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {{ 0x04, 0x14 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {{ 0x04, 0x14, 0x00, 0x00 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) em28xx_gpio_set(dev, terratec_htc_usb_xs_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dev->i2c_client[dev->def_i2c_bus].addr = 0x82 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) for (i = 0; i < ARRAY_SIZE(regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) i2c_master_send(&dev->i2c_client[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) regs[i].r, regs[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) em28xx_gpio_set(dev, terratec_htc_usb_xs_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static void pctv_520e_init(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * Init AVF4910B analog decoder. Looks like I2C traffic to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * digital demodulator and tuner are routed via AVF4910B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) unsigned char r[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) } regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {{ 0x06, 0x02, 0x00, 0x31 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {{ 0x01, 0x02 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {{ 0x01, 0x02, 0x00, 0xc6 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {{ 0x01, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {{ 0x01, 0x00, 0xff, 0xaf }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {{ 0x01, 0x00, 0x03, 0xa0 }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {{ 0x01, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {{ 0x01, 0x00, 0x73, 0xaf }, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev->i2c_client[dev->def_i2c_bus].addr = 0x82 >> 1; /* 0x41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) for (i = 0; i < ARRAY_SIZE(regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) i2c_master_send(&dev->i2c_client[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) regs[i].r, regs[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static int em28xx_pctv_290e_set_lna(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct em28xx_i2c_bus *i2c_bus = fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct em28xx *dev = i2c_bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct em28xx_dvb *dvb = dev->dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (c->lna == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) flags = GPIOF_OUT_INIT_HIGH; /* enable LNA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) flags = GPIOF_OUT_INIT_LOW; /* disable LNA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ret = gpio_request_one(dvb->lna_gpio, flags, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_err(&dev->intf->dev, "gpio request failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) gpio_free(dvb->lna_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev_warn(&dev->intf->dev, "%s: LNA control is disabled (lna=%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) KBUILD_MODNAME, c->lna);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static int em28xx_pctv_292e_set_lna(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct em28xx_i2c_bus *i2c_bus = fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct em28xx *dev = i2c_bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u8 lna;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (c->lna == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) lna = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) lna = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return em28xx_write_reg_bits(dev, EM2874_R80_GPIO_P0_CTRL, lna, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int em28xx_mt352_terratec_xs_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Values extracted from a USB trace of the Terratec Windows driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static u8 clock_config[] = { CLOCK_CTL, 0x38, 0x2c };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static u8 reset[] = { RESET, 0x80 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static u8 adc_ctl_1_cfg[] = { ADC_CTL_1, 0x40 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static u8 agc_cfg[] = { AGC_TARGET, 0x28, 0xa0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static u8 input_freq_cfg[] = { INPUT_FREQ_1, 0x31, 0xb8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static u8 rs_err_cfg[] = { RS_ERR_PER_1, 0x00, 0x4d };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static u8 trl_nom_cfg[] = { TRL_NOMINAL_RATE_1, 0x64, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static u8 tps_given_cfg[] = { TPS_GIVEN_1, 0x40, 0x80, 0x50 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static u8 tuner_go[] = { TUNER_GO, 0x01};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) mt352_write(fe, clock_config, sizeof(clock_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) usleep_range(200, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) mt352_write(fe, reset, sizeof(reset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) mt352_write(fe, agc_cfg, sizeof(agc_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) mt352_write(fe, input_freq_cfg, sizeof(input_freq_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mt352_write(fe, rs_err_cfg, sizeof(rs_err_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) mt352_write(fe, trl_nom_cfg, sizeof(trl_nom_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) mt352_write(fe, tps_given_cfg, sizeof(tps_given_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mt352_write(fe, tuner_go, sizeof(tuner_go));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static void px_bcud_init(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) unsigned char r[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) } regs1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {{ 0x0e, 0x77 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {{ 0x0f, 0x77 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {{ 0x03, 0x90 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }, regs2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {{ 0x07, 0x01 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {{ 0x08, 0x10 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {{ 0x13, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {{ 0x17, 0x00 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {{ 0x03, 0x01 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {{ 0x10, 0xb1 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {{ 0x11, 0x40 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {{ 0x85, 0x7a }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {{ 0x87, 0x04 }, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static const struct em28xx_reg_seq gpio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {EM28XX_R06_I2C_CLK, 0x40, 0xff, 300},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {EM2874_R80_GPIO_P0_CTRL, 0xfd, 0xff, 60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {EM28XX_R15_RGAIN, 0x20, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {EM28XX_R16_GGAIN, 0x20, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {EM28XX_R17_BGAIN, 0x20, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {EM28XX_R18_ROFFSET, 0x00, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {EM28XX_R19_GOFFSET, 0x00, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {EM28XX_R1A_BOFFSET, 0x00, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {EM28XX_R23_UOFFSET, 0x00, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {EM28XX_R24_VOFFSET, 0x00, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {EM28XX_R26_COMPR, 0x00, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {0x13, 0x08, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {EM28XX_R12_VINENABLE, 0x27, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {EM28XX_R0C_USBSUSP, 0x10, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {EM28XX_R27_OUTFMT, 0x00, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {EM28XX_R10_VINMODE, 0x00, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {EM28XX_R11_VINCTRL, 0x11, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {EM2874_R50_IR_CONFIG, 0x01, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {EM2874_R5F_TS_ENABLE, 0x80, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {EM28XX_R06_I2C_CLK, 0x46, 0xff, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* sleeping ISDB-T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dev->dvb->i2c_client_demod->addr = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) for (i = 0; i < ARRAY_SIZE(regs1); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) i2c_master_send(dev->dvb->i2c_client_demod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) regs1[i].r, regs1[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* sleeping ISDB-S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dev->dvb->i2c_client_demod->addr = 0x15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) for (i = 0; i < ARRAY_SIZE(regs2); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) i2c_master_send(dev->dvb->i2c_client_demod, regs2[i].r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) regs2[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) for (i = 0; i < ARRAY_SIZE(gpio); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) em28xx_write_reg_bits(dev, gpio[i].reg, gpio[i].val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) gpio[i].mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (gpio[i].sleep > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) msleep(gpio[i].sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static struct mt352_config terratec_xs_mt352_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .demod_address = (0x1e >> 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .no_tuner = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .if2 = 45600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .demod_init = em28xx_mt352_terratec_xs_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static struct tda10023_config em28xx_tda10023_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .demod_address = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .invert = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static struct cxd2820r_config em28xx_cxd2820r_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .i2c_address = (0xd8 >> 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .ts_mode = CXD2820R_TS_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static struct tda18271_config em28xx_cxd2820r_tda18271_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .output_opt = TDA18271_OUTPUT_LT_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .gate = TDA18271_GATE_DIGITAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static struct zl10353_config em28xx_zl10353_no_i2c_gate_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .demod_address = (0x1e >> 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .disable_i2c_gate_ctrl = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .no_tuner = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .parallel_ts = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static struct mt2060_config em28xx_mt2060_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .i2c_address = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static struct qt1010_config em28xx_qt1010_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .i2c_address = 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const struct mb86a20s_config c3tech_duo_mb86a20s_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .demod_address = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .is_serial = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static struct tda18271_std_map mb86a20s_tda18271_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .dvbt_6 = { .if_freq = 4000, .agc_mode = 3, .std = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .if_lvl = 1, .rfagc_top = 0x37, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static struct tda18271_config c3tech_duo_tda18271_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .std_map = &mb86a20s_tda18271_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .gate = TDA18271_GATE_DIGITAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .small_i2c = TDA18271_03_BYTE_CHUNK_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static struct tda18271_std_map drx_j_std_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .atsc_6 = { .if_freq = 5000, .agc_mode = 3, .std = 0, .if_lvl = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .rfagc_top = 0x37, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .qam_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, .if_lvl = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .rfagc_top = 0x37, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static struct tda18271_config pinnacle_80e_dvb_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .std_map = &drx_j_std_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .gate = TDA18271_GATE_DIGITAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .role = TDA18271_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static struct lgdt3306a_config hauppauge_01595_lgdt3306a_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .qam_if_khz = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .vsb_if_khz = 3250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .spectral_inversion = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .deny_i2c_rptr = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .mpeg_mode = LGDT3306A_MPEG_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .tpclk_edge = LGDT3306A_TPCLK_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .tpvalid_polarity = LGDT3306A_TP_VALID_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .xtalMHz = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static noinline_for_stack int em28xx_attach_xc3028(u8 addr, struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct xc2028_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct xc2028_ctrl ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) cfg.i2c_adap = &dev->i2c_adap[dev->def_i2c_bus];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) cfg.i2c_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) memset(&ctl, 0, sizeof(ctl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) em28xx_setup_xc3028(dev, &ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) cfg.ctrl = &ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (!dev->dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) dev_err(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) "dvb frontend not attached. Can't attach xc3028\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) fe = dvb_attach(xc2028_attach, dev->dvb->fe[0], &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (!fe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dev_err(&dev->intf->dev, "xc3028 attach failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dvb_frontend_detach(dev->dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) dev->dvb->fe[0] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dev_info(&dev->intf->dev, "xc3028 attached\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static int em28xx_register_dvb(struct em28xx_dvb *dvb, struct module *module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct em28xx *dev, struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) bool create_rf_connector = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) mutex_init(&dvb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /* register adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) result = dvb_register_adapter(&dvb->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev_name(&dev->intf->dev), module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) device, adapter_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) "dvb_register_adapter failed (errno = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) goto fail_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #ifdef CONFIG_MEDIA_CONTROLLER_DVB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dvb->adapter.mdev = dev->media_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Ensure all frontends negotiate bus access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dvb->fe[0]->ops.ts_bus_ctrl = em28xx_dvb_bus_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (dvb->fe[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) dvb->fe[1]->ops.ts_bus_ctrl = em28xx_dvb_bus_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dvb->adapter.priv = &dev->i2c_bus[dev->def_i2c_bus];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* register frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) result = dvb_register_frontend(&dvb->adapter, dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) "dvb_register_frontend failed (errno = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) goto fail_frontend0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* register 2nd frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (dvb->fe[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) result = dvb_register_frontend(&dvb->adapter, dvb->fe[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) "2nd dvb_register_frontend failed (errno = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) goto fail_frontend1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* register demux stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dvb->demux.dmx.capabilities =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) DMX_TS_FILTERING | DMX_SECTION_FILTERING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) DMX_MEMORY_BASED_FILTERING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dvb->demux.priv = dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) dvb->demux.filternum = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) dvb->demux.feednum = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dvb->demux.start_feed = em28xx_start_feed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) dvb->demux.stop_feed = em28xx_stop_feed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) result = dvb_dmx_init(&dvb->demux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) "dvb_dmx_init failed (errno = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) goto fail_dmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) dvb->dmxdev.filternum = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dvb->dmxdev.demux = &dvb->demux.dmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dvb->dmxdev.capabilities = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) result = dvb_dmxdev_init(&dvb->dmxdev, &dvb->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) "dvb_dmxdev_init failed (errno = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) goto fail_dmxdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dvb->fe_hw.source = DMX_FRONTEND_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) result = dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->fe_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) "add_frontend failed (DMX_FRONTEND_0, errno = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) goto fail_fe_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dvb->fe_mem.source = DMX_MEMORY_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) result = dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->fe_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) "add_frontend failed (DMX_MEMORY_FE, errno = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto fail_fe_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) result = dvb->demux.dmx.connect_frontend(&dvb->demux.dmx, &dvb->fe_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) dev_warn(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "connect_frontend failed (errno = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) goto fail_fe_conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* register network adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dvb_net_init(&dvb->adapter, &dvb->net, &dvb->demux.dmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* If the analog part won't create RF connectors, DVB will do it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (!dev->has_video || dev->tuner_type == TUNER_ABSENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) create_rf_connector = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) result = dvb_create_media_graph(&dvb->adapter, create_rf_connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) goto fail_create_graph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) fail_create_graph:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) dvb_net_release(&dvb->net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) fail_fe_conn:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) fail_fe_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) fail_fe_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) dvb_dmxdev_release(&dvb->dmxdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) fail_dmxdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) dvb_dmx_release(&dvb->demux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) fail_dmx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (dvb->fe[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) dvb_unregister_frontend(dvb->fe[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) dvb_unregister_frontend(dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) fail_frontend1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (dvb->fe[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) dvb_frontend_detach(dvb->fe[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) fail_frontend0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dvb_frontend_detach(dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) dvb_unregister_adapter(&dvb->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) fail_adapter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static void em28xx_unregister_dvb(struct em28xx_dvb *dvb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) dvb_net_release(&dvb->net);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dvb_dmxdev_release(&dvb->dmxdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) dvb_dmx_release(&dvb->demux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (dvb->fe[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dvb_unregister_frontend(dvb->fe[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) dvb_unregister_frontend(dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (dvb->fe[1] && !dvb->dont_attach_fe1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) dvb_frontend_detach(dvb->fe[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dvb_frontend_detach(dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dvb_unregister_adapter(&dvb->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static int em28174_dvb_init_pctv_460e(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct em28xx_dvb *dvb = dev->dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct tda10071_platform_data tda10071_pdata = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct a8293_platform_data a8293_pdata = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* attach demod + tuner combo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) tda10071_pdata.clk = 40444000; /* 40.444 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) tda10071_pdata.i2c_wr_max = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) tda10071_pdata.ts_mode = TDA10071_TS_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) tda10071_pdata.pll_multiplier = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) tda10071_pdata.tuner_i2c_addr = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) dvb->i2c_client_demod = dvb_module_probe("tda10071", "tda10071_cx24118",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) 0x55, &tda10071_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (!dvb->i2c_client_demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dvb->fe[0] = tda10071_pdata.get_dvb_frontend(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* attach SEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) a8293_pdata.dvb_frontend = dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dvb->i2c_client_sec = dvb_module_probe("a8293", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) 0x08, &a8293_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (!dvb->i2c_client_sec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dvb_module_release(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static int em28178_dvb_init_pctv_461e(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct em28xx_dvb *dvb = dev->dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct i2c_adapter *i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct m88ds3103_platform_data m88ds3103_pdata = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct ts2020_config ts2020_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct a8293_platform_data a8293_pdata = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* attach demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) m88ds3103_pdata.clk = 27000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) m88ds3103_pdata.i2c_wr_max = 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) m88ds3103_pdata.ts_mode = M88DS3103_TS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) m88ds3103_pdata.ts_clk = 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) m88ds3103_pdata.ts_clk_pol = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) m88ds3103_pdata.agc = 0x99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) dvb->i2c_client_demod = dvb_module_probe("m88ds3103", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) 0x68, &m88ds3103_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (!dvb->i2c_client_demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dvb->fe[0] = m88ds3103_pdata.get_dvb_frontend(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) i2c_adapter = m88ds3103_pdata.get_i2c_adapter(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ts2020_config.fe = dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) dvb->i2c_client_tuner = dvb_module_probe("ts2020", "ts2022",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) i2c_adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) 0x60, &ts2020_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (!dvb->i2c_client_tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dvb_module_release(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* delegate signal strength measurement to tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dvb->fe[0]->ops.read_signal_strength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) dvb->fe[0]->ops.tuner_ops.get_rf_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* attach SEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) a8293_pdata.dvb_frontend = dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) dvb->i2c_client_sec = dvb_module_probe("a8293", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) 0x08, &a8293_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (!dvb->i2c_client_sec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dvb_module_release(dvb->i2c_client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) dvb_module_release(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static int em28178_dvb_init_pctv_461e_v2(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct em28xx_dvb *dvb = dev->dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct i2c_adapter *i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct m88ds3103_platform_data m88ds3103_pdata = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct ts2020_config ts2020_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct a8293_platform_data a8293_pdata = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* attach demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) m88ds3103_pdata.clk = 27000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) m88ds3103_pdata.i2c_wr_max = 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) m88ds3103_pdata.ts_mode = M88DS3103_TS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) m88ds3103_pdata.ts_clk = 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) m88ds3103_pdata.ts_clk_pol = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) m88ds3103_pdata.agc = 0x99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) m88ds3103_pdata.agc_inv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) m88ds3103_pdata.spec_inv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) dvb->i2c_client_demod = dvb_module_probe("m88ds3103", "m88ds3103b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) 0x6a, &m88ds3103_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (!dvb->i2c_client_demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) dvb->fe[0] = m88ds3103_pdata.get_dvb_frontend(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) i2c_adapter = m88ds3103_pdata.get_i2c_adapter(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ts2020_config.fe = dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) dvb->i2c_client_tuner = dvb_module_probe("ts2020", "ts2022",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) i2c_adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) 0x60, &ts2020_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (!dvb->i2c_client_tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) dvb_module_release(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* delegate signal strength measurement to tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dvb->fe[0]->ops.read_signal_strength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) dvb->fe[0]->ops.tuner_ops.get_rf_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* attach SEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) a8293_pdata.dvb_frontend = dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) dvb->i2c_client_sec = dvb_module_probe("a8293", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) 0x08, &a8293_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (!dvb->i2c_client_sec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dvb_module_release(dvb->i2c_client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) dvb_module_release(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static int em28178_dvb_init_pctv_292e(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct em28xx_dvb *dvb = dev->dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct i2c_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct si2168_config si2168_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct si2157_config si2157_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* attach demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) si2168_config.i2c_adapter = &adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) si2168_config.fe = &dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) si2168_config.ts_mode = SI2168_TS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) si2168_config.spectral_inversion = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dvb->i2c_client_demod = dvb_module_probe("si2168", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) 0x64, &si2168_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (!dvb->i2c_client_demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) si2157_config.fe = dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) si2157_config.if_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #ifdef CONFIG_MEDIA_CONTROLLER_DVB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) si2157_config.mdev = dev->media_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dvb->i2c_client_tuner = dvb_module_probe("si2157", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) 0x60, &si2157_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (!dvb->i2c_client_tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) dvb_module_release(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) dvb->fe[0]->ops.set_lna = em28xx_pctv_292e_set_lna;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static int em28178_dvb_init_terratec_t2_stick_hd(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct em28xx_dvb *dvb = dev->dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct i2c_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct si2168_config si2168_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct si2157_config si2157_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* attach demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) si2168_config.i2c_adapter = &adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) si2168_config.fe = &dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) si2168_config.ts_mode = SI2168_TS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) dvb->i2c_client_demod = dvb_module_probe("si2168", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) 0x64, &si2168_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (!dvb->i2c_client_demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) memset(&si2157_config, 0, sizeof(si2157_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) si2157_config.fe = dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) si2157_config.if_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #ifdef CONFIG_MEDIA_CONTROLLER_DVB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) si2157_config.mdev = dev->media_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) dvb->i2c_client_tuner = dvb_module_probe("si2157", "si2146",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) 0x60, &si2157_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (!dvb->i2c_client_tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) dvb_module_release(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static int em28178_dvb_init_plex_px_bcud(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct em28xx_dvb *dvb = dev->dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct tc90522_config tc90522_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct qm1d1c0042_config qm1d1c0042_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* attach demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) dvb->i2c_client_demod = dvb_module_probe("tc90522", "tc90522sat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) 0x15, &tc90522_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (!dvb->i2c_client_demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) qm1d1c0042_config.fe = tc90522_config.fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) qm1d1c0042_config.lpf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) dvb->i2c_client_tuner = dvb_module_probe("qm1d1c0042", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) tc90522_config.tuner_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) 0x61, &qm1d1c0042_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (!dvb->i2c_client_tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) dvb_module_release(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) dvb->fe[0] = tc90522_config.fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) px_bcud_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static int em28174_dvb_init_hauppauge_wintv_dualhd_dvb(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) struct em28xx_dvb *dvb = dev->dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) struct i2c_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct si2168_config si2168_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) struct si2157_config si2157_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) unsigned char addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* attach demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) si2168_config.i2c_adapter = &adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) si2168_config.fe = &dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) si2168_config.ts_mode = SI2168_TS_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) si2168_config.spectral_inversion = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) addr = (dev->ts == PRIMARY_TS) ? 0x64 : 0x67;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) dvb->i2c_client_demod = dvb_module_probe("si2168", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) addr, &si2168_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (!dvb->i2c_client_demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) memset(&si2157_config, 0, sizeof(si2157_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) si2157_config.fe = dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) si2157_config.if_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #ifdef CONFIG_MEDIA_CONTROLLER_DVB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) si2157_config.mdev = dev->media_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) addr = (dev->ts == PRIMARY_TS) ? 0x60 : 0x63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) dvb->i2c_client_tuner = dvb_module_probe("si2157", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) addr, &si2157_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (!dvb->i2c_client_tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) dvb_module_release(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static int em28174_dvb_init_hauppauge_wintv_dualhd_01595(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) struct em28xx_dvb *dvb = dev->dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) struct i2c_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) struct lgdt3306a_config lgdt3306a_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) struct si2157_config si2157_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) unsigned char addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* attach demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) lgdt3306a_config = hauppauge_01595_lgdt3306a_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) lgdt3306a_config.fe = &dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) lgdt3306a_config.i2c_adapter = &adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) addr = (dev->ts == PRIMARY_TS) ? 0x59 : 0x0e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) dvb->i2c_client_demod = dvb_module_probe("lgdt3306a", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) addr, &lgdt3306a_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (!dvb->i2c_client_demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) si2157_config.fe = dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) si2157_config.if_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) si2157_config.inversion = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #ifdef CONFIG_MEDIA_CONTROLLER_DVB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) si2157_config.mdev = dev->media_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) addr = (dev->ts == PRIMARY_TS) ? 0x60 : 0x62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) dvb->i2c_client_tuner = dvb_module_probe("si2157", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) addr, &si2157_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (!dvb->i2c_client_tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dvb_module_release(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static int em28xx_dvb_init(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) int result = 0, dvb_alt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct em28xx_dvb *dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (dev->is_audio_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /* Shouldn't initialize IR for this interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (!dev->board.has_dvb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* This device does not support the extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) dev_info(&dev->intf->dev, "Binding DVB extension\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) dvb = kzalloc(sizeof(*dvb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (!dvb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) dev->dvb = dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) dvb->fe[0] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) dvb->fe[1] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* pre-allocate DVB usb transfer buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (dev->dvb_xfer_bulk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) result = em28xx_alloc_urbs(dev, EM28XX_DIGITAL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) dev->dvb_xfer_bulk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) EM28XX_DVB_NUM_BUFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) EM28XX_DVB_BULK_PACKET_MULTIPLIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) result = em28xx_alloc_urbs(dev, EM28XX_DIGITAL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) dev->dvb_xfer_bulk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) EM28XX_DVB_NUM_BUFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) dev->dvb_max_pkt_size_isoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) EM28XX_DVB_NUM_ISOC_PACKETS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) dev_err(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) "failed to pre-allocate USB transfer buffers for DVB.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) kfree(dvb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) dev->dvb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) mutex_lock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) em28xx_set_mode(dev, EM28XX_DIGITAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* init frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) switch (dev->model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) case EM2874_BOARD_LEADERSHIP_ISDBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) dvb->fe[0] = dvb_attach(s921_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) &sharp_isdbt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (!dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_850:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) case EM2880_BOARD_PINNACLE_PCTV_HD_PRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) case EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) dvb->fe[0] = dvb_attach(lgdt330x_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) &em2880_lgdt3303_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (em28xx_attach_xc3028(0x61, dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) case EM2880_BOARD_KWORLD_DVB_310U:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) dvb->fe[0] = dvb_attach(zl10353_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) &em28xx_zl10353_with_xc3028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (em28xx_attach_xc3028(0x61, dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) case EM2882_BOARD_TERRATEC_HYBRID_XS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) case EM2880_BOARD_EMPIRE_DUAL_TV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) case EM2882_BOARD_ZOLID_HYBRID_TV_STICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) dvb->fe[0] = dvb_attach(zl10353_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) &em28xx_zl10353_xc3028_no_i2c_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (em28xx_attach_xc3028(0x61, dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) case EM2880_BOARD_TERRATEC_HYBRID_XS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) case EM2880_BOARD_TERRATEC_HYBRID_XS_FR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) case EM2881_BOARD_PINNACLE_HYBRID_PRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) case EM2882_BOARD_DIKOM_DK300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) case EM2882_BOARD_KWORLD_VS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * Those boards could have either a zl10353 or a mt352.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * If the chip id isn't for zl10353, try mt352.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) dvb->fe[0] = dvb_attach(zl10353_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) &em28xx_zl10353_xc3028_no_i2c_gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (!dvb->fe[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) dvb->fe[0] = dvb_attach(mt352_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) &terratec_xs_mt352_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (em28xx_attach_xc3028(0x61, dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) case EM2870_BOARD_TERRATEC_XS_MT2060:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) dvb->fe[0] = dvb_attach(zl10353_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) &em28xx_zl10353_no_i2c_gate_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) dvb_attach(mt2060_attach, dvb->fe[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) &em28xx_mt2060_config, 1220);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) case EM2870_BOARD_KWORLD_355U:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) dvb->fe[0] = dvb_attach(zl10353_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) &em28xx_zl10353_no_i2c_gate_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (dvb->fe[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dvb_attach(qt1010_attach, dvb->fe[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) &em28xx_qt1010_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) case EM2883_BOARD_KWORLD_HYBRID_330U:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) case EM2882_BOARD_EVGA_INDTUBE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) dvb->fe[0] = dvb_attach(s5h1409_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) &em28xx_s5h1409_with_xc3028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (em28xx_attach_xc3028(0x61, dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) case EM2882_BOARD_KWORLD_ATSC_315U:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) dvb->fe[0] = dvb_attach(lgdt330x_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) &em2880_lgdt3303_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (!dvb_attach(simple_tuner_attach, dvb->fe[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) 0x61, TUNER_THOMSON_DTT761X)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) case EM2882_BOARD_PINNACLE_HYBRID_PRO_330E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) dvb->fe[0] = dvb_attach(drxd_attach, &em28xx_drxd, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) &dev->intf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (em28xx_attach_xc3028(0x61, dev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) case EM2870_BOARD_REDDO_DVB_C_USB_BOX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* Philips CU1216L NIM (Philips TDA10023 + Infineon TUA6034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) dvb->fe[0] = dvb_attach(tda10023_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) &em28xx_tda10023_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (!dvb_attach(simple_tuner_attach, dvb->fe[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) 0x60, TUNER_PHILIPS_CU1216L)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) case EM2870_BOARD_KWORLD_A340:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) dvb->fe[0] = dvb_attach(lgdt3305_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) &em2870_lgdt3304_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (!dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (!dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) &kworld_a340_config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) dvb_frontend_detach(dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) case EM28174_BOARD_PCTV_290E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /* set default GPIO0 for LNA, used if GPIOLIB is undefined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) dvb->lna_gpio = CXD2820R_GPIO_E | CXD2820R_GPIO_O |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) CXD2820R_GPIO_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) dvb->fe[0] = dvb_attach(cxd2820r_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) &em28xx_cxd2820r_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) &dvb->lna_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) if (dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* FE 0 attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (!dvb_attach(tda18271_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) dvb->fe[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) &em28xx_cxd2820r_tda18271_config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) dvb_frontend_detach(dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) /* enable LNA for DVB-T, DVB-T2 and DVB-C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) result = gpio_request_one(dvb->lna_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) GPIOF_OUT_INIT_LOW, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) dev_err(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) "gpio request failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) gpio_free(dvb->lna_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) result = 0; /* continue even set LNA fails */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) dvb->fe[0]->ops.set_lna = em28xx_pctv_290e_set_lna;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) case EM2884_BOARD_HAUPPAUGE_WINTV_HVR_930C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct xc5000_config cfg = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) hauppauge_hvr930c_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) dvb->fe[0] = dvb_attach(drxk_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) &hauppauge_930c_drxk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (!dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* FIXME: do we need a pll semaphore? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) dvb->fe[0]->sec_priv = dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) sema_init(&dvb->pll_mutex, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) dvb->gate_ctrl = dvb->fe[0]->ops.i2c_gate_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) dvb->fe[0]->ops.i2c_gate_ctrl = drxk_gate_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* Attach xc5000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) cfg.i2c_address = 0x61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) cfg.if_khz = 4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (dvb->fe[0]->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) dvb->fe[0]->ops.i2c_gate_ctrl(dvb->fe[0], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (!dvb_attach(xc5000_attach, dvb->fe[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) &dev->i2c_adap[dev->def_i2c_bus], &cfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (dvb->fe[0]->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) dvb->fe[0]->ops.i2c_gate_ctrl(dvb->fe[0], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) case EM2884_BOARD_TERRATEC_H5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) terratec_h5_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) dvb->fe[0] = dvb_attach(drxk_attach, &terratec_h5_drxk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if (!dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /* FIXME: do we need a pll semaphore? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) dvb->fe[0]->sec_priv = dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) sema_init(&dvb->pll_mutex, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) dvb->gate_ctrl = dvb->fe[0]->ops.i2c_gate_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) dvb->fe[0]->ops.i2c_gate_ctrl = drxk_gate_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /* Attach tda18271 to DVB-C frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if (dvb->fe[0]->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) dvb->fe[0]->ops.i2c_gate_ctrl(dvb->fe[0], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (!dvb_attach(tda18271c2dd_attach, dvb->fe[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) &dev->i2c_adap[dev->def_i2c_bus], 0x60)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (dvb->fe[0]->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) dvb->fe[0]->ops.i2c_gate_ctrl(dvb->fe[0], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) case EM2884_BOARD_C3TECH_DIGITAL_DUO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) dvb->fe[0] = dvb_attach(mb86a20s_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) &c3tech_duo_mb86a20s_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (dvb->fe[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) &c3tech_duo_tda18271_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) case EM28174_BOARD_PCTV_460E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) result = em28174_dvb_init_pctv_460e(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) case EM2874_BOARD_DELOCK_61959:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) case EM2874_BOARD_MAXMEDIA_UB425_TC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /* attach demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) dvb->fe[0] = dvb_attach(drxk_attach, &maxmedia_ub425_tc_drxk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) /* disable I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) dvb->fe[0]->ops.i2c_gate_ctrl = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if (!dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) &em28xx_cxd2820r_tda18271_config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) dvb_frontend_detach(dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) case EM2884_BOARD_PCTV_510E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) case EM2884_BOARD_PCTV_520E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) pctv_520e_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) /* attach demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) dvb->fe[0] = dvb_attach(drxk_attach, &pctv_520e_drxk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (!dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) &em28xx_cxd2820r_tda18271_config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) dvb_frontend_detach(dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) case EM2884_BOARD_ELGATO_EYETV_HYBRID_2008:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) case EM2884_BOARD_CINERGY_HTC_STICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) case EM2884_BOARD_TERRATEC_H6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) terratec_htc_stick_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) /* attach demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) dvb->fe[0] = dvb_attach(drxk_attach, &terratec_htc_stick_drxk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (!dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) /* Attach the demodulator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) if (!dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) &em28xx_cxd2820r_tda18271_config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) case EM2884_BOARD_TERRATEC_HTC_USB_XS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) terratec_htc_usb_xs_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* attach demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) dvb->fe[0] = dvb_attach(drxk_attach, &terratec_htc_stick_drxk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (!dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /* Attach the demodulator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (!dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) &em28xx_cxd2820r_tda18271_config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) case EM2874_BOARD_KWORLD_UB435Q_V2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) dvb->fe[0] = dvb_attach(lgdt3305_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) &em2874_lgdt3305_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (!dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) /* Attach the demodulator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (!dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) &kworld_ub435q_v2_config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) case EM2874_BOARD_KWORLD_UB435Q_V3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) struct i2c_adapter *adapter = &dev->i2c_adap[dev->def_i2c_bus];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) dvb->fe[0] = dvb_attach(lgdt3305_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) &em2874_lgdt3305_nogate_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (!dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) kworld_ub435q_v3_config.fe = dvb->fe[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) dvb->i2c_client_tuner = dvb_module_probe("tda18212", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) adapter, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) &kworld_ub435q_v3_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) if (!dvb->i2c_client_tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) dvb_frontend_detach(dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) result = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) case EM2874_BOARD_PCTV_HD_MINI_80E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) dvb->fe[0] = dvb_attach(drx39xxj_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) &dev->i2c_adap[dev->def_i2c_bus]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) if (dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) dvb->fe[0] = dvb_attach(tda18271_attach, dvb->fe[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) &dev->i2c_adap[dev->def_i2c_bus],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) &pinnacle_80e_dvb_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (!dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) case EM28178_BOARD_PCTV_461E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) result = em28178_dvb_init_pctv_461e(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) case EM28178_BOARD_PCTV_461E_V2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) result = em28178_dvb_init_pctv_461e_v2(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) case EM28178_BOARD_PCTV_292E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) result = em28178_dvb_init_pctv_292e(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) case EM28178_BOARD_TERRATEC_T2_STICK_HD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) result = em28178_dvb_init_terratec_t2_stick_hd(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) case EM28178_BOARD_PLEX_PX_BCUD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) result = em28178_dvb_init_plex_px_bcud(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) case EM28174_BOARD_HAUPPAUGE_WINTV_DUALHD_DVB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) result = em28174_dvb_init_hauppauge_wintv_dualhd_dvb(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) case EM28174_BOARD_HAUPPAUGE_WINTV_DUALHD_01595:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) result = em28174_dvb_init_hauppauge_wintv_dualhd_01595(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) dev_err(&dev->intf->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) "The frontend of your DVB/ATSC card isn't supported yet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if (!dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) dev_err(&dev->intf->dev, "frontend initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /* define general-purpose callback pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) dvb->fe[0]->callback = em28xx_tuner_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (dvb->fe[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) dvb->fe[1]->callback = em28xx_tuner_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) /* register everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) result = em28xx_register_dvb(dvb, THIS_MODULE, dev, &dev->intf->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if (dev->dvb_xfer_bulk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) dvb_alt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) } else { /* isoc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) dvb_alt = dev->dvb_alt_isoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) udev = interface_to_usbdev(dev->intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) usb_set_interface(udev, dev->ifnum, dvb_alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) dev_info(&dev->intf->dev, "DVB extension successfully initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) kref_get(&dev->ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) em28xx_set_mode(dev, EM28XX_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) mutex_unlock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) em28xx_uninit_usb_xfer(dev, EM28XX_DIGITAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) kfree(dvb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) dev->dvb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) goto ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) static inline void prevent_sleep(struct dvb_frontend_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ops->set_voltage = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) ops->sleep = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) ops->tuner_ops.sleep = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) static int em28xx_dvb_fini(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) struct em28xx_dvb *dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (dev->is_audio_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) /* Shouldn't initialize IR for this interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) if (!dev->board.has_dvb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) /* This device does not support the extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) if (!dev->dvb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) dev_info(&dev->intf->dev, "Closing DVB extension\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) dvb = dev->dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) em28xx_uninit_usb_xfer(dev, EM28XX_DIGITAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (dev->disconnected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) * We cannot tell the device to sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) * once it has been unplugged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) if (dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) prevent_sleep(&dvb->fe[0]->ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) dvb->fe[0]->exit = DVB_FE_DEVICE_REMOVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (dvb->fe[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) prevent_sleep(&dvb->fe[1]->ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) dvb->fe[1]->exit = DVB_FE_DEVICE_REMOVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) em28xx_unregister_dvb(dvb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) /* release I2C module bindings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) dvb_module_release(dvb->i2c_client_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) dvb_module_release(dvb->i2c_client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) dvb_module_release(dvb->i2c_client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) kfree(dvb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) dev->dvb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) kref_put(&dev->ref, em28xx_free_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) static int em28xx_dvb_suspend(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) if (dev->is_audio_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) if (!dev->board.has_dvb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) dev_info(&dev->intf->dev, "Suspending DVB extension\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) if (dev->dvb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) struct em28xx_dvb *dvb = dev->dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) if (dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) ret = dvb_frontend_suspend(dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) dev_info(&dev->intf->dev, "fe0 suspend %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) if (dvb->fe[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) dvb_frontend_suspend(dvb->fe[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) dev_info(&dev->intf->dev, "fe1 suspend %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) static int em28xx_dvb_resume(struct em28xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) if (dev->is_audio_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) if (!dev->board.has_dvb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) dev_info(&dev->intf->dev, "Resuming DVB extension\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) if (dev->dvb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) struct em28xx_dvb *dvb = dev->dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (dvb->fe[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ret = dvb_frontend_resume(dvb->fe[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) dev_info(&dev->intf->dev, "fe0 resume %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) if (dvb->fe[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) ret = dvb_frontend_resume(dvb->fe[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) dev_info(&dev->intf->dev, "fe1 resume %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) static struct em28xx_ops dvb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .id = EM28XX_DVB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .name = "Em28xx dvb Extension",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .init = em28xx_dvb_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .fini = em28xx_dvb_fini,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .suspend = em28xx_dvb_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .resume = em28xx_dvb_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) static int __init em28xx_dvb_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) return em28xx_register_extension(&dvb_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) static void __exit em28xx_dvb_unregister(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) em28xx_unregister_extension(&dvb_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) module_init(em28xx_dvb_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) module_exit(em28xx_dvb_unregister);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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