Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _DVB_USB_M920X_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _DVB_USB_M920X_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define DVB_USB_LOG_PREFIX "m920x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include "dvb-usb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define deb(args...)   dprintk(dvb_usb_m920x_debug,0x01,args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define M9206_CORE	0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define M9206_RC_STATE	0xff51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define M9206_RC_KEY	0xff52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define M9206_RC_INIT1	0xff54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define M9206_RC_INIT2	0xff55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define M9206_FW_GO	0xff69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define M9206_I2C	0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define M9206_FILTER	0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define M9206_FW	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define M9206_MAX_FILTERS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define M9206_MAX_ADAPTERS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) sequences found in logs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) [index value]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 0x80 write addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) (0x00 out byte)*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 0x40 out byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 0x80 write addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (0x00 out byte)*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 0x80 read addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) (0x21 in byte)*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 0x60 in byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) this sequence works:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 0x80 read addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (0x21 in byte)*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 0x60 in byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Guess at API of the I2C function:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) I2C operation is done one byte at a time with USB control messages.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) index the messages is sent to is made up of a set of flags that control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) the I2C bus state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 0x80:  Send START condition.  After a START condition, one would normally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)        always send the 7-bit slave I2C address as the 7 MSB, followed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)        the read/write bit as the LSB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0x40:  Send STOP condition.  This should be set on the last byte of an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)        I2C transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0x20:  Read a byte from the slave.  As opposed to writing a byte to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)        slave.  The slave will normally not produce any data unless you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)        set the R/W bit to 1 when sending the slave's address after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)        START condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0x01:  Respond with ACK, as opposed to a NACK.  For a multi-byte read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)        the master should send an ACK, that is pull SDA low during the 9th
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)        clock cycle, after every byte but the last.  This flags only makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)        sense when bit 0x20 is set, indicating a read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) What any other bits might mean, or how to get the slave's ACK/NACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) response to a write, is unknown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct m920x_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	u16 filters[M9206_MAX_ADAPTERS][M9206_MAX_FILTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	int filtering_enabled[M9206_MAX_ADAPTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	int rep_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Initialisation data for the m920x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct m920x_inits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	u16 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	u8  data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif