^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Common header-file of the Linux driver for the Afatech 9005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * USB1.1 DVB-T receiver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Thanks to Afatech who kindly provided information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _DVB_USB_AF9005_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _DVB_USB_AF9005_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DVB_USB_LOG_PREFIX "af9005"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "dvb-usb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) extern int dvb_usb_af9005_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define deb_rc(args...) dprintk(dvb_usb_af9005_debug,0x04,args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define deb_reg(args...) dprintk(dvb_usb_af9005_debug,0x08,args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define deb_i2c(args...) dprintk(dvb_usb_af9005_debug,0x10,args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define deb_fw(args...) dprintk(dvb_usb_af9005_debug,0x20,args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) extern bool dvb_usb_af9005_led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FW_BULKOUT_SIZE 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) FW_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) FW_CONFIRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) FW_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* af9005 commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AF9005_OFDM_REG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AF9005_TUNER_REG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AF9005_REGISTER_RW 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AF9005_REGISTER_RW_ACK 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AF9005_CMD_OFDM_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AF9005_CMD_TUNER 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AF9005_CMD_BURST 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AF9005_CMD_AUTOINC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AF9005_CMD_READ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AF9005_CMD_WRITE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* af9005 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define APO_REG_RESET 0xAEFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define APO_REG_I2C_RW_CAN_TUNER 0xF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define APO_REG_I2C_RW_SILICON_TUNER 0xF001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define APO_REG_GPIO_RW_SILICON_TUNER 0xFFFE /* also for OFSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define APO_REG_TRIGGER_OFSM 0xFFFF /* also for OFSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Apollo Registers from VLSI *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define xd_p_reg_aagc_inverted_agc 0xA000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define reg_aagc_inverted_agc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define reg_aagc_inverted_agc_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define reg_aagc_inverted_agc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define xd_p_reg_aagc_sign_only 0xA000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define reg_aagc_sign_only_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define reg_aagc_sign_only_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define reg_aagc_sign_only_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define xd_p_reg_aagc_slow_adc_en 0xA000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define reg_aagc_slow_adc_en_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define reg_aagc_slow_adc_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define reg_aagc_slow_adc_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define xd_p_reg_aagc_slow_adc_scale 0xA000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define reg_aagc_slow_adc_scale_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define reg_aagc_slow_adc_scale_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define reg_aagc_slow_adc_scale_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define xd_p_reg_aagc_check_slow_adc_lock 0xA001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define reg_aagc_check_slow_adc_lock_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define reg_aagc_check_slow_adc_lock_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define reg_aagc_check_slow_adc_lock_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define xd_p_reg_aagc_init_control 0xA001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define reg_aagc_init_control_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define reg_aagc_init_control_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define reg_aagc_init_control_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define xd_p_reg_aagc_total_gain_sel 0xA001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define reg_aagc_total_gain_sel_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define reg_aagc_total_gain_sel_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define reg_aagc_total_gain_sel_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define xd_p_reg_aagc_out_inv 0xA001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define reg_aagc_out_inv_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define reg_aagc_out_inv_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define reg_aagc_out_inv_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define xd_p_reg_aagc_int_en 0xA001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define reg_aagc_int_en_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define reg_aagc_int_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define reg_aagc_int_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define xd_p_reg_aagc_lock_change_flag 0xA001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define reg_aagc_lock_change_flag_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define reg_aagc_lock_change_flag_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define reg_aagc_lock_change_flag_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define xd_p_reg_aagc_rf_loop_bw_scale_acquire 0xA002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define reg_aagc_rf_loop_bw_scale_acquire_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define reg_aagc_rf_loop_bw_scale_acquire_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define reg_aagc_rf_loop_bw_scale_acquire_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define xd_p_reg_aagc_rf_loop_bw_scale_track 0xA003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define reg_aagc_rf_loop_bw_scale_track_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define reg_aagc_rf_loop_bw_scale_track_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define reg_aagc_rf_loop_bw_scale_track_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define xd_p_reg_aagc_if_loop_bw_scale_acquire 0xA004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define reg_aagc_if_loop_bw_scale_acquire_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define reg_aagc_if_loop_bw_scale_acquire_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define reg_aagc_if_loop_bw_scale_acquire_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define xd_p_reg_aagc_if_loop_bw_scale_track 0xA005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define reg_aagc_if_loop_bw_scale_track_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define reg_aagc_if_loop_bw_scale_track_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define reg_aagc_if_loop_bw_scale_track_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define xd_p_reg_aagc_max_rf_agc_7_0 0xA006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define reg_aagc_max_rf_agc_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define reg_aagc_max_rf_agc_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define reg_aagc_max_rf_agc_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define xd_p_reg_aagc_max_rf_agc_9_8 0xA007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define reg_aagc_max_rf_agc_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define reg_aagc_max_rf_agc_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define reg_aagc_max_rf_agc_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define xd_p_reg_aagc_min_rf_agc_7_0 0xA008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define reg_aagc_min_rf_agc_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define reg_aagc_min_rf_agc_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define reg_aagc_min_rf_agc_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define xd_p_reg_aagc_min_rf_agc_9_8 0xA009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define reg_aagc_min_rf_agc_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define reg_aagc_min_rf_agc_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define reg_aagc_min_rf_agc_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define xd_p_reg_aagc_max_if_agc_7_0 0xA00A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define reg_aagc_max_if_agc_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define reg_aagc_max_if_agc_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define reg_aagc_max_if_agc_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define xd_p_reg_aagc_max_if_agc_9_8 0xA00B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define reg_aagc_max_if_agc_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define reg_aagc_max_if_agc_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define reg_aagc_max_if_agc_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define xd_p_reg_aagc_min_if_agc_7_0 0xA00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define reg_aagc_min_if_agc_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define reg_aagc_min_if_agc_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define reg_aagc_min_if_agc_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define xd_p_reg_aagc_min_if_agc_9_8 0xA00D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define reg_aagc_min_if_agc_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define reg_aagc_min_if_agc_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define reg_aagc_min_if_agc_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define xd_p_reg_aagc_lock_sample_scale 0xA00E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define reg_aagc_lock_sample_scale_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define reg_aagc_lock_sample_scale_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define reg_aagc_lock_sample_scale_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define xd_p_reg_aagc_rf_agc_lock_scale_acquire 0xA00F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define reg_aagc_rf_agc_lock_scale_acquire_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define reg_aagc_rf_agc_lock_scale_acquire_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define reg_aagc_rf_agc_lock_scale_acquire_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define xd_p_reg_aagc_rf_agc_lock_scale_track 0xA00F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define reg_aagc_rf_agc_lock_scale_track_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define reg_aagc_rf_agc_lock_scale_track_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define reg_aagc_rf_agc_lock_scale_track_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define xd_p_reg_aagc_if_agc_lock_scale_acquire 0xA010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define reg_aagc_if_agc_lock_scale_acquire_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define reg_aagc_if_agc_lock_scale_acquire_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define reg_aagc_if_agc_lock_scale_acquire_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define xd_p_reg_aagc_if_agc_lock_scale_track 0xA010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define reg_aagc_if_agc_lock_scale_track_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define reg_aagc_if_agc_lock_scale_track_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define reg_aagc_if_agc_lock_scale_track_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define xd_p_reg_aagc_rf_top_numerator_7_0 0xA011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define reg_aagc_rf_top_numerator_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define reg_aagc_rf_top_numerator_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define reg_aagc_rf_top_numerator_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define xd_p_reg_aagc_rf_top_numerator_9_8 0xA012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define reg_aagc_rf_top_numerator_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define reg_aagc_rf_top_numerator_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define reg_aagc_rf_top_numerator_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define xd_p_reg_aagc_if_top_numerator_7_0 0xA013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define reg_aagc_if_top_numerator_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define reg_aagc_if_top_numerator_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define reg_aagc_if_top_numerator_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define xd_p_reg_aagc_if_top_numerator_9_8 0xA014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define reg_aagc_if_top_numerator_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define reg_aagc_if_top_numerator_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define reg_aagc_if_top_numerator_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define xd_p_reg_aagc_adc_out_desired_7_0 0xA015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define reg_aagc_adc_out_desired_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define reg_aagc_adc_out_desired_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define reg_aagc_adc_out_desired_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define xd_p_reg_aagc_adc_out_desired_8 0xA016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define reg_aagc_adc_out_desired_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define reg_aagc_adc_out_desired_8_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define reg_aagc_adc_out_desired_8_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define xd_p_reg_aagc_fixed_gain 0xA016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define reg_aagc_fixed_gain_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define reg_aagc_fixed_gain_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define reg_aagc_fixed_gain_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define xd_p_reg_aagc_lock_count_th 0xA016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define reg_aagc_lock_count_th_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define reg_aagc_lock_count_th_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define reg_aagc_lock_count_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define xd_p_reg_aagc_fixed_rf_agc_control_7_0 0xA017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define reg_aagc_fixed_rf_agc_control_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define reg_aagc_fixed_rf_agc_control_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define reg_aagc_fixed_rf_agc_control_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define xd_p_reg_aagc_fixed_rf_agc_control_15_8 0xA018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define reg_aagc_fixed_rf_agc_control_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define reg_aagc_fixed_rf_agc_control_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define reg_aagc_fixed_rf_agc_control_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define xd_p_reg_aagc_fixed_rf_agc_control_23_16 0xA019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define reg_aagc_fixed_rf_agc_control_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define reg_aagc_fixed_rf_agc_control_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define reg_aagc_fixed_rf_agc_control_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define xd_p_reg_aagc_fixed_rf_agc_control_30_24 0xA01A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define reg_aagc_fixed_rf_agc_control_30_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define reg_aagc_fixed_rf_agc_control_30_24_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define reg_aagc_fixed_rf_agc_control_30_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define xd_p_reg_aagc_fixed_if_agc_control_7_0 0xA01B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define reg_aagc_fixed_if_agc_control_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define reg_aagc_fixed_if_agc_control_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define reg_aagc_fixed_if_agc_control_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define xd_p_reg_aagc_fixed_if_agc_control_15_8 0xA01C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define reg_aagc_fixed_if_agc_control_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define reg_aagc_fixed_if_agc_control_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define reg_aagc_fixed_if_agc_control_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define xd_p_reg_aagc_fixed_if_agc_control_23_16 0xA01D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define reg_aagc_fixed_if_agc_control_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define reg_aagc_fixed_if_agc_control_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define reg_aagc_fixed_if_agc_control_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define xd_p_reg_aagc_fixed_if_agc_control_30_24 0xA01E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define reg_aagc_fixed_if_agc_control_30_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define reg_aagc_fixed_if_agc_control_30_24_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define reg_aagc_fixed_if_agc_control_30_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define xd_p_reg_aagc_rf_agc_unlock_numerator 0xA01F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define reg_aagc_rf_agc_unlock_numerator_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define reg_aagc_rf_agc_unlock_numerator_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define reg_aagc_rf_agc_unlock_numerator_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define xd_p_reg_aagc_if_agc_unlock_numerator 0xA020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define reg_aagc_if_agc_unlock_numerator_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define reg_aagc_if_agc_unlock_numerator_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define reg_aagc_if_agc_unlock_numerator_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define xd_p_reg_unplug_th 0xA021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define reg_unplug_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define reg_unplug_th_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define reg_aagc_rf_x0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define xd_p_reg_weak_signal_rfagc_thr 0xA022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define reg_weak_signal_rfagc_thr_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define reg_weak_signal_rfagc_thr_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define reg_weak_signal_rfagc_thr_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define xd_p_reg_unplug_rf_gain_th 0xA023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define reg_unplug_rf_gain_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define reg_unplug_rf_gain_th_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define reg_unplug_rf_gain_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define xd_p_reg_unplug_dtop_rf_gain_th 0xA024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define reg_unplug_dtop_rf_gain_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define reg_unplug_dtop_rf_gain_th_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define reg_unplug_dtop_rf_gain_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define xd_p_reg_unplug_dtop_if_gain_th 0xA025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define reg_unplug_dtop_if_gain_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define reg_unplug_dtop_if_gain_th_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define reg_unplug_dtop_if_gain_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define xd_p_reg_top_recover_at_unplug_en 0xA026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define reg_top_recover_at_unplug_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define reg_top_recover_at_unplug_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define reg_top_recover_at_unplug_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define xd_p_reg_aagc_rf_x6 0xA027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define reg_aagc_rf_x6_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define reg_aagc_rf_x6_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define reg_aagc_rf_x6_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define xd_p_reg_aagc_rf_x7 0xA028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define reg_aagc_rf_x7_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define reg_aagc_rf_x7_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define reg_aagc_rf_x7_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define xd_p_reg_aagc_rf_x8 0xA029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define reg_aagc_rf_x8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define reg_aagc_rf_x8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define reg_aagc_rf_x8_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define xd_p_reg_aagc_rf_x9 0xA02A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define reg_aagc_rf_x9_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define reg_aagc_rf_x9_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define reg_aagc_rf_x9_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define xd_p_reg_aagc_rf_x10 0xA02B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define reg_aagc_rf_x10_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define reg_aagc_rf_x10_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define reg_aagc_rf_x10_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define xd_p_reg_aagc_rf_x11 0xA02C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define reg_aagc_rf_x11_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define reg_aagc_rf_x11_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define reg_aagc_rf_x11_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define xd_p_reg_aagc_rf_x12 0xA02D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define reg_aagc_rf_x12_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define reg_aagc_rf_x12_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define reg_aagc_rf_x12_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define xd_p_reg_aagc_rf_x13 0xA02E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define reg_aagc_rf_x13_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define reg_aagc_rf_x13_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define reg_aagc_rf_x13_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define xd_p_reg_aagc_if_x0 0xA02F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define reg_aagc_if_x0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define reg_aagc_if_x0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define reg_aagc_if_x0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define xd_p_reg_aagc_if_x1 0xA030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define reg_aagc_if_x1_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define reg_aagc_if_x1_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define reg_aagc_if_x1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define xd_p_reg_aagc_if_x2 0xA031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define reg_aagc_if_x2_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define reg_aagc_if_x2_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define reg_aagc_if_x2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define xd_p_reg_aagc_if_x3 0xA032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define reg_aagc_if_x3_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define reg_aagc_if_x3_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define reg_aagc_if_x3_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define xd_p_reg_aagc_if_x4 0xA033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define reg_aagc_if_x4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define reg_aagc_if_x4_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define reg_aagc_if_x4_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define xd_p_reg_aagc_if_x5 0xA034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define reg_aagc_if_x5_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define reg_aagc_if_x5_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define reg_aagc_if_x5_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define xd_p_reg_aagc_if_x6 0xA035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define reg_aagc_if_x6_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define reg_aagc_if_x6_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define reg_aagc_if_x6_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define xd_p_reg_aagc_if_x7 0xA036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define reg_aagc_if_x7_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define reg_aagc_if_x7_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define reg_aagc_if_x7_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define xd_p_reg_aagc_if_x8 0xA037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define reg_aagc_if_x8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define reg_aagc_if_x8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define reg_aagc_if_x8_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define xd_p_reg_aagc_if_x9 0xA038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define reg_aagc_if_x9_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define reg_aagc_if_x9_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define reg_aagc_if_x9_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define xd_p_reg_aagc_if_x10 0xA039
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define reg_aagc_if_x10_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define reg_aagc_if_x10_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define reg_aagc_if_x10_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define xd_p_reg_aagc_if_x11 0xA03A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define reg_aagc_if_x11_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define reg_aagc_if_x11_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define reg_aagc_if_x11_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define xd_p_reg_aagc_if_x12 0xA03B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define reg_aagc_if_x12_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define reg_aagc_if_x12_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define reg_aagc_if_x12_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define xd_p_reg_aagc_if_x13 0xA03C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define reg_aagc_if_x13_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define reg_aagc_if_x13_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define reg_aagc_if_x13_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define xd_p_reg_aagc_min_rf_ctl_8bit_for_dca 0xA03D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define reg_aagc_min_rf_ctl_8bit_for_dca_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define reg_aagc_min_rf_ctl_8bit_for_dca_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define reg_aagc_min_rf_ctl_8bit_for_dca_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define xd_p_reg_aagc_min_if_ctl_8bit_for_dca 0xA03E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define reg_aagc_min_if_ctl_8bit_for_dca_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define reg_aagc_min_if_ctl_8bit_for_dca_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define reg_aagc_min_if_ctl_8bit_for_dca_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define xd_r_reg_aagc_total_gain_7_0 0xA070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define reg_aagc_total_gain_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define reg_aagc_total_gain_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define reg_aagc_total_gain_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define xd_r_reg_aagc_total_gain_15_8 0xA071
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define reg_aagc_total_gain_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define reg_aagc_total_gain_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define reg_aagc_total_gain_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define xd_p_reg_aagc_in_sat_cnt_7_0 0xA074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define reg_aagc_in_sat_cnt_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define reg_aagc_in_sat_cnt_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define reg_aagc_in_sat_cnt_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define xd_p_reg_aagc_in_sat_cnt_15_8 0xA075
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define reg_aagc_in_sat_cnt_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define reg_aagc_in_sat_cnt_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define reg_aagc_in_sat_cnt_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define xd_p_reg_aagc_in_sat_cnt_23_16 0xA076
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define reg_aagc_in_sat_cnt_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define reg_aagc_in_sat_cnt_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define reg_aagc_in_sat_cnt_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define xd_p_reg_aagc_in_sat_cnt_31_24 0xA077
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define reg_aagc_in_sat_cnt_31_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define reg_aagc_in_sat_cnt_31_24_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define reg_aagc_in_sat_cnt_31_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define xd_r_reg_aagc_digital_rf_volt_7_0 0xA078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define reg_aagc_digital_rf_volt_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define reg_aagc_digital_rf_volt_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define reg_aagc_digital_rf_volt_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define xd_r_reg_aagc_digital_rf_volt_9_8 0xA079
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define reg_aagc_digital_rf_volt_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define reg_aagc_digital_rf_volt_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define reg_aagc_digital_rf_volt_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define xd_r_reg_aagc_digital_if_volt_7_0 0xA07A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define reg_aagc_digital_if_volt_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define reg_aagc_digital_if_volt_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define reg_aagc_digital_if_volt_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define xd_r_reg_aagc_digital_if_volt_9_8 0xA07B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define reg_aagc_digital_if_volt_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define reg_aagc_digital_if_volt_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define reg_aagc_digital_if_volt_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define xd_r_reg_aagc_rf_gain 0xA07C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define reg_aagc_rf_gain_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define reg_aagc_rf_gain_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define reg_aagc_rf_gain_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define xd_r_reg_aagc_if_gain 0xA07D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define reg_aagc_if_gain_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define reg_aagc_if_gain_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define reg_aagc_if_gain_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define xd_p_tinr_imp_indicator 0xA080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define tinr_imp_indicator_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define tinr_imp_indicator_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define tinr_imp_indicator_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define xd_p_reg_tinr_fifo_size 0xA080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define reg_tinr_fifo_size_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define reg_tinr_fifo_size_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define reg_tinr_fifo_size_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define xd_p_reg_tinr_saturation_cnt_th 0xA081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define reg_tinr_saturation_cnt_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define reg_tinr_saturation_cnt_th_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define reg_tinr_saturation_cnt_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define xd_p_reg_tinr_saturation_th_3_0 0xA081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define reg_tinr_saturation_th_3_0_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define reg_tinr_saturation_th_3_0_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define reg_tinr_saturation_th_3_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define xd_p_reg_tinr_saturation_th_8_4 0xA082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define reg_tinr_saturation_th_8_4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define reg_tinr_saturation_th_8_4_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define reg_tinr_saturation_th_8_4_lsb 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define xd_p_reg_tinr_imp_duration_th_2k_7_0 0xA083
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define reg_tinr_imp_duration_th_2k_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define reg_tinr_imp_duration_th_2k_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define reg_tinr_imp_duration_th_2k_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define xd_p_reg_tinr_imp_duration_th_2k_8 0xA084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define reg_tinr_imp_duration_th_2k_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define reg_tinr_imp_duration_th_2k_8_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define reg_tinr_imp_duration_th_2k_8_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define xd_p_reg_tinr_imp_duration_th_8k_7_0 0xA085
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define reg_tinr_imp_duration_th_8k_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define reg_tinr_imp_duration_th_8k_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define reg_tinr_imp_duration_th_8k_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define xd_p_reg_tinr_imp_duration_th_8k_10_8 0xA086
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define reg_tinr_imp_duration_th_8k_10_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define reg_tinr_imp_duration_th_8k_10_8_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define reg_tinr_imp_duration_th_8k_10_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define xd_p_reg_tinr_freq_ratio_6m_7_0 0xA087
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define reg_tinr_freq_ratio_6m_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define reg_tinr_freq_ratio_6m_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define reg_tinr_freq_ratio_6m_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define xd_p_reg_tinr_freq_ratio_6m_12_8 0xA088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define reg_tinr_freq_ratio_6m_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define reg_tinr_freq_ratio_6m_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define reg_tinr_freq_ratio_6m_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define xd_p_reg_tinr_freq_ratio_7m_7_0 0xA089
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define reg_tinr_freq_ratio_7m_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define reg_tinr_freq_ratio_7m_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define reg_tinr_freq_ratio_7m_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define xd_p_reg_tinr_freq_ratio_7m_12_8 0xA08A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define reg_tinr_freq_ratio_7m_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define reg_tinr_freq_ratio_7m_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define reg_tinr_freq_ratio_7m_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define xd_p_reg_tinr_freq_ratio_8m_7_0 0xA08B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define reg_tinr_freq_ratio_8m_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define reg_tinr_freq_ratio_8m_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define reg_tinr_freq_ratio_8m_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define xd_p_reg_tinr_freq_ratio_8m_12_8 0xA08C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define reg_tinr_freq_ratio_8m_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define reg_tinr_freq_ratio_8m_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define reg_tinr_freq_ratio_8m_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define xd_p_reg_tinr_imp_duration_th_low_2k 0xA08D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define reg_tinr_imp_duration_th_low_2k_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define reg_tinr_imp_duration_th_low_2k_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define reg_tinr_imp_duration_th_low_2k_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define xd_p_reg_tinr_imp_duration_th_low_8k 0xA08E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define reg_tinr_imp_duration_th_low_8k_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define reg_tinr_imp_duration_th_low_8k_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define reg_tinr_imp_duration_th_low_8k_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define xd_r_reg_tinr_counter_7_0 0xA090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define reg_tinr_counter_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define reg_tinr_counter_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define reg_tinr_counter_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define xd_r_reg_tinr_counter_15_8 0xA091
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define reg_tinr_counter_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define reg_tinr_counter_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define reg_tinr_counter_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define xd_p_reg_tinr_adative_tinr_en 0xA093
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define reg_tinr_adative_tinr_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define reg_tinr_adative_tinr_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define reg_tinr_adative_tinr_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define xd_p_reg_tinr_peak_fifo_size 0xA093
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define reg_tinr_peak_fifo_size_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define reg_tinr_peak_fifo_size_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define reg_tinr_peak_fifo_size_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define xd_p_reg_tinr_counter_rst 0xA093
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define reg_tinr_counter_rst_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define reg_tinr_counter_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define reg_tinr_counter_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define xd_p_reg_tinr_search_period_7_0 0xA094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define reg_tinr_search_period_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define reg_tinr_search_period_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define reg_tinr_search_period_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define xd_p_reg_tinr_search_period_15_8 0xA095
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define reg_tinr_search_period_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define reg_tinr_search_period_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define reg_tinr_search_period_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define xd_p_reg_ccifs_fcw_7_0 0xA0A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define reg_ccifs_fcw_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define reg_ccifs_fcw_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define reg_ccifs_fcw_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define xd_p_reg_ccifs_fcw_12_8 0xA0A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define reg_ccifs_fcw_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define reg_ccifs_fcw_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define reg_ccifs_fcw_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define xd_p_reg_ccifs_spec_inv 0xA0A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define reg_ccifs_spec_inv_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define reg_ccifs_spec_inv_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define reg_ccifs_spec_inv_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define xd_p_reg_gp_trigger 0xA0A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define reg_gp_trigger_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define reg_gp_trigger_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define reg_gp_trigger_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define xd_p_reg_trigger_sel 0xA0A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define reg_trigger_sel_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define reg_trigger_sel_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define reg_trigger_sel_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define xd_p_reg_debug_ofdm 0xA0A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define reg_debug_ofdm_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define reg_debug_ofdm_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define reg_debug_ofdm_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define xd_p_reg_trigger_module_sel 0xA0A3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define reg_trigger_module_sel_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define reg_trigger_module_sel_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define reg_trigger_module_sel_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define xd_p_reg_trigger_set_sel 0xA0A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define reg_trigger_set_sel_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define reg_trigger_set_sel_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define reg_trigger_set_sel_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define xd_p_reg_fw_int_mask_n 0xA0A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define reg_fw_int_mask_n_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define reg_fw_int_mask_n_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define reg_fw_int_mask_n_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define xd_p_reg_debug_group 0xA0A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define reg_debug_group_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define reg_debug_group_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define reg_debug_group_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define xd_p_reg_odbg_clk_sel 0xA0A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define reg_odbg_clk_sel_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define reg_odbg_clk_sel_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define reg_odbg_clk_sel_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define xd_p_reg_ccif_sc 0xA0C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define reg_ccif_sc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define reg_ccif_sc_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define reg_ccif_sc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define xd_r_reg_ccif_saturate 0xA0C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define reg_ccif_saturate_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define reg_ccif_saturate_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define reg_ccif_saturate_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define xd_r_reg_antif_saturate 0xA0C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define reg_antif_saturate_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define reg_antif_saturate_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define reg_antif_saturate_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define xd_r_reg_acif_saturate 0xA0C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define reg_acif_saturate_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define reg_acif_saturate_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define reg_acif_saturate_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define xd_p_reg_tmr_timer0_threshold_7_0 0xA0C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define reg_tmr_timer0_threshold_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define reg_tmr_timer0_threshold_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define reg_tmr_timer0_threshold_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define xd_p_reg_tmr_timer0_threshold_15_8 0xA0C9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define reg_tmr_timer0_threshold_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define reg_tmr_timer0_threshold_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define reg_tmr_timer0_threshold_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define xd_p_reg_tmr_timer0_enable 0xA0CA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define reg_tmr_timer0_enable_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define reg_tmr_timer0_enable_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define reg_tmr_timer0_enable_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define xd_p_reg_tmr_timer0_clk_sel 0xA0CA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define reg_tmr_timer0_clk_sel_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define reg_tmr_timer0_clk_sel_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define reg_tmr_timer0_clk_sel_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define xd_p_reg_tmr_timer0_int 0xA0CA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define reg_tmr_timer0_int_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define reg_tmr_timer0_int_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define reg_tmr_timer0_int_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define xd_p_reg_tmr_timer0_rst 0xA0CA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define reg_tmr_timer0_rst_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define reg_tmr_timer0_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define reg_tmr_timer0_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define xd_r_reg_tmr_timer0_count_7_0 0xA0CB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define reg_tmr_timer0_count_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define reg_tmr_timer0_count_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define reg_tmr_timer0_count_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define xd_r_reg_tmr_timer0_count_15_8 0xA0CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define reg_tmr_timer0_count_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define reg_tmr_timer0_count_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define reg_tmr_timer0_count_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define xd_p_reg_suspend 0xA0CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define reg_suspend_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define reg_suspend_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define reg_suspend_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define xd_p_reg_suspend_rdy 0xA0CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define reg_suspend_rdy_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define reg_suspend_rdy_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define reg_suspend_rdy_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define xd_p_reg_resume 0xA0CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define reg_resume_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define reg_resume_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define reg_resume_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define xd_p_reg_resume_rdy 0xA0CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define reg_resume_rdy_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define reg_resume_rdy_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define reg_resume_rdy_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define xd_p_reg_fmf 0xA0CE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define reg_fmf_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define reg_fmf_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define reg_fmf_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define xd_p_ccid_accumulate_num_2k_7_0 0xA100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define ccid_accumulate_num_2k_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define ccid_accumulate_num_2k_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define ccid_accumulate_num_2k_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define xd_p_ccid_accumulate_num_2k_12_8 0xA101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define ccid_accumulate_num_2k_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define ccid_accumulate_num_2k_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define ccid_accumulate_num_2k_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define xd_p_ccid_accumulate_num_8k_7_0 0xA102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define ccid_accumulate_num_8k_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define ccid_accumulate_num_8k_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define ccid_accumulate_num_8k_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define xd_p_ccid_accumulate_num_8k_14_8 0xA103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define ccid_accumulate_num_8k_14_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define ccid_accumulate_num_8k_14_8_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define ccid_accumulate_num_8k_14_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define xd_p_ccid_desired_level_0 0xA103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define ccid_desired_level_0_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define ccid_desired_level_0_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define ccid_desired_level_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define xd_p_ccid_desired_level_8_1 0xA104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define ccid_desired_level_8_1_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define ccid_desired_level_8_1_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define ccid_desired_level_8_1_lsb 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define xd_p_ccid_apply_delay 0xA105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define ccid_apply_delay_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define ccid_apply_delay_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define ccid_apply_delay_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define xd_p_ccid_CCID_Threshold1 0xA106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define ccid_CCID_Threshold1_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define ccid_CCID_Threshold1_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define ccid_CCID_Threshold1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define xd_p_ccid_CCID_Threshold2 0xA107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define ccid_CCID_Threshold2_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define ccid_CCID_Threshold2_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define ccid_CCID_Threshold2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define xd_p_reg_ccid_gain_scale 0xA108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define reg_ccid_gain_scale_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define reg_ccid_gain_scale_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define reg_ccid_gain_scale_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define xd_p_reg_ccid2_passband_gain_set 0xA108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define reg_ccid2_passband_gain_set_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define reg_ccid2_passband_gain_set_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define reg_ccid2_passband_gain_set_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define xd_r_ccid_multiplier_7_0 0xA109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define ccid_multiplier_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define ccid_multiplier_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define ccid_multiplier_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define xd_r_ccid_multiplier_15_8 0xA10A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define ccid_multiplier_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define ccid_multiplier_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define ccid_multiplier_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define xd_r_ccid_right_shift_bits 0xA10B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define ccid_right_shift_bits_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define ccid_right_shift_bits_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define ccid_right_shift_bits_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define xd_r_reg_ccid_sx_7_0 0xA10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define reg_ccid_sx_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define reg_ccid_sx_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define reg_ccid_sx_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define xd_r_reg_ccid_sx_15_8 0xA10D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define reg_ccid_sx_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define reg_ccid_sx_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define reg_ccid_sx_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define xd_r_reg_ccid_sx_21_16 0xA10E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define reg_ccid_sx_21_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define reg_ccid_sx_21_16_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define reg_ccid_sx_21_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define xd_r_reg_ccid_sy_7_0 0xA110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define reg_ccid_sy_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define reg_ccid_sy_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define reg_ccid_sy_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define xd_r_reg_ccid_sy_15_8 0xA111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define reg_ccid_sy_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define reg_ccid_sy_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define reg_ccid_sy_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define xd_r_reg_ccid_sy_23_16 0xA112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define reg_ccid_sy_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define reg_ccid_sy_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define reg_ccid_sy_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define xd_r_reg_ccid2_sz_7_0 0xA114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define reg_ccid2_sz_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define reg_ccid2_sz_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define reg_ccid2_sz_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define xd_r_reg_ccid2_sz_15_8 0xA115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define reg_ccid2_sz_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define reg_ccid2_sz_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define reg_ccid2_sz_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define xd_r_reg_ccid2_sz_23_16 0xA116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define reg_ccid2_sz_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define reg_ccid2_sz_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define reg_ccid2_sz_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define xd_r_reg_ccid2_sz_25_24 0xA117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define reg_ccid2_sz_25_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define reg_ccid2_sz_25_24_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define reg_ccid2_sz_25_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define xd_r_reg_ccid2_sy_7_0 0xA118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define reg_ccid2_sy_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define reg_ccid2_sy_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define reg_ccid2_sy_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define xd_r_reg_ccid2_sy_15_8 0xA119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define reg_ccid2_sy_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define reg_ccid2_sy_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define reg_ccid2_sy_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define xd_r_reg_ccid2_sy_23_16 0xA11A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define reg_ccid2_sy_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define reg_ccid2_sy_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define reg_ccid2_sy_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define xd_r_reg_ccid2_sy_25_24 0xA11B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define reg_ccid2_sy_25_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define reg_ccid2_sy_25_24_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define reg_ccid2_sy_25_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define xd_p_dagc1_accumulate_num_2k_7_0 0xA120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define dagc1_accumulate_num_2k_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define dagc1_accumulate_num_2k_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define dagc1_accumulate_num_2k_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define xd_p_dagc1_accumulate_num_2k_12_8 0xA121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define dagc1_accumulate_num_2k_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define dagc1_accumulate_num_2k_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define dagc1_accumulate_num_2k_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define xd_p_dagc1_accumulate_num_8k_7_0 0xA122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define dagc1_accumulate_num_8k_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define dagc1_accumulate_num_8k_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define dagc1_accumulate_num_8k_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define xd_p_dagc1_accumulate_num_8k_14_8 0xA123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define dagc1_accumulate_num_8k_14_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define dagc1_accumulate_num_8k_14_8_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define dagc1_accumulate_num_8k_14_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define xd_p_dagc1_desired_level_0 0xA123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define dagc1_desired_level_0_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define dagc1_desired_level_0_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define dagc1_desired_level_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define xd_p_dagc1_desired_level_8_1 0xA124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define dagc1_desired_level_8_1_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define dagc1_desired_level_8_1_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define dagc1_desired_level_8_1_lsb 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define xd_p_dagc1_apply_delay 0xA125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define dagc1_apply_delay_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define dagc1_apply_delay_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define dagc1_apply_delay_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define xd_p_dagc1_bypass_scale_ctl 0xA126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define dagc1_bypass_scale_ctl_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define dagc1_bypass_scale_ctl_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define dagc1_bypass_scale_ctl_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define xd_p_reg_dagc1_in_sat_cnt_7_0 0xA127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define reg_dagc1_in_sat_cnt_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define reg_dagc1_in_sat_cnt_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define reg_dagc1_in_sat_cnt_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define xd_p_reg_dagc1_in_sat_cnt_15_8 0xA128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define reg_dagc1_in_sat_cnt_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define reg_dagc1_in_sat_cnt_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define reg_dagc1_in_sat_cnt_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define xd_p_reg_dagc1_in_sat_cnt_23_16 0xA129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define reg_dagc1_in_sat_cnt_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define reg_dagc1_in_sat_cnt_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define reg_dagc1_in_sat_cnt_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define xd_p_reg_dagc1_in_sat_cnt_31_24 0xA12A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define reg_dagc1_in_sat_cnt_31_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define reg_dagc1_in_sat_cnt_31_24_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define reg_dagc1_in_sat_cnt_31_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define xd_p_reg_dagc1_out_sat_cnt_7_0 0xA12B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define reg_dagc1_out_sat_cnt_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define reg_dagc1_out_sat_cnt_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define reg_dagc1_out_sat_cnt_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define xd_p_reg_dagc1_out_sat_cnt_15_8 0xA12C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define reg_dagc1_out_sat_cnt_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define reg_dagc1_out_sat_cnt_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define reg_dagc1_out_sat_cnt_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define xd_p_reg_dagc1_out_sat_cnt_23_16 0xA12D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define reg_dagc1_out_sat_cnt_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define reg_dagc1_out_sat_cnt_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define reg_dagc1_out_sat_cnt_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define xd_p_reg_dagc1_out_sat_cnt_31_24 0xA12E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define reg_dagc1_out_sat_cnt_31_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define reg_dagc1_out_sat_cnt_31_24_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define reg_dagc1_out_sat_cnt_31_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define xd_r_dagc1_multiplier_7_0 0xA136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define dagc1_multiplier_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define dagc1_multiplier_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define dagc1_multiplier_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define xd_r_dagc1_multiplier_15_8 0xA137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define dagc1_multiplier_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define dagc1_multiplier_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define dagc1_multiplier_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define xd_r_dagc1_right_shift_bits 0xA138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define dagc1_right_shift_bits_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define dagc1_right_shift_bits_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define dagc1_right_shift_bits_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define xd_p_reg_bfs_fcw_7_0 0xA140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define reg_bfs_fcw_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define reg_bfs_fcw_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define reg_bfs_fcw_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define xd_p_reg_bfs_fcw_15_8 0xA141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define reg_bfs_fcw_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define reg_bfs_fcw_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define reg_bfs_fcw_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define xd_p_reg_bfs_fcw_22_16 0xA142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define reg_bfs_fcw_22_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define reg_bfs_fcw_22_16_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define reg_bfs_fcw_22_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define xd_p_reg_antif_sf_7_0 0xA144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define reg_antif_sf_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define reg_antif_sf_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define reg_antif_sf_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define xd_p_reg_antif_sf_11_8 0xA145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define reg_antif_sf_11_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define reg_antif_sf_11_8_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define reg_antif_sf_11_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define xd_r_bfs_fcw_q_7_0 0xA150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define bfs_fcw_q_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define bfs_fcw_q_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define bfs_fcw_q_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define xd_r_bfs_fcw_q_15_8 0xA151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define bfs_fcw_q_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define bfs_fcw_q_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define bfs_fcw_q_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define xd_r_bfs_fcw_q_22_16 0xA152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define bfs_fcw_q_22_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define bfs_fcw_q_22_16_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define bfs_fcw_q_22_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define xd_p_reg_dca_enu 0xA160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define reg_dca_enu_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define reg_dca_enu_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define reg_dca_enu_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define xd_p_reg_dca_enl 0xA160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define reg_dca_enl_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define reg_dca_enl_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define reg_dca_enl_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define xd_p_reg_dca_lower_chip 0xA160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define reg_dca_lower_chip_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define reg_dca_lower_chip_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define reg_dca_lower_chip_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define xd_p_reg_dca_upper_chip 0xA160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define reg_dca_upper_chip_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define reg_dca_upper_chip_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define reg_dca_upper_chip_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define xd_p_reg_dca_platch 0xA160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define reg_dca_platch_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define reg_dca_platch_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define reg_dca_platch_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define xd_p_reg_dca_th 0xA161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define reg_dca_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define reg_dca_th_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define reg_dca_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define xd_p_reg_dca_scale 0xA162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define reg_dca_scale_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define reg_dca_scale_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define reg_dca_scale_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define xd_p_reg_dca_tone_7_0 0xA163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define reg_dca_tone_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define reg_dca_tone_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define reg_dca_tone_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define xd_p_reg_dca_tone_12_8 0xA164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define reg_dca_tone_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define reg_dca_tone_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define reg_dca_tone_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define xd_p_reg_dca_time_7_0 0xA165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define reg_dca_time_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define reg_dca_time_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define reg_dca_time_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define xd_p_reg_dca_time_15_8 0xA166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define reg_dca_time_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define reg_dca_time_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define reg_dca_time_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define xd_r_dcasm 0xA167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define dcasm_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define dcasm_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define dcasm_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define xd_p_reg_qnt_valuew_7_0 0xA168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define reg_qnt_valuew_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define reg_qnt_valuew_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define reg_qnt_valuew_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define xd_p_reg_qnt_valuew_10_8 0xA169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define reg_qnt_valuew_10_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define reg_qnt_valuew_10_8_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define reg_qnt_valuew_10_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define xd_p_dca_sbx_gain_diff_7_0 0xA16A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define dca_sbx_gain_diff_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define dca_sbx_gain_diff_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define dca_sbx_gain_diff_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define xd_p_dca_sbx_gain_diff_9_8 0xA16B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define dca_sbx_gain_diff_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define dca_sbx_gain_diff_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define dca_sbx_gain_diff_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define xd_p_reg_dca_stand_alone 0xA16C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define reg_dca_stand_alone_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define reg_dca_stand_alone_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define reg_dca_stand_alone_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define xd_p_reg_dca_upper_out_en 0xA16C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define reg_dca_upper_out_en_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define reg_dca_upper_out_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define reg_dca_upper_out_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define xd_p_reg_dca_rc_en 0xA16C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define reg_dca_rc_en_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define reg_dca_rc_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define reg_dca_rc_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define xd_p_reg_dca_retrain_send 0xA16C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define reg_dca_retrain_send_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define reg_dca_retrain_send_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define reg_dca_retrain_send_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define xd_p_reg_dca_retrain_rec 0xA16C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define reg_dca_retrain_rec_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define reg_dca_retrain_rec_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define reg_dca_retrain_rec_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define xd_p_reg_dca_api_tpsrdy 0xA16C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define reg_dca_api_tpsrdy_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define reg_dca_api_tpsrdy_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define reg_dca_api_tpsrdy_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define xd_p_reg_dca_symbol_gap 0xA16D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define reg_dca_symbol_gap_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define reg_dca_symbol_gap_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define reg_dca_symbol_gap_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define xd_p_reg_qnt_nfvaluew_7_0 0xA16E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define reg_qnt_nfvaluew_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define reg_qnt_nfvaluew_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define reg_qnt_nfvaluew_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define xd_p_reg_qnt_nfvaluew_10_8 0xA16F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define reg_qnt_nfvaluew_10_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define reg_qnt_nfvaluew_10_8_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define reg_qnt_nfvaluew_10_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define xd_p_reg_qnt_flatness_thr_7_0 0xA170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define reg_qnt_flatness_thr_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define reg_qnt_flatness_thr_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define reg_qnt_flatness_thr_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define xd_p_reg_qnt_flatness_thr_9_8 0xA171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define reg_qnt_flatness_thr_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define reg_qnt_flatness_thr_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define reg_qnt_flatness_thr_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define xd_p_reg_dca_tone_idx_5_0 0xA171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define reg_dca_tone_idx_5_0_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define reg_dca_tone_idx_5_0_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define reg_dca_tone_idx_5_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define xd_p_reg_dca_tone_idx_12_6 0xA172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define reg_dca_tone_idx_12_6_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define reg_dca_tone_idx_12_6_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define reg_dca_tone_idx_12_6_lsb 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define xd_p_reg_dca_data_vld 0xA173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define reg_dca_data_vld_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define reg_dca_data_vld_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define reg_dca_data_vld_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define xd_p_reg_dca_read_update 0xA173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define reg_dca_read_update_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define reg_dca_read_update_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define reg_dca_read_update_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define xd_r_reg_dca_data_re_5_0 0xA173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define reg_dca_data_re_5_0_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define reg_dca_data_re_5_0_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define reg_dca_data_re_5_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define xd_r_reg_dca_data_re_10_6 0xA174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define reg_dca_data_re_10_6_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define reg_dca_data_re_10_6_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define reg_dca_data_re_10_6_lsb 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define xd_r_reg_dca_data_im_7_0 0xA175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define reg_dca_data_im_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define reg_dca_data_im_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define reg_dca_data_im_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define xd_r_reg_dca_data_im_10_8 0xA176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define reg_dca_data_im_10_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define reg_dca_data_im_10_8_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define reg_dca_data_im_10_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define xd_r_reg_dca_data_h2_7_0 0xA178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define reg_dca_data_h2_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define reg_dca_data_h2_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define reg_dca_data_h2_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define xd_r_reg_dca_data_h2_9_8 0xA179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define reg_dca_data_h2_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define reg_dca_data_h2_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define reg_dca_data_h2_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define xd_p_reg_f_adc_7_0 0xA180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define reg_f_adc_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define reg_f_adc_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define reg_f_adc_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define xd_p_reg_f_adc_15_8 0xA181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define reg_f_adc_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define reg_f_adc_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define reg_f_adc_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define xd_p_reg_f_adc_23_16 0xA182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define reg_f_adc_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define reg_f_adc_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define reg_f_adc_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define xd_r_intp_mu_7_0 0xA190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define intp_mu_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define intp_mu_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define intp_mu_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define xd_r_intp_mu_15_8 0xA191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define intp_mu_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define intp_mu_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define intp_mu_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define xd_r_intp_mu_19_16 0xA192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define intp_mu_19_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define intp_mu_19_16_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define intp_mu_19_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define xd_p_reg_agc_rst 0xA1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define reg_agc_rst_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define reg_agc_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define reg_agc_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define xd_p_rf_agc_en 0xA1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define rf_agc_en_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define rf_agc_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define rf_agc_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define xd_p_rf_agc_dis 0xA1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define rf_agc_dis_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define rf_agc_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define rf_agc_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define xd_p_if_agc_rst 0xA1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define if_agc_rst_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define if_agc_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define if_agc_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define xd_p_if_agc_en 0xA1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define if_agc_en_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define if_agc_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define if_agc_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define xd_p_if_agc_dis 0xA1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define if_agc_dis_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define if_agc_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define if_agc_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define xd_p_agc_lock 0xA1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define agc_lock_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define agc_lock_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define agc_lock_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define xd_p_reg_tinr_rst 0xA1A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define reg_tinr_rst_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define reg_tinr_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define reg_tinr_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define xd_p_reg_tinr_en 0xA1A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define reg_tinr_en_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define reg_tinr_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define reg_tinr_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define xd_p_reg_ccifs_en 0xA1A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define reg_ccifs_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define reg_ccifs_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define reg_ccifs_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define xd_p_reg_ccifs_dis 0xA1A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define reg_ccifs_dis_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define reg_ccifs_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define reg_ccifs_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define xd_p_reg_ccifs_rst 0xA1A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define reg_ccifs_rst_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define reg_ccifs_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define reg_ccifs_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define xd_p_reg_ccifs_byp 0xA1A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define reg_ccifs_byp_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define reg_ccifs_byp_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define reg_ccifs_byp_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define xd_p_reg_ccif_en 0xA1A3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define reg_ccif_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define reg_ccif_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define reg_ccif_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define xd_p_reg_ccif_dis 0xA1A3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define reg_ccif_dis_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define reg_ccif_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define reg_ccif_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define xd_p_reg_ccif_rst 0xA1A3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define reg_ccif_rst_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define reg_ccif_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define reg_ccif_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define xd_p_reg_ccif_byp 0xA1A3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define reg_ccif_byp_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define reg_ccif_byp_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define reg_ccif_byp_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define xd_p_dagc1_rst 0xA1A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define dagc1_rst_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define dagc1_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define dagc1_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define xd_p_dagc1_en 0xA1A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define dagc1_en_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define dagc1_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define dagc1_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define xd_p_dagc1_mode 0xA1A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define dagc1_mode_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define dagc1_mode_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define dagc1_mode_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define xd_p_dagc1_done 0xA1A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define dagc1_done_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define dagc1_done_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define dagc1_done_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define xd_p_ccid_rst 0xA1A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define ccid_rst_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define ccid_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define ccid_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define xd_p_ccid_en 0xA1A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define ccid_en_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define ccid_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define ccid_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define xd_p_ccid_mode 0xA1A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define ccid_mode_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define ccid_mode_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define ccid_mode_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define xd_p_ccid_done 0xA1A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define ccid_done_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define ccid_done_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define ccid_done_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define xd_r_ccid_deted 0xA1A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define ccid_deted_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define ccid_deted_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define ccid_deted_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define xd_p_ccid2_en 0xA1A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define ccid2_en_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define ccid2_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define ccid2_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define xd_p_ccid2_done 0xA1A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define ccid2_done_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define ccid2_done_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define ccid2_done_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define xd_p_reg_bfs_en 0xA1A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define reg_bfs_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define reg_bfs_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define reg_bfs_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define xd_p_reg_bfs_dis 0xA1A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define reg_bfs_dis_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define reg_bfs_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define reg_bfs_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define xd_p_reg_bfs_rst 0xA1A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define reg_bfs_rst_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define reg_bfs_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define reg_bfs_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define xd_p_reg_bfs_byp 0xA1A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define reg_bfs_byp_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define reg_bfs_byp_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define reg_bfs_byp_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define xd_p_reg_antif_en 0xA1A7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define reg_antif_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define reg_antif_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define reg_antif_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define xd_p_reg_antif_dis 0xA1A7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define reg_antif_dis_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define reg_antif_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define reg_antif_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define xd_p_reg_antif_rst 0xA1A7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define reg_antif_rst_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define reg_antif_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define reg_antif_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define xd_p_reg_antif_byp 0xA1A7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define reg_antif_byp_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define reg_antif_byp_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define reg_antif_byp_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define xd_p_intp_en 0xA1A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define intp_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define intp_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define intp_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define xd_p_intp_dis 0xA1A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define intp_dis_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define intp_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define intp_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define xd_p_intp_rst 0xA1A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define intp_rst_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define intp_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define intp_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define xd_p_intp_byp 0xA1A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define intp_byp_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define intp_byp_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define intp_byp_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define xd_p_reg_acif_en 0xA1A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define reg_acif_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define reg_acif_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define reg_acif_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define xd_p_reg_acif_dis 0xA1A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define reg_acif_dis_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define reg_acif_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define reg_acif_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define xd_p_reg_acif_rst 0xA1A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define reg_acif_rst_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define reg_acif_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define reg_acif_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define xd_p_reg_acif_byp 0xA1A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define reg_acif_byp_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define reg_acif_byp_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define reg_acif_byp_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define xd_p_reg_acif_sync_mode 0xA1A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define reg_acif_sync_mode_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define reg_acif_sync_mode_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define reg_acif_sync_mode_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define xd_p_dagc2_rst 0xA1AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define dagc2_rst_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define dagc2_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define dagc2_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define xd_p_dagc2_en 0xA1AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define dagc2_en_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define dagc2_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define dagc2_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define xd_p_dagc2_mode 0xA1AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define dagc2_mode_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define dagc2_mode_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define dagc2_mode_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define xd_p_dagc2_done 0xA1AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define dagc2_done_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define dagc2_done_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define dagc2_done_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define xd_p_reg_dca_en 0xA1AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define reg_dca_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define reg_dca_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define reg_dca_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define xd_p_dagc2_accumulate_num_2k_7_0 0xA1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define dagc2_accumulate_num_2k_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define dagc2_accumulate_num_2k_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define dagc2_accumulate_num_2k_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define xd_p_dagc2_accumulate_num_2k_12_8 0xA1C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define dagc2_accumulate_num_2k_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define dagc2_accumulate_num_2k_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define dagc2_accumulate_num_2k_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define xd_p_dagc2_accumulate_num_8k_7_0 0xA1C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define dagc2_accumulate_num_8k_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define dagc2_accumulate_num_8k_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define dagc2_accumulate_num_8k_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define xd_p_dagc2_accumulate_num_8k_12_8 0xA1C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define dagc2_accumulate_num_8k_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define dagc2_accumulate_num_8k_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define dagc2_accumulate_num_8k_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define xd_p_dagc2_desired_level_2_0 0xA1C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define dagc2_desired_level_2_0_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define dagc2_desired_level_2_0_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define dagc2_desired_level_2_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define xd_p_dagc2_desired_level_8_3 0xA1C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define dagc2_desired_level_8_3_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define dagc2_desired_level_8_3_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define dagc2_desired_level_8_3_lsb 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define xd_p_dagc2_apply_delay 0xA1C5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define dagc2_apply_delay_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define dagc2_apply_delay_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define dagc2_apply_delay_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define xd_p_dagc2_bypass_scale_ctl 0xA1C6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define dagc2_bypass_scale_ctl_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define dagc2_bypass_scale_ctl_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define dagc2_bypass_scale_ctl_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define xd_p_dagc2_programmable_shift1 0xA1C7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define dagc2_programmable_shift1_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define dagc2_programmable_shift1_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define dagc2_programmable_shift1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define xd_p_dagc2_programmable_shift2 0xA1C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define dagc2_programmable_shift2_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define dagc2_programmable_shift2_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define dagc2_programmable_shift2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define xd_p_reg_dagc2_in_sat_cnt_7_0 0xA1C9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define reg_dagc2_in_sat_cnt_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define reg_dagc2_in_sat_cnt_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define reg_dagc2_in_sat_cnt_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define xd_p_reg_dagc2_in_sat_cnt_15_8 0xA1CA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define reg_dagc2_in_sat_cnt_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define reg_dagc2_in_sat_cnt_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define reg_dagc2_in_sat_cnt_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define xd_p_reg_dagc2_in_sat_cnt_23_16 0xA1CB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define reg_dagc2_in_sat_cnt_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define reg_dagc2_in_sat_cnt_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define reg_dagc2_in_sat_cnt_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define xd_p_reg_dagc2_in_sat_cnt_31_24 0xA1CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define reg_dagc2_in_sat_cnt_31_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define reg_dagc2_in_sat_cnt_31_24_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define reg_dagc2_in_sat_cnt_31_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define xd_p_reg_dagc2_out_sat_cnt_7_0 0xA1CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define reg_dagc2_out_sat_cnt_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define reg_dagc2_out_sat_cnt_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define reg_dagc2_out_sat_cnt_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define xd_p_reg_dagc2_out_sat_cnt_15_8 0xA1CE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define reg_dagc2_out_sat_cnt_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define reg_dagc2_out_sat_cnt_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define reg_dagc2_out_sat_cnt_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define xd_p_reg_dagc2_out_sat_cnt_23_16 0xA1CF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define reg_dagc2_out_sat_cnt_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define reg_dagc2_out_sat_cnt_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define reg_dagc2_out_sat_cnt_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define xd_p_reg_dagc2_out_sat_cnt_31_24 0xA1D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define reg_dagc2_out_sat_cnt_31_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define reg_dagc2_out_sat_cnt_31_24_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define reg_dagc2_out_sat_cnt_31_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define xd_r_dagc2_multiplier_7_0 0xA1D6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define dagc2_multiplier_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define dagc2_multiplier_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define dagc2_multiplier_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define xd_r_dagc2_multiplier_15_8 0xA1D7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define dagc2_multiplier_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define dagc2_multiplier_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define dagc2_multiplier_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define xd_r_dagc2_right_shift_bits 0xA1D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define dagc2_right_shift_bits_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define dagc2_right_shift_bits_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define dagc2_right_shift_bits_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define xd_p_cfoe_NS_coeff1_7_0 0xA200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define cfoe_NS_coeff1_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define cfoe_NS_coeff1_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define cfoe_NS_coeff1_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define xd_p_cfoe_NS_coeff1_15_8 0xA201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define cfoe_NS_coeff1_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define cfoe_NS_coeff1_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define cfoe_NS_coeff1_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define xd_p_cfoe_NS_coeff1_23_16 0xA202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define cfoe_NS_coeff1_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define cfoe_NS_coeff1_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define cfoe_NS_coeff1_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define xd_p_cfoe_NS_coeff1_25_24 0xA203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define cfoe_NS_coeff1_25_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define cfoe_NS_coeff1_25_24_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define cfoe_NS_coeff1_25_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define xd_p_cfoe_NS_coeff2_5_0 0xA203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define cfoe_NS_coeff2_5_0_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define cfoe_NS_coeff2_5_0_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define cfoe_NS_coeff2_5_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define xd_p_cfoe_NS_coeff2_13_6 0xA204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define cfoe_NS_coeff2_13_6_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define cfoe_NS_coeff2_13_6_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define cfoe_NS_coeff2_13_6_lsb 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define xd_p_cfoe_NS_coeff2_21_14 0xA205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define cfoe_NS_coeff2_21_14_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define cfoe_NS_coeff2_21_14_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define cfoe_NS_coeff2_21_14_lsb 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define xd_p_cfoe_NS_coeff2_24_22 0xA206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define cfoe_NS_coeff2_24_22_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define cfoe_NS_coeff2_24_22_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define cfoe_NS_coeff2_24_22_lsb 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define xd_p_cfoe_lf_c1_4_0 0xA206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define cfoe_lf_c1_4_0_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define cfoe_lf_c1_4_0_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define cfoe_lf_c1_4_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define xd_p_cfoe_lf_c1_12_5 0xA207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define cfoe_lf_c1_12_5_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define cfoe_lf_c1_12_5_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define cfoe_lf_c1_12_5_lsb 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define xd_p_cfoe_lf_c1_20_13 0xA208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define cfoe_lf_c1_20_13_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define cfoe_lf_c1_20_13_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define cfoe_lf_c1_20_13_lsb 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define xd_p_cfoe_lf_c1_25_21 0xA209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define cfoe_lf_c1_25_21_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define cfoe_lf_c1_25_21_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define cfoe_lf_c1_25_21_lsb 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define xd_p_cfoe_lf_c2_2_0 0xA209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define cfoe_lf_c2_2_0_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define cfoe_lf_c2_2_0_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define cfoe_lf_c2_2_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define xd_p_cfoe_lf_c2_10_3 0xA20A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define cfoe_lf_c2_10_3_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define cfoe_lf_c2_10_3_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define cfoe_lf_c2_10_3_lsb 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define xd_p_cfoe_lf_c2_18_11 0xA20B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define cfoe_lf_c2_18_11_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define cfoe_lf_c2_18_11_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define cfoe_lf_c2_18_11_lsb 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #define xd_p_cfoe_lf_c2_25_19 0xA20C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define cfoe_lf_c2_25_19_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define cfoe_lf_c2_25_19_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define cfoe_lf_c2_25_19_lsb 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define xd_p_cfoe_ifod_7_0 0xA20D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define cfoe_ifod_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define cfoe_ifod_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define cfoe_ifod_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define xd_p_cfoe_ifod_10_8 0xA20E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define cfoe_ifod_10_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define cfoe_ifod_10_8_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define cfoe_ifod_10_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define xd_p_cfoe_Divg_ctr_th 0xA20E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define cfoe_Divg_ctr_th_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define cfoe_Divg_ctr_th_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define cfoe_Divg_ctr_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define xd_p_cfoe_FOT_divg_th 0xA20F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define cfoe_FOT_divg_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define cfoe_FOT_divg_th_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define cfoe_FOT_divg_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define xd_p_cfoe_FOT_cnvg_th 0xA210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define cfoe_FOT_cnvg_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define cfoe_FOT_cnvg_th_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define cfoe_FOT_cnvg_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define xd_p_reg_cfoe_offset_7_0 0xA211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define reg_cfoe_offset_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define reg_cfoe_offset_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define reg_cfoe_offset_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define xd_p_reg_cfoe_offset_9_8 0xA212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define reg_cfoe_offset_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define reg_cfoe_offset_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define reg_cfoe_offset_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define xd_p_reg_cfoe_ifoe_sign_corr 0xA212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define reg_cfoe_ifoe_sign_corr_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define reg_cfoe_ifoe_sign_corr_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define reg_cfoe_ifoe_sign_corr_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #define xd_r_cfoe_fot_LF_output_7_0 0xA218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define cfoe_fot_LF_output_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define cfoe_fot_LF_output_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define cfoe_fot_LF_output_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define xd_r_cfoe_fot_LF_output_15_8 0xA219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define cfoe_fot_LF_output_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define cfoe_fot_LF_output_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define cfoe_fot_LF_output_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define xd_r_cfoe_ifo_metric_7_0 0xA21A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #define cfoe_ifo_metric_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define cfoe_ifo_metric_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define cfoe_ifo_metric_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define xd_r_cfoe_ifo_metric_15_8 0xA21B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define cfoe_ifo_metric_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define cfoe_ifo_metric_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define cfoe_ifo_metric_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define xd_r_cfoe_ifo_metric_23_16 0xA21C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define cfoe_ifo_metric_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define cfoe_ifo_metric_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define cfoe_ifo_metric_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define xd_p_ste_Nu 0xA220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define ste_Nu_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define ste_Nu_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define ste_Nu_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define xd_p_ste_GI 0xA220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define ste_GI_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define ste_GI_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define ste_GI_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define xd_p_ste_symbol_num 0xA221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define ste_symbol_num_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define ste_symbol_num_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define ste_symbol_num_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define xd_p_ste_sample_num 0xA221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define ste_sample_num_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define ste_sample_num_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define ste_sample_num_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define xd_p_reg_ste_buf_en 0xA221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define reg_ste_buf_en_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) #define reg_ste_buf_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #define reg_ste_buf_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define xd_p_ste_FFT_offset_7_0 0xA222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define ste_FFT_offset_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define ste_FFT_offset_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define ste_FFT_offset_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define xd_p_ste_FFT_offset_11_8 0xA223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define ste_FFT_offset_11_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define ste_FFT_offset_11_8_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define ste_FFT_offset_11_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define xd_p_reg_ste_tstmod 0xA223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define reg_ste_tstmod_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define reg_ste_tstmod_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define reg_ste_tstmod_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) #define xd_p_ste_adv_start_7_0 0xA224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #define ste_adv_start_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define ste_adv_start_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define ste_adv_start_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define xd_p_ste_adv_start_10_8 0xA225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define ste_adv_start_10_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define ste_adv_start_10_8_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define ste_adv_start_10_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define xd_p_ste_adv_stop 0xA226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define ste_adv_stop_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define ste_adv_stop_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define ste_adv_stop_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define xd_r_ste_P_value_7_0 0xA228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define ste_P_value_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define ste_P_value_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define ste_P_value_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define xd_r_ste_P_value_10_8 0xA229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define ste_P_value_10_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define ste_P_value_10_8_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #define ste_P_value_10_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define xd_r_ste_M_value_7_0 0xA22A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define ste_M_value_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define ste_M_value_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define ste_M_value_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define xd_r_ste_M_value_10_8 0xA22B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define ste_M_value_10_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define ste_M_value_10_8_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define ste_M_value_10_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #define xd_r_ste_H1 0xA22C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define ste_H1_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define ste_H1_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define ste_H1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define xd_r_ste_H2 0xA22D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define ste_H2_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define ste_H2_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define ste_H2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define xd_r_ste_H3 0xA22E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define ste_H3_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define ste_H3_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define ste_H3_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define xd_r_ste_H4 0xA22F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define ste_H4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define ste_H4_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define ste_H4_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define xd_r_ste_Corr_value_I_7_0 0xA230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define ste_Corr_value_I_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define ste_Corr_value_I_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define ste_Corr_value_I_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define xd_r_ste_Corr_value_I_15_8 0xA231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define ste_Corr_value_I_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define ste_Corr_value_I_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define ste_Corr_value_I_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define xd_r_ste_Corr_value_I_23_16 0xA232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define ste_Corr_value_I_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #define ste_Corr_value_I_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define ste_Corr_value_I_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define xd_r_ste_Corr_value_I_27_24 0xA233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #define ste_Corr_value_I_27_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #define ste_Corr_value_I_27_24_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define ste_Corr_value_I_27_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define xd_r_ste_Corr_value_Q_7_0 0xA234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define ste_Corr_value_Q_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define ste_Corr_value_Q_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define ste_Corr_value_Q_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define xd_r_ste_Corr_value_Q_15_8 0xA235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define ste_Corr_value_Q_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define ste_Corr_value_Q_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define ste_Corr_value_Q_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define xd_r_ste_Corr_value_Q_23_16 0xA236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define ste_Corr_value_Q_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define ste_Corr_value_Q_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define ste_Corr_value_Q_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define xd_r_ste_Corr_value_Q_27_24 0xA237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define ste_Corr_value_Q_27_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define ste_Corr_value_Q_27_24_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define ste_Corr_value_Q_27_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define xd_r_ste_J_num_7_0 0xA238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define ste_J_num_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define ste_J_num_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define ste_J_num_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define xd_r_ste_J_num_15_8 0xA239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define ste_J_num_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define ste_J_num_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define ste_J_num_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #define xd_r_ste_J_num_23_16 0xA23A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define ste_J_num_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define ste_J_num_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define ste_J_num_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define xd_r_ste_J_num_31_24 0xA23B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define ste_J_num_31_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #define ste_J_num_31_24_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define ste_J_num_31_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define xd_r_ste_J_den_7_0 0xA23C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #define ste_J_den_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define ste_J_den_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #define ste_J_den_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define xd_r_ste_J_den_15_8 0xA23D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #define ste_J_den_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) #define ste_J_den_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #define ste_J_den_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) #define xd_r_ste_J_den_18_16 0xA23E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #define ste_J_den_18_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) #define ste_J_den_18_16_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define ste_J_den_18_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #define xd_r_ste_Beacon_Indicator 0xA23E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) #define ste_Beacon_Indicator_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #define ste_Beacon_Indicator_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) #define ste_Beacon_Indicator_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #define xd_r_tpsd_Frame_Num 0xA250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define tpsd_Frame_Num_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #define tpsd_Frame_Num_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #define tpsd_Frame_Num_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define xd_r_tpsd_Constel 0xA250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define tpsd_Constel_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) #define tpsd_Constel_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #define tpsd_Constel_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #define xd_r_tpsd_GI 0xA250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) #define tpsd_GI_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #define tpsd_GI_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) #define tpsd_GI_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #define xd_r_tpsd_Mode 0xA250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) #define tpsd_Mode_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) #define tpsd_Mode_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #define tpsd_Mode_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) #define xd_r_tpsd_CR_HP 0xA251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) #define tpsd_CR_HP_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) #define tpsd_CR_HP_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #define tpsd_CR_HP_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define xd_r_tpsd_CR_LP 0xA251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) #define tpsd_CR_LP_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #define tpsd_CR_LP_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) #define tpsd_CR_LP_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define xd_r_tpsd_Hie 0xA252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #define tpsd_Hie_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #define tpsd_Hie_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define tpsd_Hie_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #define xd_r_tpsd_Res_Bits 0xA252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #define tpsd_Res_Bits_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) #define tpsd_Res_Bits_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #define tpsd_Res_Bits_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #define xd_r_tpsd_Res_Bits_0 0xA253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #define tpsd_Res_Bits_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #define tpsd_Res_Bits_0_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #define tpsd_Res_Bits_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #define xd_r_tpsd_LengthInd 0xA253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #define tpsd_LengthInd_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #define tpsd_LengthInd_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define tpsd_LengthInd_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #define xd_r_tpsd_Cell_Id_7_0 0xA254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) #define tpsd_Cell_Id_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #define tpsd_Cell_Id_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define tpsd_Cell_Id_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define xd_r_tpsd_Cell_Id_15_8 0xA255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #define tpsd_Cell_Id_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) #define tpsd_Cell_Id_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define tpsd_Cell_Id_15_8_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #define xd_p_reg_fft_mask_tone0_7_0 0xA260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define reg_fft_mask_tone0_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #define reg_fft_mask_tone0_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define reg_fft_mask_tone0_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define xd_p_reg_fft_mask_tone0_12_8 0xA261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define reg_fft_mask_tone0_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define reg_fft_mask_tone0_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define reg_fft_mask_tone0_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define xd_p_reg_fft_mask_tone1_7_0 0xA262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define reg_fft_mask_tone1_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define reg_fft_mask_tone1_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define reg_fft_mask_tone1_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define xd_p_reg_fft_mask_tone1_12_8 0xA263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define reg_fft_mask_tone1_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define reg_fft_mask_tone1_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define reg_fft_mask_tone1_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #define xd_p_reg_fft_mask_tone2_7_0 0xA264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define reg_fft_mask_tone2_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define reg_fft_mask_tone2_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #define reg_fft_mask_tone2_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #define xd_p_reg_fft_mask_tone2_12_8 0xA265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #define reg_fft_mask_tone2_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define reg_fft_mask_tone2_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #define reg_fft_mask_tone2_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #define xd_p_reg_fft_mask_tone3_7_0 0xA266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define reg_fft_mask_tone3_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #define reg_fft_mask_tone3_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #define reg_fft_mask_tone3_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define xd_p_reg_fft_mask_tone3_12_8 0xA267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define reg_fft_mask_tone3_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define reg_fft_mask_tone3_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) #define reg_fft_mask_tone3_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #define xd_p_reg_fft_mask_from0_7_0 0xA268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #define reg_fft_mask_from0_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #define reg_fft_mask_from0_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define reg_fft_mask_from0_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #define xd_p_reg_fft_mask_from0_12_8 0xA269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) #define reg_fft_mask_from0_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #define reg_fft_mask_from0_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define reg_fft_mask_from0_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define xd_p_reg_fft_mask_to0_7_0 0xA26A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define reg_fft_mask_to0_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) #define reg_fft_mask_to0_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #define reg_fft_mask_to0_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #define xd_p_reg_fft_mask_to0_12_8 0xA26B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #define reg_fft_mask_to0_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) #define reg_fft_mask_to0_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #define reg_fft_mask_to0_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #define xd_p_reg_fft_mask_from1_7_0 0xA26C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) #define reg_fft_mask_from1_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) #define reg_fft_mask_from1_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) #define reg_fft_mask_from1_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) #define xd_p_reg_fft_mask_from1_12_8 0xA26D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #define reg_fft_mask_from1_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) #define reg_fft_mask_from1_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) #define reg_fft_mask_from1_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) #define xd_p_reg_fft_mask_to1_7_0 0xA26E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #define reg_fft_mask_to1_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) #define reg_fft_mask_to1_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define reg_fft_mask_to1_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #define xd_p_reg_fft_mask_to1_12_8 0xA26F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #define reg_fft_mask_to1_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) #define reg_fft_mask_to1_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #define reg_fft_mask_to1_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) #define xd_p_reg_cge_idx0_7_0 0xA280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define reg_cge_idx0_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define reg_cge_idx0_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #define reg_cge_idx0_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define xd_p_reg_cge_idx0_12_8 0xA281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #define reg_cge_idx0_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #define reg_cge_idx0_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) #define reg_cge_idx0_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) #define xd_p_reg_cge_idx1_7_0 0xA282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) #define reg_cge_idx1_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) #define reg_cge_idx1_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) #define reg_cge_idx1_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) #define xd_p_reg_cge_idx1_12_8 0xA283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) #define reg_cge_idx1_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define reg_cge_idx1_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) #define reg_cge_idx1_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) #define xd_p_reg_cge_idx2_7_0 0xA284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) #define reg_cge_idx2_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #define reg_cge_idx2_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) #define reg_cge_idx2_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #define xd_p_reg_cge_idx2_12_8 0xA285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) #define reg_cge_idx2_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #define reg_cge_idx2_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) #define reg_cge_idx2_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) #define xd_p_reg_cge_idx3_7_0 0xA286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #define reg_cge_idx3_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #define reg_cge_idx3_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) #define reg_cge_idx3_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) #define xd_p_reg_cge_idx3_12_8 0xA287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) #define reg_cge_idx3_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) #define reg_cge_idx3_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #define reg_cge_idx3_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #define xd_p_reg_cge_idx4_7_0 0xA288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) #define reg_cge_idx4_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) #define reg_cge_idx4_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #define reg_cge_idx4_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #define xd_p_reg_cge_idx4_12_8 0xA289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #define reg_cge_idx4_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) #define reg_cge_idx4_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) #define reg_cge_idx4_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) #define xd_p_reg_cge_idx5_7_0 0xA28A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) #define reg_cge_idx5_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) #define reg_cge_idx5_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) #define reg_cge_idx5_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #define xd_p_reg_cge_idx5_12_8 0xA28B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) #define reg_cge_idx5_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) #define reg_cge_idx5_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #define reg_cge_idx5_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) #define xd_p_reg_cge_idx6_7_0 0xA28C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) #define reg_cge_idx6_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #define reg_cge_idx6_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define reg_cge_idx6_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define xd_p_reg_cge_idx6_12_8 0xA28D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #define reg_cge_idx6_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #define reg_cge_idx6_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #define reg_cge_idx6_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #define xd_p_reg_cge_idx7_7_0 0xA28E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) #define reg_cge_idx7_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #define reg_cge_idx7_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define reg_cge_idx7_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) #define xd_p_reg_cge_idx7_12_8 0xA28F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) #define reg_cge_idx7_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) #define reg_cge_idx7_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) #define reg_cge_idx7_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) #define xd_p_reg_cge_idx8_7_0 0xA290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #define reg_cge_idx8_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) #define reg_cge_idx8_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) #define reg_cge_idx8_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #define xd_p_reg_cge_idx8_12_8 0xA291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) #define reg_cge_idx8_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) #define reg_cge_idx8_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) #define reg_cge_idx8_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) #define xd_p_reg_cge_idx9_7_0 0xA292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) #define reg_cge_idx9_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #define reg_cge_idx9_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) #define reg_cge_idx9_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #define xd_p_reg_cge_idx9_12_8 0xA293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) #define reg_cge_idx9_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) #define reg_cge_idx9_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #define reg_cge_idx9_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #define xd_p_reg_cge_idx10_7_0 0xA294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #define reg_cge_idx10_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #define reg_cge_idx10_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) #define reg_cge_idx10_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) #define xd_p_reg_cge_idx10_12_8 0xA295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) #define reg_cge_idx10_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #define reg_cge_idx10_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #define reg_cge_idx10_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #define xd_p_reg_cge_idx11_7_0 0xA296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) #define reg_cge_idx11_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) #define reg_cge_idx11_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) #define reg_cge_idx11_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #define xd_p_reg_cge_idx11_12_8 0xA297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #define reg_cge_idx11_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define reg_cge_idx11_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define reg_cge_idx11_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #define xd_p_reg_cge_idx12_7_0 0xA298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #define reg_cge_idx12_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #define reg_cge_idx12_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) #define reg_cge_idx12_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #define xd_p_reg_cge_idx12_12_8 0xA299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define reg_cge_idx12_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #define reg_cge_idx12_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #define reg_cge_idx12_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) #define xd_p_reg_cge_idx13_7_0 0xA29A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #define reg_cge_idx13_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define reg_cge_idx13_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #define reg_cge_idx13_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #define xd_p_reg_cge_idx13_12_8 0xA29B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define reg_cge_idx13_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define reg_cge_idx13_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define reg_cge_idx13_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define xd_p_reg_cge_idx14_7_0 0xA29C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define reg_cge_idx14_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define reg_cge_idx14_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #define reg_cge_idx14_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #define xd_p_reg_cge_idx14_12_8 0xA29D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #define reg_cge_idx14_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define reg_cge_idx14_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #define reg_cge_idx14_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define xd_p_reg_cge_idx15_7_0 0xA29E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define reg_cge_idx15_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #define reg_cge_idx15_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #define reg_cge_idx15_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #define xd_p_reg_cge_idx15_12_8 0xA29F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #define reg_cge_idx15_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #define reg_cge_idx15_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #define reg_cge_idx15_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) #define xd_r_reg_fft_crc 0xA2A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) #define reg_fft_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) #define reg_fft_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #define reg_fft_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) #define xd_p_fd_fft_shift_max 0xA2A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #define fd_fft_shift_max_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #define fd_fft_shift_max_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) #define fd_fft_shift_max_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define xd_r_fd_fft_shift 0xA2A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #define fd_fft_shift_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define fd_fft_shift_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #define fd_fft_shift_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #define xd_r_fd_fft_frame_num 0xA2AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) #define fd_fft_frame_num_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #define fd_fft_frame_num_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) #define fd_fft_frame_num_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) #define xd_r_fd_fft_symbol_count 0xA2AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) #define fd_fft_symbol_count_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #define fd_fft_symbol_count_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) #define fd_fft_symbol_count_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) #define xd_r_reg_fft_idx_max_7_0 0xA2AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) #define reg_fft_idx_max_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #define reg_fft_idx_max_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define reg_fft_idx_max_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define xd_r_reg_fft_idx_max_12_8 0xA2AD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #define reg_fft_idx_max_12_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) #define reg_fft_idx_max_12_8_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) #define reg_fft_idx_max_12_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #define xd_p_reg_cge_program 0xA2AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) #define reg_cge_program_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #define reg_cge_program_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) #define reg_cge_program_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) #define xd_p_reg_cge_fixed 0xA2AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #define reg_cge_fixed_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) #define reg_cge_fixed_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) #define reg_cge_fixed_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #define xd_p_reg_fft_rotate_en 0xA2AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #define reg_fft_rotate_en_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #define reg_fft_rotate_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) #define reg_fft_rotate_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #define xd_p_reg_fft_rotate_base_4_0 0xA2AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) #define reg_fft_rotate_base_4_0_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) #define reg_fft_rotate_base_4_0_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) #define reg_fft_rotate_base_4_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #define xd_p_reg_fft_rotate_base_12_5 0xA2AF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #define reg_fft_rotate_base_12_5_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) #define reg_fft_rotate_base_12_5_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #define reg_fft_rotate_base_12_5_lsb 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) #define xd_p_reg_gp_trigger_fd 0xA2B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) #define reg_gp_trigger_fd_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) #define reg_gp_trigger_fd_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) #define reg_gp_trigger_fd_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define xd_p_reg_trigger_sel_fd 0xA2B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #define reg_trigger_sel_fd_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define reg_trigger_sel_fd_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) #define reg_trigger_sel_fd_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #define xd_p_reg_trigger_module_sel_fd 0xA2B9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) #define reg_trigger_module_sel_fd_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define reg_trigger_module_sel_fd_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) #define reg_trigger_module_sel_fd_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #define xd_p_reg_trigger_set_sel_fd 0xA2BA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) #define reg_trigger_set_sel_fd_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #define reg_trigger_set_sel_fd_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define reg_trigger_set_sel_fd_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #define xd_p_reg_fd_noname_7_0 0xA2BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #define reg_fd_noname_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #define reg_fd_noname_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) #define reg_fd_noname_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #define xd_p_reg_fd_noname_15_8 0xA2BD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) #define reg_fd_noname_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) #define reg_fd_noname_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define reg_fd_noname_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #define xd_p_reg_fd_noname_23_16 0xA2BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define reg_fd_noname_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #define reg_fd_noname_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #define reg_fd_noname_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #define xd_p_reg_fd_noname_31_24 0xA2BF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #define reg_fd_noname_31_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) #define reg_fd_noname_31_24_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) #define reg_fd_noname_31_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) #define xd_r_fd_fpcc_cp_corr_signn 0xA2C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) #define fd_fpcc_cp_corr_signn_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #define fd_fpcc_cp_corr_signn_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #define fd_fpcc_cp_corr_signn_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) #define xd_p_reg_feq_s1 0xA2C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #define reg_feq_s1_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) #define reg_feq_s1_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #define reg_feq_s1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #define xd_p_fd_fpcc_cp_corr_tone_th 0xA2C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) #define fd_fpcc_cp_corr_tone_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define fd_fpcc_cp_corr_tone_th_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #define fd_fpcc_cp_corr_tone_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #define xd_p_fd_fpcc_cp_corr_symbol_log_th 0xA2C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) #define fd_fpcc_cp_corr_symbol_log_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #define fd_fpcc_cp_corr_symbol_log_th_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define fd_fpcc_cp_corr_symbol_log_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #define xd_p_fd_fpcc_cp_corr_int 0xA2C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define fd_fpcc_cp_corr_int_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) #define fd_fpcc_cp_corr_int_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #define fd_fpcc_cp_corr_int_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) #define xd_p_reg_sfoe_ns_7_0 0xA320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) #define reg_sfoe_ns_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #define reg_sfoe_ns_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) #define reg_sfoe_ns_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) #define xd_p_reg_sfoe_ns_14_8 0xA321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) #define reg_sfoe_ns_14_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) #define reg_sfoe_ns_14_8_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) #define reg_sfoe_ns_14_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) #define xd_p_reg_sfoe_c1_7_0 0xA322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) #define reg_sfoe_c1_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) #define reg_sfoe_c1_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #define reg_sfoe_c1_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) #define xd_p_reg_sfoe_c1_15_8 0xA323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) #define reg_sfoe_c1_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) #define reg_sfoe_c1_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define reg_sfoe_c1_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) #define xd_p_reg_sfoe_c1_17_16 0xA324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) #define reg_sfoe_c1_17_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) #define reg_sfoe_c1_17_16_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #define reg_sfoe_c1_17_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) #define xd_p_reg_sfoe_c2_7_0 0xA325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) #define reg_sfoe_c2_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) #define reg_sfoe_c2_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) #define reg_sfoe_c2_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #define xd_p_reg_sfoe_c2_15_8 0xA326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) #define reg_sfoe_c2_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) #define reg_sfoe_c2_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) #define reg_sfoe_c2_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) #define xd_p_reg_sfoe_c2_17_16 0xA327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) #define reg_sfoe_c2_17_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) #define reg_sfoe_c2_17_16_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) #define reg_sfoe_c2_17_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) #define xd_r_reg_sfoe_out_9_2 0xA328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) #define reg_sfoe_out_9_2_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #define reg_sfoe_out_9_2_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) #define reg_sfoe_out_9_2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) #define xd_r_reg_sfoe_out_1_0 0xA329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) #define reg_sfoe_out_1_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) #define reg_sfoe_out_1_0_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #define reg_sfoe_out_1_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) #define xd_p_reg_sfoe_lm_counter_th 0xA32A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) #define reg_sfoe_lm_counter_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) #define reg_sfoe_lm_counter_th_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) #define reg_sfoe_lm_counter_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) #define xd_p_reg_sfoe_convg_th 0xA32B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) #define reg_sfoe_convg_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) #define reg_sfoe_convg_th_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #define reg_sfoe_convg_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) #define xd_p_reg_sfoe_divg_th 0xA32C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) #define reg_sfoe_divg_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) #define reg_sfoe_divg_th_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) #define reg_sfoe_divg_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #define xd_p_fd_tpsd_en 0xA330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) #define fd_tpsd_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #define fd_tpsd_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define fd_tpsd_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #define xd_p_fd_tpsd_dis 0xA330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) #define fd_tpsd_dis_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) #define fd_tpsd_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define fd_tpsd_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define xd_p_fd_tpsd_rst 0xA330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define fd_tpsd_rst_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define fd_tpsd_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define fd_tpsd_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) #define xd_p_fd_tpsd_lock 0xA330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) #define fd_tpsd_lock_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) #define fd_tpsd_lock_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #define fd_tpsd_lock_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) #define xd_r_fd_tpsd_s19 0xA330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #define fd_tpsd_s19_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define fd_tpsd_s19_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #define fd_tpsd_s19_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) #define xd_r_fd_tpsd_s17 0xA330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) #define fd_tpsd_s17_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) #define fd_tpsd_s17_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) #define fd_tpsd_s17_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) #define xd_p_fd_sfr_ste_en 0xA331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) #define fd_sfr_ste_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) #define fd_sfr_ste_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) #define fd_sfr_ste_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) #define xd_p_fd_sfr_ste_dis 0xA331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #define fd_sfr_ste_dis_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) #define fd_sfr_ste_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #define fd_sfr_ste_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #define xd_p_fd_sfr_ste_rst 0xA331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) #define fd_sfr_ste_rst_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #define fd_sfr_ste_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) #define fd_sfr_ste_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) #define xd_p_fd_sfr_ste_mode 0xA331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) #define fd_sfr_ste_mode_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #define fd_sfr_ste_mode_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #define fd_sfr_ste_mode_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #define xd_p_fd_sfr_ste_done 0xA331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) #define fd_sfr_ste_done_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #define fd_sfr_ste_done_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) #define fd_sfr_ste_done_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #define xd_p_reg_cfoe_ffoe_en 0xA332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) #define reg_cfoe_ffoe_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #define reg_cfoe_ffoe_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) #define reg_cfoe_ffoe_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #define xd_p_reg_cfoe_ffoe_dis 0xA332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) #define reg_cfoe_ffoe_dis_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #define reg_cfoe_ffoe_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) #define reg_cfoe_ffoe_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #define xd_p_reg_cfoe_ffoe_rst 0xA332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) #define reg_cfoe_ffoe_rst_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) #define reg_cfoe_ffoe_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) #define reg_cfoe_ffoe_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #define xd_p_reg_cfoe_ifoe_en 0xA332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) #define reg_cfoe_ifoe_en_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) #define reg_cfoe_ifoe_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) #define reg_cfoe_ifoe_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) #define xd_p_reg_cfoe_ifoe_dis 0xA332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) #define reg_cfoe_ifoe_dis_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) #define reg_cfoe_ifoe_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) #define reg_cfoe_ifoe_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) #define xd_p_reg_cfoe_ifoe_rst 0xA332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) #define reg_cfoe_ifoe_rst_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) #define reg_cfoe_ifoe_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) #define reg_cfoe_ifoe_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) #define xd_p_reg_cfoe_fot_en 0xA332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) #define reg_cfoe_fot_en_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) #define reg_cfoe_fot_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) #define reg_cfoe_fot_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) #define xd_p_reg_cfoe_fot_lm_en 0xA332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) #define reg_cfoe_fot_lm_en_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) #define reg_cfoe_fot_lm_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) #define reg_cfoe_fot_lm_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) #define xd_p_reg_cfoe_fot_rst 0xA333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) #define reg_cfoe_fot_rst_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) #define reg_cfoe_fot_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) #define reg_cfoe_fot_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) #define xd_r_fd_cfoe_ffoe_done 0xA333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) #define fd_cfoe_ffoe_done_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) #define fd_cfoe_ffoe_done_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) #define fd_cfoe_ffoe_done_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) #define xd_p_fd_cfoe_metric_vld 0xA333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) #define fd_cfoe_metric_vld_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) #define fd_cfoe_metric_vld_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) #define fd_cfoe_metric_vld_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) #define xd_p_reg_cfoe_ifod_vld 0xA333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) #define reg_cfoe_ifod_vld_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) #define reg_cfoe_ifod_vld_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) #define reg_cfoe_ifod_vld_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #define xd_r_fd_cfoe_ifoe_done 0xA333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) #define fd_cfoe_ifoe_done_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) #define fd_cfoe_ifoe_done_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) #define fd_cfoe_ifoe_done_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) #define xd_r_fd_cfoe_fot_valid 0xA333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) #define fd_cfoe_fot_valid_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) #define fd_cfoe_fot_valid_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) #define fd_cfoe_fot_valid_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) #define xd_p_reg_cfoe_divg_int 0xA333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) #define reg_cfoe_divg_int_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) #define reg_cfoe_divg_int_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) #define reg_cfoe_divg_int_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #define xd_r_reg_cfoe_divg_flag 0xA333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) #define reg_cfoe_divg_flag_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) #define reg_cfoe_divg_flag_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) #define reg_cfoe_divg_flag_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) #define xd_p_reg_sfoe_en 0xA334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) #define reg_sfoe_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #define reg_sfoe_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #define reg_sfoe_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) #define xd_p_reg_sfoe_dis 0xA334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) #define reg_sfoe_dis_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) #define reg_sfoe_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) #define reg_sfoe_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) #define xd_p_reg_sfoe_rst 0xA334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) #define reg_sfoe_rst_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) #define reg_sfoe_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) #define reg_sfoe_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) #define xd_p_reg_sfoe_vld_int 0xA334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) #define reg_sfoe_vld_int_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) #define reg_sfoe_vld_int_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) #define reg_sfoe_vld_int_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) #define xd_p_reg_sfoe_lm_en 0xA334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) #define reg_sfoe_lm_en_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) #define reg_sfoe_lm_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) #define reg_sfoe_lm_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) #define xd_p_reg_sfoe_divg_int 0xA334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) #define reg_sfoe_divg_int_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) #define reg_sfoe_divg_int_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) #define reg_sfoe_divg_int_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) #define xd_r_reg_sfoe_divg_flag 0xA334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) #define reg_sfoe_divg_flag_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #define reg_sfoe_divg_flag_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #define reg_sfoe_divg_flag_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #define xd_p_reg_fft_rst 0xA335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #define reg_fft_rst_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #define reg_fft_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #define reg_fft_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) #define xd_p_reg_fft_fast_beacon 0xA335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) #define reg_fft_fast_beacon_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #define reg_fft_fast_beacon_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) #define reg_fft_fast_beacon_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) #define xd_p_reg_fft_fast_valid 0xA335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #define reg_fft_fast_valid_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) #define reg_fft_fast_valid_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) #define reg_fft_fast_valid_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) #define xd_p_reg_fft_mask_en 0xA335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) #define reg_fft_mask_en_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) #define reg_fft_mask_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) #define reg_fft_mask_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) #define xd_p_reg_fft_crc_en 0xA335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) #define reg_fft_crc_en_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) #define reg_fft_crc_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) #define reg_fft_crc_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) #define xd_p_reg_finr_en 0xA336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) #define reg_finr_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) #define reg_finr_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) #define reg_finr_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) #define xd_p_fd_fste_en 0xA337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) #define fd_fste_en_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) #define fd_fste_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) #define fd_fste_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) #define xd_p_fd_sqi_tps_level_shift 0xA338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) #define fd_sqi_tps_level_shift_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #define fd_sqi_tps_level_shift_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) #define fd_sqi_tps_level_shift_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) #define xd_p_fd_pilot_ma_len 0xA339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) #define fd_pilot_ma_len_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #define fd_pilot_ma_len_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) #define fd_pilot_ma_len_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) #define xd_p_fd_tps_ma_len 0xA33A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) #define fd_tps_ma_len_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) #define fd_tps_ma_len_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) #define fd_tps_ma_len_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) #define xd_p_fd_sqi_s3 0xA33B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) #define fd_sqi_s3_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) #define fd_sqi_s3_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) #define fd_sqi_s3_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) #define xd_p_fd_sqi_dummy_reg_0 0xA33C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) #define fd_sqi_dummy_reg_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) #define fd_sqi_dummy_reg_0_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) #define fd_sqi_dummy_reg_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) #define xd_p_fd_sqi_debug_sel 0xA33C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) #define fd_sqi_debug_sel_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) #define fd_sqi_debug_sel_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) #define fd_sqi_debug_sel_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) #define xd_p_fd_sqi_s2 0xA33C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) #define fd_sqi_s2_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) #define fd_sqi_s2_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) #define fd_sqi_s2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) #define xd_p_fd_sqi_dummy_reg_1 0xA33D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) #define fd_sqi_dummy_reg_1_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) #define fd_sqi_dummy_reg_1_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) #define fd_sqi_dummy_reg_1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) #define xd_p_fd_inr_ignore 0xA33D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) #define fd_inr_ignore_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) #define fd_inr_ignore_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) #define fd_inr_ignore_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) #define xd_p_fd_pilot_ignore 0xA33D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) #define fd_pilot_ignore_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) #define fd_pilot_ignore_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) #define fd_pilot_ignore_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) #define xd_p_fd_etps_ignore 0xA33D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) #define fd_etps_ignore_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) #define fd_etps_ignore_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) #define fd_etps_ignore_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) #define xd_p_fd_sqi_s1 0xA33D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) #define fd_sqi_s1_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) #define fd_sqi_s1_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) #define fd_sqi_s1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) #define xd_p_reg_fste_ehw_7_0 0xA33E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) #define reg_fste_ehw_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) #define reg_fste_ehw_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) #define reg_fste_ehw_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) #define xd_p_reg_fste_ehw_9_8 0xA33F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) #define reg_fste_ehw_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) #define reg_fste_ehw_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) #define reg_fste_ehw_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) #define xd_p_reg_fste_i_adj_vld 0xA33F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) #define reg_fste_i_adj_vld_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) #define reg_fste_i_adj_vld_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) #define reg_fste_i_adj_vld_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) #define xd_p_reg_fste_phase_ini_7_0 0xA340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) #define reg_fste_phase_ini_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) #define reg_fste_phase_ini_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) #define reg_fste_phase_ini_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) #define xd_p_reg_fste_phase_ini_11_8 0xA341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) #define reg_fste_phase_ini_11_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) #define reg_fste_phase_ini_11_8_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) #define reg_fste_phase_ini_11_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) #define xd_p_reg_fste_phase_inc_3_0 0xA341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) #define reg_fste_phase_inc_3_0_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) #define reg_fste_phase_inc_3_0_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) #define reg_fste_phase_inc_3_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) #define xd_p_reg_fste_phase_inc_11_4 0xA342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) #define reg_fste_phase_inc_11_4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) #define reg_fste_phase_inc_11_4_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) #define reg_fste_phase_inc_11_4_lsb 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) #define xd_p_reg_fste_acum_cost_cnt_max 0xA343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) #define reg_fste_acum_cost_cnt_max_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) #define reg_fste_acum_cost_cnt_max_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) #define reg_fste_acum_cost_cnt_max_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) #define xd_p_reg_fste_step_size_std 0xA343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) #define reg_fste_step_size_std_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) #define reg_fste_step_size_std_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) #define reg_fste_step_size_std_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) #define xd_p_reg_fste_step_size_max 0xA344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) #define reg_fste_step_size_max_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) #define reg_fste_step_size_max_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) #define reg_fste_step_size_max_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) #define xd_p_reg_fste_step_size_min 0xA344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) #define reg_fste_step_size_min_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) #define reg_fste_step_size_min_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) #define reg_fste_step_size_min_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) #define xd_p_reg_fste_frac_step_size_7_0 0xA345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) #define reg_fste_frac_step_size_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) #define reg_fste_frac_step_size_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) #define reg_fste_frac_step_size_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) #define xd_p_reg_fste_frac_step_size_15_8 0xA346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) #define reg_fste_frac_step_size_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) #define reg_fste_frac_step_size_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) #define reg_fste_frac_step_size_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) #define xd_p_reg_fste_frac_step_size_19_16 0xA347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) #define reg_fste_frac_step_size_19_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) #define reg_fste_frac_step_size_19_16_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) #define reg_fste_frac_step_size_19_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) #define xd_p_reg_fste_rpd_dir_cnt_max 0xA347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) #define reg_fste_rpd_dir_cnt_max_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) #define reg_fste_rpd_dir_cnt_max_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) #define reg_fste_rpd_dir_cnt_max_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) #define xd_p_reg_fste_ehs 0xA348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) #define reg_fste_ehs_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) #define reg_fste_ehs_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) #define reg_fste_ehs_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) #define xd_p_reg_fste_frac_cost_cnt_max_3_0 0xA348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) #define reg_fste_frac_cost_cnt_max_3_0_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) #define reg_fste_frac_cost_cnt_max_3_0_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) #define reg_fste_frac_cost_cnt_max_3_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) #define xd_p_reg_fste_frac_cost_cnt_max_9_4 0xA349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) #define reg_fste_frac_cost_cnt_max_9_4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) #define reg_fste_frac_cost_cnt_max_9_4_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) #define reg_fste_frac_cost_cnt_max_9_4_lsb 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) #define xd_p_reg_fste_w0_7_0 0xA34A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) #define reg_fste_w0_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) #define reg_fste_w0_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) #define reg_fste_w0_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) #define xd_p_reg_fste_w0_11_8 0xA34B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) #define reg_fste_w0_11_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) #define reg_fste_w0_11_8_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) #define reg_fste_w0_11_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) #define xd_p_reg_fste_w1_3_0 0xA34B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) #define reg_fste_w1_3_0_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) #define reg_fste_w1_3_0_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) #define reg_fste_w1_3_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) #define xd_p_reg_fste_w1_11_4 0xA34C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) #define reg_fste_w1_11_4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) #define reg_fste_w1_11_4_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) #define reg_fste_w1_11_4_lsb 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) #define xd_p_reg_fste_w2_7_0 0xA34D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) #define reg_fste_w2_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) #define reg_fste_w2_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) #define reg_fste_w2_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) #define xd_p_reg_fste_w2_11_8 0xA34E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) #define reg_fste_w2_11_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) #define reg_fste_w2_11_8_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) #define reg_fste_w2_11_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) #define xd_p_reg_fste_w3_3_0 0xA34E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) #define reg_fste_w3_3_0_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) #define reg_fste_w3_3_0_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) #define reg_fste_w3_3_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) #define xd_p_reg_fste_w3_11_4 0xA34F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) #define reg_fste_w3_11_4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) #define reg_fste_w3_11_4_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) #define reg_fste_w3_11_4_lsb 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) #define xd_p_reg_fste_w4_7_0 0xA350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) #define reg_fste_w4_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) #define reg_fste_w4_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) #define reg_fste_w4_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) #define xd_p_reg_fste_w4_11_8 0xA351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) #define reg_fste_w4_11_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) #define reg_fste_w4_11_8_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) #define reg_fste_w4_11_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) #define xd_p_reg_fste_w5_3_0 0xA351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) #define reg_fste_w5_3_0_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) #define reg_fste_w5_3_0_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) #define reg_fste_w5_3_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) #define xd_p_reg_fste_w5_11_4 0xA352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) #define reg_fste_w5_11_4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) #define reg_fste_w5_11_4_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) #define reg_fste_w5_11_4_lsb 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) #define xd_p_reg_fste_w6_7_0 0xA353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) #define reg_fste_w6_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) #define reg_fste_w6_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) #define reg_fste_w6_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) #define xd_p_reg_fste_w6_11_8 0xA354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) #define reg_fste_w6_11_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) #define reg_fste_w6_11_8_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) #define reg_fste_w6_11_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) #define xd_p_reg_fste_w7_3_0 0xA354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) #define reg_fste_w7_3_0_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) #define reg_fste_w7_3_0_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) #define reg_fste_w7_3_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) #define xd_p_reg_fste_w7_11_4 0xA355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) #define reg_fste_w7_11_4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) #define reg_fste_w7_11_4_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) #define reg_fste_w7_11_4_lsb 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) #define xd_p_reg_fste_w8_7_0 0xA356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) #define reg_fste_w8_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) #define reg_fste_w8_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) #define reg_fste_w8_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) #define xd_p_reg_fste_w8_11_8 0xA357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) #define reg_fste_w8_11_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) #define reg_fste_w8_11_8_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) #define reg_fste_w8_11_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) #define xd_p_reg_fste_w9_3_0 0xA357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) #define reg_fste_w9_3_0_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) #define reg_fste_w9_3_0_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) #define reg_fste_w9_3_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) #define xd_p_reg_fste_w9_11_4 0xA358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) #define reg_fste_w9_11_4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) #define reg_fste_w9_11_4_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) #define reg_fste_w9_11_4_lsb 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) #define xd_p_reg_fste_wa_7_0 0xA359
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) #define reg_fste_wa_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) #define reg_fste_wa_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) #define reg_fste_wa_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) #define xd_p_reg_fste_wa_11_8 0xA35A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) #define reg_fste_wa_11_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) #define reg_fste_wa_11_8_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) #define reg_fste_wa_11_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) #define xd_p_reg_fste_wb_3_0 0xA35A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) #define reg_fste_wb_3_0_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) #define reg_fste_wb_3_0_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) #define reg_fste_wb_3_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) #define xd_p_reg_fste_wb_11_4 0xA35B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) #define reg_fste_wb_11_4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) #define reg_fste_wb_11_4_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) #define reg_fste_wb_11_4_lsb 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) #define xd_r_fd_fste_i_adj 0xA35C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) #define fd_fste_i_adj_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) #define fd_fste_i_adj_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) #define fd_fste_i_adj_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) #define xd_r_fd_fste_f_adj_7_0 0xA35D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) #define fd_fste_f_adj_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) #define fd_fste_f_adj_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) #define fd_fste_f_adj_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) #define xd_r_fd_fste_f_adj_15_8 0xA35E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) #define fd_fste_f_adj_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) #define fd_fste_f_adj_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) #define fd_fste_f_adj_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) #define xd_r_fd_fste_f_adj_19_16 0xA35F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) #define fd_fste_f_adj_19_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) #define fd_fste_f_adj_19_16_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) #define fd_fste_f_adj_19_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) #define xd_p_reg_feq_Leak_Bypass 0xA366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) #define reg_feq_Leak_Bypass_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) #define reg_feq_Leak_Bypass_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) #define reg_feq_Leak_Bypass_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) #define xd_p_reg_feq_Leak_Mneg1 0xA366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) #define reg_feq_Leak_Mneg1_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) #define reg_feq_Leak_Mneg1_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) #define reg_feq_Leak_Mneg1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) #define xd_p_reg_feq_Leak_B_ShiftQ 0xA366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) #define reg_feq_Leak_B_ShiftQ_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) #define reg_feq_Leak_B_ShiftQ_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) #define reg_feq_Leak_B_ShiftQ_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) #define xd_p_reg_feq_Leak_B_Float0 0xA367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) #define reg_feq_Leak_B_Float0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) #define reg_feq_Leak_B_Float0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) #define reg_feq_Leak_B_Float0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) #define xd_p_reg_feq_Leak_B_Float1 0xA368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) #define reg_feq_Leak_B_Float1_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) #define reg_feq_Leak_B_Float1_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) #define reg_feq_Leak_B_Float1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) #define xd_p_reg_feq_Leak_B_Float2 0xA369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) #define reg_feq_Leak_B_Float2_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) #define reg_feq_Leak_B_Float2_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) #define reg_feq_Leak_B_Float2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) #define xd_p_reg_feq_Leak_B_Float3 0xA36A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) #define reg_feq_Leak_B_Float3_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) #define reg_feq_Leak_B_Float3_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) #define reg_feq_Leak_B_Float3_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) #define xd_p_reg_feq_Leak_B_Float4 0xA36B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) #define reg_feq_Leak_B_Float4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) #define reg_feq_Leak_B_Float4_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) #define reg_feq_Leak_B_Float4_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) #define xd_p_reg_feq_Leak_B_Float5 0xA36C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) #define reg_feq_Leak_B_Float5_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) #define reg_feq_Leak_B_Float5_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) #define reg_feq_Leak_B_Float5_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) #define xd_p_reg_feq_Leak_B_Float6 0xA36D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) #define reg_feq_Leak_B_Float6_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) #define reg_feq_Leak_B_Float6_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) #define reg_feq_Leak_B_Float6_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) #define xd_p_reg_feq_Leak_B_Float7 0xA36E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) #define reg_feq_Leak_B_Float7_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) #define reg_feq_Leak_B_Float7_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) #define reg_feq_Leak_B_Float7_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) #define xd_r_reg_feq_data_h2_7_0 0xA36F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) #define reg_feq_data_h2_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) #define reg_feq_data_h2_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) #define reg_feq_data_h2_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) #define xd_r_reg_feq_data_h2_9_8 0xA370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) #define reg_feq_data_h2_9_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) #define reg_feq_data_h2_9_8_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) #define reg_feq_data_h2_9_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) #define xd_p_reg_feq_leak_use_slice_tps 0xA371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) #define reg_feq_leak_use_slice_tps_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) #define reg_feq_leak_use_slice_tps_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) #define reg_feq_leak_use_slice_tps_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) #define xd_p_reg_feq_read_update 0xA371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) #define reg_feq_read_update_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) #define reg_feq_read_update_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) #define reg_feq_read_update_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) #define xd_p_reg_feq_data_vld 0xA371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) #define reg_feq_data_vld_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) #define reg_feq_data_vld_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) #define reg_feq_data_vld_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) #define xd_p_reg_feq_tone_idx_4_0 0xA371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) #define reg_feq_tone_idx_4_0_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) #define reg_feq_tone_idx_4_0_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) #define reg_feq_tone_idx_4_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) #define xd_p_reg_feq_tone_idx_12_5 0xA372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) #define reg_feq_tone_idx_12_5_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) #define reg_feq_tone_idx_12_5_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) #define reg_feq_tone_idx_12_5_lsb 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) #define xd_r_reg_feq_data_re_7_0 0xA373
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) #define reg_feq_data_re_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) #define reg_feq_data_re_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) #define reg_feq_data_re_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) #define xd_r_reg_feq_data_re_10_8 0xA374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) #define reg_feq_data_re_10_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) #define reg_feq_data_re_10_8_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) #define reg_feq_data_re_10_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) #define xd_r_reg_feq_data_im_7_0 0xA375
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) #define reg_feq_data_im_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) #define reg_feq_data_im_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) #define reg_feq_data_im_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) #define xd_r_reg_feq_data_im_10_8 0xA376
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) #define reg_feq_data_im_10_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) #define reg_feq_data_im_10_8_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) #define reg_feq_data_im_10_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) #define xd_r_reg_feq_y_re 0xA377
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) #define reg_feq_y_re_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) #define reg_feq_y_re_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) #define reg_feq_y_re_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) #define xd_r_reg_feq_y_im 0xA378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) #define reg_feq_y_im_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) #define reg_feq_y_im_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) #define reg_feq_y_im_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) #define xd_r_reg_feq_h_re_7_0 0xA379
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) #define reg_feq_h_re_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) #define reg_feq_h_re_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) #define reg_feq_h_re_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) #define xd_r_reg_feq_h_re_8 0xA37A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) #define reg_feq_h_re_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) #define reg_feq_h_re_8_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) #define reg_feq_h_re_8_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) #define xd_r_reg_feq_h_im_7_0 0xA37B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) #define reg_feq_h_im_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) #define reg_feq_h_im_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) #define reg_feq_h_im_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) #define xd_r_reg_feq_h_im_8 0xA37C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) #define reg_feq_h_im_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) #define reg_feq_h_im_8_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) #define reg_feq_h_im_8_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) #define xd_p_fec_super_frm_unit_7_0 0xA380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) #define fec_super_frm_unit_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) #define fec_super_frm_unit_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) #define fec_super_frm_unit_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) #define xd_p_fec_super_frm_unit_15_8 0xA381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) #define fec_super_frm_unit_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) #define fec_super_frm_unit_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) #define fec_super_frm_unit_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) #define xd_r_fec_vtb_err_bit_cnt_7_0 0xA382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) #define fec_vtb_err_bit_cnt_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) #define fec_vtb_err_bit_cnt_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) #define fec_vtb_err_bit_cnt_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) #define xd_r_fec_vtb_err_bit_cnt_15_8 0xA383
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) #define fec_vtb_err_bit_cnt_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) #define fec_vtb_err_bit_cnt_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) #define fec_vtb_err_bit_cnt_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) #define xd_r_fec_vtb_err_bit_cnt_23_16 0xA384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) #define fec_vtb_err_bit_cnt_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) #define fec_vtb_err_bit_cnt_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) #define fec_vtb_err_bit_cnt_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) #define xd_p_fec_rsd_packet_unit_7_0 0xA385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) #define fec_rsd_packet_unit_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) #define fec_rsd_packet_unit_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) #define fec_rsd_packet_unit_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) #define xd_p_fec_rsd_packet_unit_15_8 0xA386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) #define fec_rsd_packet_unit_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) #define fec_rsd_packet_unit_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) #define fec_rsd_packet_unit_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) #define xd_r_fec_rsd_bit_err_cnt_7_0 0xA387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) #define fec_rsd_bit_err_cnt_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) #define fec_rsd_bit_err_cnt_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) #define fec_rsd_bit_err_cnt_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) #define xd_r_fec_rsd_bit_err_cnt_15_8 0xA388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) #define fec_rsd_bit_err_cnt_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) #define fec_rsd_bit_err_cnt_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) #define fec_rsd_bit_err_cnt_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) #define xd_r_fec_rsd_bit_err_cnt_23_16 0xA389
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) #define fec_rsd_bit_err_cnt_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) #define fec_rsd_bit_err_cnt_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) #define fec_rsd_bit_err_cnt_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) #define xd_r_fec_rsd_abort_packet_cnt_7_0 0xA38A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) #define fec_rsd_abort_packet_cnt_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) #define fec_rsd_abort_packet_cnt_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) #define fec_rsd_abort_packet_cnt_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) #define xd_r_fec_rsd_abort_packet_cnt_15_8 0xA38B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) #define fec_rsd_abort_packet_cnt_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) #define fec_rsd_abort_packet_cnt_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) #define fec_rsd_abort_packet_cnt_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) #define xd_p_fec_RSD_PKT_NUM_PER_UNIT_7_0 0xA38C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) #define fec_RSD_PKT_NUM_PER_UNIT_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) #define fec_RSD_PKT_NUM_PER_UNIT_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) #define fec_RSD_PKT_NUM_PER_UNIT_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) #define xd_p_fec_RSD_PKT_NUM_PER_UNIT_15_8 0xA38D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) #define fec_RSD_PKT_NUM_PER_UNIT_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) #define fec_RSD_PKT_NUM_PER_UNIT_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) #define fec_RSD_PKT_NUM_PER_UNIT_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) #define xd_p_fec_RS_TH_1_7_0 0xA38E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) #define fec_RS_TH_1_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) #define fec_RS_TH_1_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) #define fec_RS_TH_1_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) #define xd_p_fec_RS_TH_1_15_8 0xA38F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) #define fec_RS_TH_1_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) #define fec_RS_TH_1_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) #define fec_RS_TH_1_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) #define xd_p_fec_RS_TH_2 0xA390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) #define fec_RS_TH_2_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) #define fec_RS_TH_2_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) #define fec_RS_TH_2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) #define xd_p_fec_mon_en 0xA391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) #define fec_mon_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) #define fec_mon_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) #define fec_mon_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) #define xd_p_reg_b8to47 0xA391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) #define reg_b8to47_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) #define reg_b8to47_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) #define reg_b8to47_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) #define xd_p_reg_rsd_sync_rep 0xA391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) #define reg_rsd_sync_rep_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) #define reg_rsd_sync_rep_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) #define reg_rsd_sync_rep_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) #define xd_p_fec_rsd_retrain_rst 0xA391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) #define fec_rsd_retrain_rst_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) #define fec_rsd_retrain_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) #define fec_rsd_retrain_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) #define xd_r_fec_rsd_ber_rdy 0xA391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) #define fec_rsd_ber_rdy_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) #define fec_rsd_ber_rdy_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) #define fec_rsd_ber_rdy_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) #define xd_p_fec_rsd_ber_rst 0xA391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) #define fec_rsd_ber_rst_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) #define fec_rsd_ber_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) #define fec_rsd_ber_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) #define xd_r_fec_vtb_ber_rdy 0xA391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) #define fec_vtb_ber_rdy_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) #define fec_vtb_ber_rdy_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) #define fec_vtb_ber_rdy_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) #define xd_p_fec_vtb_ber_rst 0xA391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) #define fec_vtb_ber_rst_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) #define fec_vtb_ber_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) #define fec_vtb_ber_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) #define xd_p_reg_vtb_clk40en 0xA392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) #define reg_vtb_clk40en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) #define reg_vtb_clk40en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) #define reg_vtb_clk40en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) #define xd_p_fec_vtb_rsd_mon_en 0xA392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) #define fec_vtb_rsd_mon_en_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) #define fec_vtb_rsd_mon_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) #define fec_vtb_rsd_mon_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) #define xd_p_reg_fec_data_en 0xA392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) #define reg_fec_data_en_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) #define reg_fec_data_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) #define reg_fec_data_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) #define xd_p_fec_dummy_reg_2 0xA392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) #define fec_dummy_reg_2_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) #define fec_dummy_reg_2_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) #define fec_dummy_reg_2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) #define xd_p_reg_sync_chk 0xA392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) #define reg_sync_chk_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) #define reg_sync_chk_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) #define reg_sync_chk_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) #define xd_p_fec_rsd_bypass 0xA392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) #define fec_rsd_bypass_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) #define fec_rsd_bypass_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) #define fec_rsd_bypass_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) #define xd_p_fec_sw_rst 0xA393
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) #define fec_sw_rst_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) #define fec_sw_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) #define fec_sw_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) #define xd_r_fec_vtb_pm_crc 0xA394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) #define fec_vtb_pm_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) #define fec_vtb_pm_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) #define fec_vtb_pm_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) #define xd_r_fec_vtb_tb_7_crc 0xA395
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) #define fec_vtb_tb_7_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) #define fec_vtb_tb_7_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) #define fec_vtb_tb_7_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) #define xd_r_fec_vtb_tb_6_crc 0xA396
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) #define fec_vtb_tb_6_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) #define fec_vtb_tb_6_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) #define fec_vtb_tb_6_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) #define xd_r_fec_vtb_tb_5_crc 0xA397
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) #define fec_vtb_tb_5_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) #define fec_vtb_tb_5_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) #define fec_vtb_tb_5_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) #define xd_r_fec_vtb_tb_4_crc 0xA398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) #define fec_vtb_tb_4_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) #define fec_vtb_tb_4_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) #define fec_vtb_tb_4_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) #define xd_r_fec_vtb_tb_3_crc 0xA399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) #define fec_vtb_tb_3_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) #define fec_vtb_tb_3_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) #define fec_vtb_tb_3_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) #define xd_r_fec_vtb_tb_2_crc 0xA39A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) #define fec_vtb_tb_2_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) #define fec_vtb_tb_2_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) #define fec_vtb_tb_2_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) #define xd_r_fec_vtb_tb_1_crc 0xA39B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) #define fec_vtb_tb_1_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) #define fec_vtb_tb_1_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) #define fec_vtb_tb_1_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) #define xd_r_fec_vtb_tb_0_crc 0xA39C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) #define fec_vtb_tb_0_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) #define fec_vtb_tb_0_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) #define fec_vtb_tb_0_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) #define xd_r_fec_rsd_bank0_crc 0xA39D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) #define fec_rsd_bank0_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) #define fec_rsd_bank0_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) #define fec_rsd_bank0_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) #define xd_r_fec_rsd_bank1_crc 0xA39E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) #define fec_rsd_bank1_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) #define fec_rsd_bank1_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) #define fec_rsd_bank1_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) #define xd_r_fec_idi_vtb_crc 0xA39F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) #define fec_idi_vtb_crc_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) #define fec_idi_vtb_crc_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) #define fec_idi_vtb_crc_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) #define xd_g_reg_tpsd_txmod 0xA3C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) #define reg_tpsd_txmod_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) #define reg_tpsd_txmod_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) #define reg_tpsd_txmod_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) #define xd_g_reg_tpsd_gi 0xA3C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) #define reg_tpsd_gi_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) #define reg_tpsd_gi_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) #define reg_tpsd_gi_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) #define xd_g_reg_tpsd_hier 0xA3C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) #define reg_tpsd_hier_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) #define reg_tpsd_hier_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) #define reg_tpsd_hier_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) #define xd_g_reg_bw 0xA3C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) #define reg_bw_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) #define reg_bw_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) #define reg_bw_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) #define xd_g_reg_dec_pri 0xA3C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) #define reg_dec_pri_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) #define reg_dec_pri_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) #define reg_dec_pri_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) #define xd_g_reg_tpsd_const 0xA3C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) #define reg_tpsd_const_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) #define reg_tpsd_const_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) #define reg_tpsd_const_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) #define xd_g_reg_tpsd_hpcr 0xA3C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) #define reg_tpsd_hpcr_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) #define reg_tpsd_hpcr_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) #define reg_tpsd_hpcr_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) #define xd_g_reg_tpsd_lpcr 0xA3C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) #define reg_tpsd_lpcr_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) #define reg_tpsd_lpcr_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) #define reg_tpsd_lpcr_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) #define xd_g_reg_ofsm_clk 0xA3D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) #define reg_ofsm_clk_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) #define reg_ofsm_clk_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) #define reg_ofsm_clk_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) #define xd_g_reg_fclk_cfg 0xA3D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) #define reg_fclk_cfg_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) #define reg_fclk_cfg_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) #define reg_fclk_cfg_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) #define xd_g_reg_fclk_idi 0xA3D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) #define reg_fclk_idi_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) #define reg_fclk_idi_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) #define reg_fclk_idi_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) #define xd_g_reg_fclk_odi 0xA3D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) #define reg_fclk_odi_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) #define reg_fclk_odi_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) #define reg_fclk_odi_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) #define xd_g_reg_fclk_rsd 0xA3D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) #define reg_fclk_rsd_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) #define reg_fclk_rsd_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) #define reg_fclk_rsd_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) #define xd_g_reg_fclk_vtb 0xA3D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) #define reg_fclk_vtb_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) #define reg_fclk_vtb_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) #define reg_fclk_vtb_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) #define xd_g_reg_fclk_cste 0xA3D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) #define reg_fclk_cste_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) #define reg_fclk_cste_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) #define reg_fclk_cste_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) #define xd_g_reg_fclk_mp2if 0xA3D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) #define reg_fclk_mp2if_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) #define reg_fclk_mp2if_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) #define reg_fclk_mp2if_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) #define xd_I2C_i2c_m_slave_addr 0xA400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) #define i2c_m_slave_addr_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) #define i2c_m_slave_addr_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) #define i2c_m_slave_addr_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) #define xd_I2C_i2c_m_data1 0xA401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) #define i2c_m_data1_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) #define i2c_m_data1_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) #define i2c_m_data1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) #define xd_I2C_i2c_m_data2 0xA402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) #define i2c_m_data2_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) #define i2c_m_data2_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) #define i2c_m_data2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) #define xd_I2C_i2c_m_data3 0xA403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) #define i2c_m_data3_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) #define i2c_m_data3_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) #define i2c_m_data3_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) #define xd_I2C_i2c_m_data4 0xA404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) #define i2c_m_data4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) #define i2c_m_data4_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) #define i2c_m_data4_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) #define xd_I2C_i2c_m_data5 0xA405
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) #define i2c_m_data5_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) #define i2c_m_data5_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) #define i2c_m_data5_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) #define xd_I2C_i2c_m_data6 0xA406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) #define i2c_m_data6_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) #define i2c_m_data6_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) #define i2c_m_data6_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) #define xd_I2C_i2c_m_data7 0xA407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) #define i2c_m_data7_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) #define i2c_m_data7_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) #define i2c_m_data7_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) #define xd_I2C_i2c_m_data8 0xA408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) #define i2c_m_data8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) #define i2c_m_data8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) #define i2c_m_data8_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) #define xd_I2C_i2c_m_data9 0xA409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) #define i2c_m_data9_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) #define i2c_m_data9_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) #define i2c_m_data9_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) #define xd_I2C_i2c_m_data10 0xA40A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) #define i2c_m_data10_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) #define i2c_m_data10_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) #define i2c_m_data10_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) #define xd_I2C_i2c_m_data11 0xA40B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) #define i2c_m_data11_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) #define i2c_m_data11_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) #define i2c_m_data11_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) #define xd_I2C_i2c_m_cmd_rw 0xA40C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) #define i2c_m_cmd_rw_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) #define i2c_m_cmd_rw_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) #define i2c_m_cmd_rw_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) #define xd_I2C_i2c_m_cmd_rwlen 0xA40C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) #define i2c_m_cmd_rwlen_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) #define i2c_m_cmd_rwlen_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) #define i2c_m_cmd_rwlen_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) #define xd_I2C_i2c_m_status_cmd_exe 0xA40D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) #define i2c_m_status_cmd_exe_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) #define i2c_m_status_cmd_exe_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) #define i2c_m_status_cmd_exe_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) #define xd_I2C_i2c_m_status_wdat_done 0xA40D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) #define i2c_m_status_wdat_done_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) #define i2c_m_status_wdat_done_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) #define i2c_m_status_wdat_done_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) #define xd_I2C_i2c_m_status_wdat_fail 0xA40D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) #define i2c_m_status_wdat_fail_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) #define i2c_m_status_wdat_fail_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) #define i2c_m_status_wdat_fail_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) #define xd_I2C_i2c_m_period 0xA40E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) #define i2c_m_period_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) #define i2c_m_period_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) #define i2c_m_period_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) #define xd_I2C_i2c_m_reg_msb_lsb 0xA40F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) #define i2c_m_reg_msb_lsb_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) #define i2c_m_reg_msb_lsb_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) #define i2c_m_reg_msb_lsb_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) #define xd_I2C_reg_ofdm_rst 0xA40F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) #define reg_ofdm_rst_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) #define reg_ofdm_rst_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) #define reg_ofdm_rst_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) #define xd_I2C_reg_sample_period_on_tuner 0xA40F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) #define reg_sample_period_on_tuner_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) #define reg_sample_period_on_tuner_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) #define reg_sample_period_on_tuner_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) #define xd_I2C_reg_rst_i2c 0xA40F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) #define reg_rst_i2c_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) #define reg_rst_i2c_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) #define reg_rst_i2c_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) #define xd_I2C_reg_ofdm_rst_en 0xA40F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) #define reg_ofdm_rst_en_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) #define reg_ofdm_rst_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) #define reg_ofdm_rst_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) #define xd_I2C_reg_tuner_sda_sync_on 0xA40F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) #define reg_tuner_sda_sync_on_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) #define reg_tuner_sda_sync_on_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) #define reg_tuner_sda_sync_on_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) #define xd_p_mp2if_data_access_disable_ofsm 0xA500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) #define mp2if_data_access_disable_ofsm_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) #define mp2if_data_access_disable_ofsm_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) #define mp2if_data_access_disable_ofsm_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) #define xd_p_reg_mp2_sw_rst_ofsm 0xA500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) #define reg_mp2_sw_rst_ofsm_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) #define reg_mp2_sw_rst_ofsm_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) #define reg_mp2_sw_rst_ofsm_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) #define xd_p_reg_mp2if_clk_en_ofsm 0xA500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) #define reg_mp2if_clk_en_ofsm_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) #define reg_mp2if_clk_en_ofsm_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) #define reg_mp2if_clk_en_ofsm_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) #define xd_r_mp2if_sync_byte_locked 0xA500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) #define mp2if_sync_byte_locked_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) #define mp2if_sync_byte_locked_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) #define mp2if_sync_byte_locked_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) #define xd_r_mp2if_ts_not_188 0xA500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) #define mp2if_ts_not_188_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) #define mp2if_ts_not_188_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) #define mp2if_ts_not_188_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) #define xd_r_mp2if_psb_empty 0xA500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) #define mp2if_psb_empty_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) #define mp2if_psb_empty_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) #define mp2if_psb_empty_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) #define xd_r_mp2if_psb_overflow 0xA500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) #define mp2if_psb_overflow_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) #define mp2if_psb_overflow_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) #define mp2if_psb_overflow_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) #define xd_p_mp2if_keep_sf_sync_byte_ofsm 0xA500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) #define mp2if_keep_sf_sync_byte_ofsm_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) #define mp2if_keep_sf_sync_byte_ofsm_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) #define mp2if_keep_sf_sync_byte_ofsm_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) #define xd_r_mp2if_psb_mp2if_num_pkt 0xA501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) #define mp2if_psb_mp2if_num_pkt_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) #define mp2if_psb_mp2if_num_pkt_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) #define mp2if_psb_mp2if_num_pkt_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) #define xd_p_reg_mpeg_full_speed_ofsm 0xA501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) #define reg_mpeg_full_speed_ofsm_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) #define reg_mpeg_full_speed_ofsm_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) #define reg_mpeg_full_speed_ofsm_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) #define xd_p_mp2if_mpeg_ser_mode_ofsm 0xA501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) #define mp2if_mpeg_ser_mode_ofsm_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) #define mp2if_mpeg_ser_mode_ofsm_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) #define mp2if_mpeg_ser_mode_ofsm_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) #define xd_p_reg_sw_mon51 0xA600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) #define reg_sw_mon51_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) #define reg_sw_mon51_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) #define reg_sw_mon51_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) #define xd_p_reg_top_pcsel 0xA601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) #define reg_top_pcsel_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) #define reg_top_pcsel_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) #define reg_top_pcsel_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) #define xd_p_reg_top_rs232 0xA601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) #define reg_top_rs232_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) #define reg_top_rs232_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) #define reg_top_rs232_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) #define xd_p_reg_top_pcout 0xA601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) #define reg_top_pcout_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) #define reg_top_pcout_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) #define reg_top_pcout_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) #define xd_p_reg_top_debug 0xA601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) #define reg_top_debug_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) #define reg_top_debug_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) #define reg_top_debug_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) #define xd_p_reg_top_adcdly 0xA601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) #define reg_top_adcdly_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) #define reg_top_adcdly_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) #define reg_top_adcdly_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) #define xd_p_reg_top_pwrdw 0xA601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) #define reg_top_pwrdw_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) #define reg_top_pwrdw_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) #define reg_top_pwrdw_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) #define xd_p_reg_top_pwrdw_inv 0xA601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) #define reg_top_pwrdw_inv_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) #define reg_top_pwrdw_inv_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) #define reg_top_pwrdw_inv_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) #define xd_p_reg_top_int_inv 0xA602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) #define reg_top_int_inv_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) #define reg_top_int_inv_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) #define reg_top_int_inv_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) #define xd_p_reg_top_dio_sel 0xA602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) #define reg_top_dio_sel_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) #define reg_top_dio_sel_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) #define reg_top_dio_sel_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) #define xd_p_reg_top_gpioon0 0xA603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) #define reg_top_gpioon0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) #define reg_top_gpioon0_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) #define reg_top_gpioon0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) #define xd_p_reg_top_gpioon1 0xA603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) #define reg_top_gpioon1_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) #define reg_top_gpioon1_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) #define reg_top_gpioon1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) #define xd_p_reg_top_gpioon2 0xA603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) #define reg_top_gpioon2_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) #define reg_top_gpioon2_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) #define reg_top_gpioon2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) #define xd_p_reg_top_gpioon3 0xA603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) #define reg_top_gpioon3_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) #define reg_top_gpioon3_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) #define reg_top_gpioon3_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) #define xd_p_reg_top_lockon1 0xA603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) #define reg_top_lockon1_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) #define reg_top_lockon1_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) #define reg_top_lockon1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) #define xd_p_reg_top_lockon2 0xA603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) #define reg_top_lockon2_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) #define reg_top_lockon2_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) #define reg_top_lockon2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) #define xd_p_reg_top_gpioo0 0xA604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) #define reg_top_gpioo0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) #define reg_top_gpioo0_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) #define reg_top_gpioo0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) #define xd_p_reg_top_gpioo1 0xA604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) #define reg_top_gpioo1_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) #define reg_top_gpioo1_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) #define reg_top_gpioo1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) #define xd_p_reg_top_gpioo2 0xA604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) #define reg_top_gpioo2_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) #define reg_top_gpioo2_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) #define reg_top_gpioo2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) #define xd_p_reg_top_gpioo3 0xA604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) #define reg_top_gpioo3_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) #define reg_top_gpioo3_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) #define reg_top_gpioo3_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) #define xd_p_reg_top_lock1 0xA604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) #define reg_top_lock1_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) #define reg_top_lock1_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) #define reg_top_lock1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) #define xd_p_reg_top_lock2 0xA604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) #define reg_top_lock2_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) #define reg_top_lock2_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) #define reg_top_lock2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) #define xd_p_reg_top_gpioen0 0xA605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) #define reg_top_gpioen0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) #define reg_top_gpioen0_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) #define reg_top_gpioen0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) #define xd_p_reg_top_gpioen1 0xA605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) #define reg_top_gpioen1_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) #define reg_top_gpioen1_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) #define reg_top_gpioen1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) #define xd_p_reg_top_gpioen2 0xA605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) #define reg_top_gpioen2_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) #define reg_top_gpioen2_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) #define reg_top_gpioen2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) #define xd_p_reg_top_gpioen3 0xA605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) #define reg_top_gpioen3_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) #define reg_top_gpioen3_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) #define reg_top_gpioen3_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) #define xd_p_reg_top_locken1 0xA605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) #define reg_top_locken1_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) #define reg_top_locken1_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) #define reg_top_locken1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) #define xd_p_reg_top_locken2 0xA605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) #define reg_top_locken2_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) #define reg_top_locken2_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) #define reg_top_locken2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) #define xd_r_reg_top_gpioi0 0xA606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) #define reg_top_gpioi0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) #define reg_top_gpioi0_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) #define reg_top_gpioi0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) #define xd_r_reg_top_gpioi1 0xA606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) #define reg_top_gpioi1_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) #define reg_top_gpioi1_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) #define reg_top_gpioi1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) #define xd_r_reg_top_gpioi2 0xA606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) #define reg_top_gpioi2_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) #define reg_top_gpioi2_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) #define reg_top_gpioi2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) #define xd_r_reg_top_gpioi3 0xA606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) #define reg_top_gpioi3_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) #define reg_top_gpioi3_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) #define reg_top_gpioi3_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) #define xd_r_reg_top_locki1 0xA606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) #define reg_top_locki1_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) #define reg_top_locki1_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) #define reg_top_locki1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) #define xd_r_reg_top_locki2 0xA606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) #define reg_top_locki2_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) #define reg_top_locki2_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) #define reg_top_locki2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) #define xd_p_reg_dummy_7_0 0xA608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) #define reg_dummy_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) #define reg_dummy_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) #define reg_dummy_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) #define xd_p_reg_dummy_15_8 0xA609
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) #define reg_dummy_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) #define reg_dummy_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) #define reg_dummy_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) #define xd_p_reg_dummy_23_16 0xA60A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) #define reg_dummy_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) #define reg_dummy_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) #define reg_dummy_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) #define xd_p_reg_dummy_31_24 0xA60B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) #define reg_dummy_31_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) #define reg_dummy_31_24_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) #define reg_dummy_31_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) #define xd_p_reg_dummy_39_32 0xA60C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) #define reg_dummy_39_32_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) #define reg_dummy_39_32_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) #define reg_dummy_39_32_lsb 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) #define xd_p_reg_dummy_47_40 0xA60D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) #define reg_dummy_47_40_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) #define reg_dummy_47_40_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) #define reg_dummy_47_40_lsb 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) #define xd_p_reg_dummy_55_48 0xA60E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) #define reg_dummy_55_48_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) #define reg_dummy_55_48_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) #define reg_dummy_55_48_lsb 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) #define xd_p_reg_dummy_63_56 0xA60F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) #define reg_dummy_63_56_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) #define reg_dummy_63_56_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) #define reg_dummy_63_56_lsb 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) #define xd_p_reg_dummy_71_64 0xA610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) #define reg_dummy_71_64_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) #define reg_dummy_71_64_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) #define reg_dummy_71_64_lsb 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) #define xd_p_reg_dummy_79_72 0xA611
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) #define reg_dummy_79_72_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) #define reg_dummy_79_72_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) #define reg_dummy_79_72_lsb 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) #define xd_p_reg_dummy_87_80 0xA612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) #define reg_dummy_87_80_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) #define reg_dummy_87_80_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) #define reg_dummy_87_80_lsb 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) #define xd_p_reg_dummy_95_88 0xA613
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) #define reg_dummy_95_88_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) #define reg_dummy_95_88_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) #define reg_dummy_95_88_lsb 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) #define xd_p_reg_dummy_103_96 0xA614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) #define reg_dummy_103_96_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) #define reg_dummy_103_96_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) #define reg_dummy_103_96_lsb 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) #define xd_p_reg_unplug_flag 0xA615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) #define reg_unplug_flag_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) #define reg_unplug_flag_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) #define reg_unplug_flag_lsb 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) #define xd_p_reg_api_dca_stes_request 0xA615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) #define reg_api_dca_stes_request_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) #define reg_api_dca_stes_request_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) #define reg_api_dca_stes_request_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) #define xd_p_reg_back_to_dca_flag 0xA615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) #define reg_back_to_dca_flag_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) #define reg_back_to_dca_flag_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) #define reg_back_to_dca_flag_lsb 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) #define xd_p_reg_api_retrain_request 0xA615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) #define reg_api_retrain_request_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) #define reg_api_retrain_request_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) #define reg_api_retrain_request_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) #define xd_p_reg_Dyn_Top_Try_flag 0xA615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) #define reg_Dyn_Top_Try_flag_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) #define reg_Dyn_Top_Try_flag_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) #define reg_Dyn_Top_Try_flag_lsb 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) #define xd_p_reg_API_retrain_freeze_flag 0xA615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) #define reg_API_retrain_freeze_flag_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) #define reg_API_retrain_freeze_flag_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) #define reg_API_retrain_freeze_flag_lsb 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) #define xd_p_reg_dummy_111_104 0xA615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) #define reg_dummy_111_104_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) #define reg_dummy_111_104_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) #define reg_dummy_111_104_lsb 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) #define xd_p_reg_dummy_119_112 0xA616
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) #define reg_dummy_119_112_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) #define reg_dummy_119_112_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) #define reg_dummy_119_112_lsb 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) #define xd_p_reg_dummy_127_120 0xA617
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) #define reg_dummy_127_120_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) #define reg_dummy_127_120_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) #define reg_dummy_127_120_lsb 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) #define xd_p_reg_dummy_135_128 0xA618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) #define reg_dummy_135_128_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) #define reg_dummy_135_128_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) #define reg_dummy_135_128_lsb 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) #define xd_p_reg_dummy_143_136 0xA619
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) #define reg_dummy_143_136_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) #define reg_dummy_143_136_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) #define reg_dummy_143_136_lsb 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) #define xd_p_reg_CCIR_dis 0xA619
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) #define reg_CCIR_dis_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) #define reg_CCIR_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) #define reg_CCIR_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) #define xd_p_reg_dummy_151_144 0xA61A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) #define reg_dummy_151_144_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) #define reg_dummy_151_144_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) #define reg_dummy_151_144_lsb 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) #define xd_p_reg_dummy_159_152 0xA61B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) #define reg_dummy_159_152_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) #define reg_dummy_159_152_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) #define reg_dummy_159_152_lsb 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) #define xd_p_reg_dummy_167_160 0xA61C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) #define reg_dummy_167_160_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) #define reg_dummy_167_160_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) #define reg_dummy_167_160_lsb 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) #define xd_p_reg_dummy_175_168 0xA61D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) #define reg_dummy_175_168_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) #define reg_dummy_175_168_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) #define reg_dummy_175_168_lsb 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) #define xd_p_reg_dummy_183_176 0xA61E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) #define reg_dummy_183_176_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) #define reg_dummy_183_176_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) #define reg_dummy_183_176_lsb 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) #define xd_p_reg_ofsm_read_rbc_en 0xA61E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) #define reg_ofsm_read_rbc_en_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) #define reg_ofsm_read_rbc_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) #define reg_ofsm_read_rbc_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) #define xd_p_reg_ce_filter_selection_dis 0xA61E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) #define reg_ce_filter_selection_dis_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) #define reg_ce_filter_selection_dis_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) #define reg_ce_filter_selection_dis_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) #define xd_p_reg_OFSM_version_control_7_0 0xA611
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) #define reg_OFSM_version_control_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) #define reg_OFSM_version_control_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) #define reg_OFSM_version_control_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) #define xd_p_reg_OFSM_version_control_15_8 0xA61F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) #define reg_OFSM_version_control_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) #define reg_OFSM_version_control_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) #define reg_OFSM_version_control_15_8_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) #define xd_p_reg_OFSM_version_control_23_16 0xA620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) #define reg_OFSM_version_control_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) #define reg_OFSM_version_control_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) #define reg_OFSM_version_control_23_16_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) #define xd_p_reg_dummy_191_184 0xA61F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) #define reg_dummy_191_184_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) #define reg_dummy_191_184_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) #define reg_dummy_191_184_lsb 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) #define xd_p_reg_dummy_199_192 0xA620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) #define reg_dummy_199_192_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) #define reg_dummy_199_192_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) #define reg_dummy_199_192_lsb 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) #define xd_p_reg_ce_en 0xABC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) #define reg_ce_en_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) #define reg_ce_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) #define reg_ce_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) #define xd_p_reg_ce_fctrl_en 0xABC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) #define reg_ce_fctrl_en_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) #define reg_ce_fctrl_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) #define reg_ce_fctrl_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) #define xd_p_reg_ce_fste_tdi 0xABC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) #define reg_ce_fste_tdi_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) #define reg_ce_fste_tdi_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) #define reg_ce_fste_tdi_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) #define xd_p_reg_ce_dynamic 0xABC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) #define reg_ce_dynamic_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) #define reg_ce_dynamic_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) #define reg_ce_dynamic_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) #define xd_p_reg_ce_conf 0xABC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) #define reg_ce_conf_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) #define reg_ce_conf_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) #define reg_ce_conf_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) #define xd_p_reg_ce_dyn12 0xABC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) #define reg_ce_dyn12_pos 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) #define reg_ce_dyn12_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) #define reg_ce_dyn12_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) #define xd_p_reg_ce_derot_en 0xABC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) #define reg_ce_derot_en_pos 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) #define reg_ce_derot_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) #define reg_ce_derot_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) #define xd_p_reg_ce_dynamic_th_7_0 0xABC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) #define reg_ce_dynamic_th_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) #define reg_ce_dynamic_th_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) #define reg_ce_dynamic_th_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) #define xd_p_reg_ce_dynamic_th_15_8 0xABC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) #define reg_ce_dynamic_th_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) #define reg_ce_dynamic_th_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) #define reg_ce_dynamic_th_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) #define xd_p_reg_ce_s1 0xABC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) #define reg_ce_s1_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) #define reg_ce_s1_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) #define reg_ce_s1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) #define xd_p_reg_ce_var_forced_value 0xABC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) #define reg_ce_var_forced_value_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) #define reg_ce_var_forced_value_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) #define reg_ce_var_forced_value_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) #define xd_p_reg_ce_data_im_7_0 0xABC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) #define reg_ce_data_im_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) #define reg_ce_data_im_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) #define reg_ce_data_im_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) #define xd_p_reg_ce_data_im_8 0xABC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) #define reg_ce_data_im_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) #define reg_ce_data_im_8_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) #define reg_ce_data_im_8_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) #define xd_p_reg_ce_data_re_6_0 0xABC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) #define reg_ce_data_re_6_0_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) #define reg_ce_data_re_6_0_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) #define reg_ce_data_re_6_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) #define xd_p_reg_ce_data_re_8_7 0xABC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) #define reg_ce_data_re_8_7_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) #define reg_ce_data_re_8_7_len 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) #define reg_ce_data_re_8_7_lsb 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) #define xd_p_reg_ce_tone_5_0 0xABC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) #define reg_ce_tone_5_0_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) #define reg_ce_tone_5_0_len 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) #define reg_ce_tone_5_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) #define xd_p_reg_ce_tone_12_6 0xABC7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) #define reg_ce_tone_12_6_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) #define reg_ce_tone_12_6_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) #define reg_ce_tone_12_6_lsb 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) #define xd_p_reg_ce_centroid_drift_th 0xABC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) #define reg_ce_centroid_drift_th_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) #define reg_ce_centroid_drift_th_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) #define reg_ce_centroid_drift_th_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) #define xd_p_reg_ce_centroid_count_max 0xABC9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) #define reg_ce_centroid_count_max_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) #define reg_ce_centroid_count_max_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) #define reg_ce_centroid_count_max_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) #define xd_p_reg_ce_centroid_bias_inc_7_0 0xABCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) #define reg_ce_centroid_bias_inc_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) #define reg_ce_centroid_bias_inc_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) #define reg_ce_centroid_bias_inc_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) #define xd_p_reg_ce_centroid_bias_inc_8 0xABCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) #define reg_ce_centroid_bias_inc_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) #define reg_ce_centroid_bias_inc_8_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) #define reg_ce_centroid_bias_inc_8_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) #define xd_p_reg_ce_var_th0_7_0 0xABCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) #define reg_ce_var_th0_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) #define reg_ce_var_th0_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) #define reg_ce_var_th0_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) #define xd_p_reg_ce_var_th0_15_8 0xABCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) #define reg_ce_var_th0_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) #define reg_ce_var_th0_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) #define reg_ce_var_th0_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) #define xd_p_reg_ce_var_th1_7_0 0xABCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) #define reg_ce_var_th1_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) #define reg_ce_var_th1_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) #define reg_ce_var_th1_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) #define xd_p_reg_ce_var_th1_15_8 0xABCF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) #define reg_ce_var_th1_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) #define reg_ce_var_th1_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) #define reg_ce_var_th1_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) #define xd_p_reg_ce_var_th2_7_0 0xABD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) #define reg_ce_var_th2_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) #define reg_ce_var_th2_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) #define reg_ce_var_th2_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) #define xd_p_reg_ce_var_th2_15_8 0xABD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) #define reg_ce_var_th2_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) #define reg_ce_var_th2_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) #define reg_ce_var_th2_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) #define xd_p_reg_ce_var_th3_7_0 0xABD2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) #define reg_ce_var_th3_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) #define reg_ce_var_th3_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) #define reg_ce_var_th3_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) #define xd_p_reg_ce_var_th3_15_8 0xABD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) #define reg_ce_var_th3_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) #define reg_ce_var_th3_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) #define reg_ce_var_th3_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) #define xd_p_reg_ce_var_th4_7_0 0xABD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) #define reg_ce_var_th4_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) #define reg_ce_var_th4_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) #define reg_ce_var_th4_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) #define xd_p_reg_ce_var_th4_15_8 0xABD5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) #define reg_ce_var_th4_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) #define reg_ce_var_th4_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) #define reg_ce_var_th4_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) #define xd_p_reg_ce_var_th5_7_0 0xABD6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) #define reg_ce_var_th5_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) #define reg_ce_var_th5_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) #define reg_ce_var_th5_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) #define xd_p_reg_ce_var_th5_15_8 0xABD7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) #define reg_ce_var_th5_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) #define reg_ce_var_th5_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) #define reg_ce_var_th5_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) #define xd_p_reg_ce_var_th6_7_0 0xABD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) #define reg_ce_var_th6_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) #define reg_ce_var_th6_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) #define reg_ce_var_th6_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) #define xd_p_reg_ce_var_th6_15_8 0xABD9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) #define reg_ce_var_th6_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) #define reg_ce_var_th6_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) #define reg_ce_var_th6_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) #define xd_p_reg_ce_fctrl_reset 0xABDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) #define reg_ce_fctrl_reset_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) #define reg_ce_fctrl_reset_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) #define reg_ce_fctrl_reset_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) #define xd_p_reg_ce_cent_auto_clr_en 0xABDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) #define reg_ce_cent_auto_clr_en_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) #define reg_ce_cent_auto_clr_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) #define reg_ce_cent_auto_clr_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) #define xd_p_reg_ce_fctrl_auto_reset_en 0xABDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) #define reg_ce_fctrl_auto_reset_en_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) #define reg_ce_fctrl_auto_reset_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) #define reg_ce_fctrl_auto_reset_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) #define xd_p_reg_ce_var_forced_en 0xABDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) #define reg_ce_var_forced_en_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) #define reg_ce_var_forced_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) #define reg_ce_var_forced_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) #define xd_p_reg_ce_cent_forced_en 0xABDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) #define reg_ce_cent_forced_en_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) #define reg_ce_cent_forced_en_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) #define reg_ce_cent_forced_en_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) #define xd_p_reg_ce_var_max 0xABDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) #define reg_ce_var_max_pos 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) #define reg_ce_var_max_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) #define reg_ce_var_max_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) #define xd_p_reg_ce_cent_forced_value_7_0 0xABDB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) #define reg_ce_cent_forced_value_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) #define reg_ce_cent_forced_value_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) #define reg_ce_cent_forced_value_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) #define xd_p_reg_ce_cent_forced_value_11_8 0xABDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) #define reg_ce_cent_forced_value_11_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) #define reg_ce_cent_forced_value_11_8_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) #define reg_ce_cent_forced_value_11_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) #define xd_p_reg_ce_fctrl_rd 0xABDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) #define reg_ce_fctrl_rd_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) #define reg_ce_fctrl_rd_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) #define reg_ce_fctrl_rd_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) #define xd_p_reg_ce_centroid_max_6_0 0xABDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) #define reg_ce_centroid_max_6_0_pos 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) #define reg_ce_centroid_max_6_0_len 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) #define reg_ce_centroid_max_6_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) #define xd_p_reg_ce_centroid_max_11_7 0xABDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) #define reg_ce_centroid_max_11_7_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) #define reg_ce_centroid_max_11_7_len 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) #define reg_ce_centroid_max_11_7_lsb 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) #define xd_p_reg_ce_var 0xABDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) #define reg_ce_var_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) #define reg_ce_var_len 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) #define reg_ce_var_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) #define xd_p_reg_ce_fctrl_rdy 0xABDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) #define reg_ce_fctrl_rdy_pos 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) #define reg_ce_fctrl_rdy_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) #define reg_ce_fctrl_rdy_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) #define xd_p_reg_ce_centroid_out_3_0 0xABDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) #define reg_ce_centroid_out_3_0_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) #define reg_ce_centroid_out_3_0_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) #define reg_ce_centroid_out_3_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) #define xd_p_reg_ce_centroid_out_11_4 0xABE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) #define reg_ce_centroid_out_11_4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) #define reg_ce_centroid_out_11_4_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) #define reg_ce_centroid_out_11_4_lsb 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) #define xd_p_reg_ce_bias_7_0 0xABE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) #define reg_ce_bias_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) #define reg_ce_bias_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) #define reg_ce_bias_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) #define xd_p_reg_ce_bias_11_8 0xABE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) #define reg_ce_bias_11_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) #define reg_ce_bias_11_8_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) #define reg_ce_bias_11_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) #define xd_p_reg_ce_m1_3_0 0xABE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) #define reg_ce_m1_3_0_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) #define reg_ce_m1_3_0_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) #define reg_ce_m1_3_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) #define xd_p_reg_ce_m1_11_4 0xABE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) #define reg_ce_m1_11_4_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) #define reg_ce_m1_11_4_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) #define reg_ce_m1_11_4_lsb 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) #define xd_p_reg_ce_rh0_7_0 0xABE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) #define reg_ce_rh0_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) #define reg_ce_rh0_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) #define reg_ce_rh0_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) #define xd_p_reg_ce_rh0_15_8 0xABE5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) #define reg_ce_rh0_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) #define reg_ce_rh0_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) #define reg_ce_rh0_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) #define xd_p_reg_ce_rh0_23_16 0xABE6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) #define reg_ce_rh0_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) #define reg_ce_rh0_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) #define reg_ce_rh0_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) #define xd_p_reg_ce_rh0_31_24 0xABE7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) #define reg_ce_rh0_31_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) #define reg_ce_rh0_31_24_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) #define reg_ce_rh0_31_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) #define xd_p_reg_ce_rh3_real_7_0 0xABE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) #define reg_ce_rh3_real_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) #define reg_ce_rh3_real_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) #define reg_ce_rh3_real_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) #define xd_p_reg_ce_rh3_real_15_8 0xABE9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) #define reg_ce_rh3_real_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) #define reg_ce_rh3_real_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) #define reg_ce_rh3_real_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) #define xd_p_reg_ce_rh3_real_23_16 0xABEA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) #define reg_ce_rh3_real_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) #define reg_ce_rh3_real_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) #define reg_ce_rh3_real_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) #define xd_p_reg_ce_rh3_real_31_24 0xABEB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) #define reg_ce_rh3_real_31_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) #define reg_ce_rh3_real_31_24_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) #define reg_ce_rh3_real_31_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) #define xd_p_reg_ce_rh3_imag_7_0 0xABEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) #define reg_ce_rh3_imag_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) #define reg_ce_rh3_imag_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) #define reg_ce_rh3_imag_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) #define xd_p_reg_ce_rh3_imag_15_8 0xABED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) #define reg_ce_rh3_imag_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) #define reg_ce_rh3_imag_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) #define reg_ce_rh3_imag_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) #define xd_p_reg_ce_rh3_imag_23_16 0xABEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) #define reg_ce_rh3_imag_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) #define reg_ce_rh3_imag_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) #define reg_ce_rh3_imag_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) #define xd_p_reg_ce_rh3_imag_31_24 0xABEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) #define reg_ce_rh3_imag_31_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) #define reg_ce_rh3_imag_31_24_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) #define reg_ce_rh3_imag_31_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) #define xd_p_reg_feq_fix_eh2_7_0 0xABF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) #define reg_feq_fix_eh2_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) #define reg_feq_fix_eh2_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) #define reg_feq_fix_eh2_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) #define xd_p_reg_feq_fix_eh2_15_8 0xABF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) #define reg_feq_fix_eh2_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) #define reg_feq_fix_eh2_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) #define reg_feq_fix_eh2_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) #define xd_p_reg_feq_fix_eh2_23_16 0xABF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) #define reg_feq_fix_eh2_23_16_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) #define reg_feq_fix_eh2_23_16_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) #define reg_feq_fix_eh2_23_16_lsb 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) #define xd_p_reg_feq_fix_eh2_31_24 0xABF3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) #define reg_feq_fix_eh2_31_24_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) #define reg_feq_fix_eh2_31_24_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) #define reg_feq_fix_eh2_31_24_lsb 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) #define xd_p_reg_ce_m2_central_7_0 0xABF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) #define reg_ce_m2_central_7_0_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) #define reg_ce_m2_central_7_0_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) #define reg_ce_m2_central_7_0_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) #define xd_p_reg_ce_m2_central_15_8 0xABF5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) #define reg_ce_m2_central_15_8_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) #define reg_ce_m2_central_15_8_len 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) #define reg_ce_m2_central_15_8_lsb 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) #define xd_p_reg_ce_fftshift 0xABF6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) #define reg_ce_fftshift_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) #define reg_ce_fftshift_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) #define reg_ce_fftshift_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) #define xd_p_reg_ce_fftshift1 0xABF6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) #define reg_ce_fftshift1_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) #define reg_ce_fftshift1_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) #define reg_ce_fftshift1_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) #define xd_p_reg_ce_fftshift2 0xABF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) #define reg_ce_fftshift2_pos 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) #define reg_ce_fftshift2_len 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) #define reg_ce_fftshift2_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) #define xd_p_reg_ce_top_mobile 0xABF7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) #define reg_ce_top_mobile_pos 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) #define reg_ce_top_mobile_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) #define reg_ce_top_mobile_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) #define xd_p_reg_strong_sginal_detected 0xA2BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) #define reg_strong_sginal_detected_pos 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) #define reg_strong_sginal_detected_len 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) #define reg_strong_sginal_detected_lsb 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) #define XD_MP2IF_BASE 0xB000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) #define XD_MP2IF_CSR (0x00 + XD_MP2IF_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) #define XD_MP2IF_DMX_CTRL (0x03 + XD_MP2IF_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) #define XD_MP2IF_PID_IDX (0x04 + XD_MP2IF_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) #define XD_MP2IF_PID_DATA_L (0x05 + XD_MP2IF_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) #define XD_MP2IF_PID_DATA_H (0x06 + XD_MP2IF_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) #define XD_MP2IF_MISC (0x07 + XD_MP2IF_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) extern struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) extern int af9005_read_ofdm_register(struct dvb_usb_device *d, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) u8 * value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) extern int af9005_read_ofdm_registers(struct dvb_usb_device *d, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) u8 * values, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) extern int af9005_write_ofdm_register(struct dvb_usb_device *d, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) u8 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) extern int af9005_write_ofdm_registers(struct dvb_usb_device *d, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) u8 * values, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) extern int af9005_read_tuner_registers(struct dvb_usb_device *d, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) u8 addr, u8 * values, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) extern int af9005_write_tuner_registers(struct dvb_usb_device *d, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) u8 * values, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) extern int af9005_read_register_bits(struct dvb_usb_device *d, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) u8 pos, u8 len, u8 * value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) extern int af9005_write_register_bits(struct dvb_usb_device *d, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) u8 pos, u8 len, u8 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) extern int af9005_send_command(struct dvb_usb_device *d, u8 command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) u8 * wbuf, int wlen, u8 * rbuf, int rlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) extern int af9005_read_eeprom(struct dvb_usb_device *d, u8 address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) u8 * values, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) extern int af9005_tuner_attach(struct dvb_usb_adapter *adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) extern int af9005_led_control(struct dvb_usb_device *d, int onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) extern u8 regmask[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) /* remote control decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) extern int af9005_rc_decode(struct dvb_usb_device *d, u8 * data, int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) u32 * event, int *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) extern struct rc_map_table rc_map_af9005_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) extern int rc_map_af9005_table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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