^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Frontend part of the Linux driver for the Afatech 9005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * USB1.1 DVB-T receiver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Thanks to Afatech who kindly provided information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "af9005.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "af9005-script.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "mt2060.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "qt1010.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct af9005_fe_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct dvb_usb_device *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum fe_status stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* retraining parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 original_fcw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u16 original_rf_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u16 original_if_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u16 original_if_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u16 original_aci0_if_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u16 original_aci1_if_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u16 original_aci0_if_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 original_if_unplug_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 original_rf_unplug_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 original_dtop_if_unplug_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 original_dtop_rf_unplug_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 pre_vit_error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 pre_vit_bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 post_vit_error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 post_vit_bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 unc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u16 abort_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int opened;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int strong;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long next_status_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct dvb_frontend frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int af9005_write_word_agc(struct dvb_usb_device *d, u16 reghi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u16 reglo, u8 pos, u8 len, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if ((ret = af9005_write_ofdm_register(d, reglo, (u8) (value & 0xff))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return af9005_write_register_bits(d, reghi, pos, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (u8) ((value & 0x300) >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int af9005_read_word_agc(struct dvb_usb_device *d, u16 reghi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u16 reglo, u8 pos, u8 len, u16 * value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 temp0, temp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if ((ret = af9005_read_ofdm_register(d, reglo, &temp0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if ((ret = af9005_read_ofdm_register(d, reghi, &temp1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) switch (pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *value = ((u16) (temp1 & 0x03) << 8) + (u16) temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *value = ((u16) (temp1 & 0x0C) << 6) + (u16) temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *value = ((u16) (temp1 & 0x30) << 4) + (u16) temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *value = ((u16) (temp1 & 0xC0) << 2) + (u16) temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) err("invalid pos in read word agc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int af9005_is_fecmon_available(struct dvb_frontend *fe, int *available)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *available = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = af9005_read_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) fec_vtb_rsd_mon_en_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) fec_vtb_rsd_mon_en_len, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (temp & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) af9005_read_register_bits(state->d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) xd_p_reg_ofsm_read_rbc_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) reg_ofsm_read_rbc_en_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reg_ofsm_read_rbc_en_len, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if ((temp & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *available = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int af9005_get_post_vit_err_cw_count(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 * post_err_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 * post_cw_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u16 * abort_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 cw_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 temp, temp0, temp1, temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u16 loc_abort_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *post_err_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *post_cw_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* check if error bit count is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) af9005_read_register_bits(state->d, xd_r_fec_rsd_ber_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) fec_rsd_ber_rdy_pos, fec_rsd_ber_rdy_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) deb_info("rsd counter not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* get abort count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) af9005_read_ofdm_register(state->d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) xd_r_fec_rsd_abort_packet_cnt_7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) &temp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) af9005_read_ofdm_register(state->d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) xd_r_fec_rsd_abort_packet_cnt_15_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) &temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) loc_abort_count = ((u16) temp1 << 8) + temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* get error count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) &temp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_15_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) &temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_23_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *post_err_count = err_count - (u32) loc_abort_count *8 * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* get RSD packet number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &temp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) &temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cw_count = ((u32) temp1 << 8) + temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (cw_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) err("wrong RSD packet count");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) deb_info("POST abort count %d err count %d rsd packets %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) loc_abort_count, err_count, cw_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) *post_cw_count = cw_count - (u32) loc_abort_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *abort_count = loc_abort_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int af9005_get_post_vit_ber(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 * post_err_count, u32 * post_cw_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u16 * abort_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 loc_cw_count = 0, loc_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u16 loc_abort_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) af9005_get_post_vit_err_cw_count(fe, &loc_err_count, &loc_cw_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) &loc_abort_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *post_err_count = loc_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *post_cw_count = loc_cw_count * 204 * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *abort_count = loc_abort_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int af9005_get_pre_vit_err_bit_count(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 * pre_err_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 * pre_bit_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 temp, temp0, temp1, temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 super_frame_count, x, bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) af9005_read_register_bits(state->d, xd_r_fec_vtb_ber_rdy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) fec_vtb_ber_rdy_pos, fec_vtb_ber_rdy_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) deb_info("viterbi counter not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 101; /* ERR_APO_VTB_COUNTER_NOT_READY; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) &temp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_15_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) &temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_23_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) &temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *pre_err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) &temp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) &temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) super_frame_count = ((u32) temp1 << 8) + temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (super_frame_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) deb_info("super frame count 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 102;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* read fft mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (temp == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* 2K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) x = 1512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) } else if (temp == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* 8k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) x = 6048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) err("Invalid fft mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* read modulation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) reg_tpsd_const_pos, reg_tpsd_const_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) switch (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case 0: /* QPSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bits = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case 1: /* QAM_16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) bits = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case 2: /* QAM_64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) err("invalid modulation mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *pre_bit_count = super_frame_count * 68 * 4 * x * bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) deb_info("PRE err count %d frame count %d bit count %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *pre_err_count, super_frame_count, *pre_bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int af9005_reset_pre_viterbi(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* set super frame count to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 1 & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 1 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* reset pre viterbi error count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) af9005_write_register_bits(state->d, xd_p_fec_vtb_ber_rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) fec_vtb_ber_rst_pos, fec_vtb_ber_rst_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int af9005_reset_post_viterbi(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* set packet unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 10000 & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 10000 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* reset post viterbi error count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) af9005_write_register_bits(state->d, xd_p_fec_rsd_ber_rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) fec_rsd_ber_rst_pos, fec_rsd_ber_rst_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int af9005_get_statistic(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int ret, fecavailable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u64 numerator, denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) deb_info("GET STATISTIC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = af9005_is_fecmon_available(fe, &fecavailable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!fecavailable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) deb_info("fecmon not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = af9005_get_pre_vit_err_bit_count(fe, &state->pre_vit_error_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) &state->pre_vit_bit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) af9005_reset_pre_viterbi(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (state->pre_vit_bit_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* according to v 0.0.4 of the dvb api ber should be a multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) of 10E-9 so we have to multiply the error count by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 10E9=1000000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) numerator =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) (u64) state->pre_vit_error_count * (u64) 1000000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) denominator = (u64) state->pre_vit_bit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) state->ber = do_div(numerator, denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) state->ber = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = af9005_get_post_vit_ber(fe, &state->post_vit_error_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) &state->post_vit_bit_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) &state->abort_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = af9005_reset_post_viterbi(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) state->unc += state->abort_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int af9005_fe_refresh_state(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (time_after(jiffies, state->next_status_check)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) deb_info("REFRESH STATE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (af9005_get_statistic(fe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) err("get_statistic_failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) state->next_status_check = jiffies + 250 * HZ / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int af9005_fe_read_status(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) enum fe_status *stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (fe->ops.tuner_ops.release == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = af9005_read_register_bits(state->d, xd_p_agc_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) agc_lock_pos, agc_lock_len, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) *stat |= FE_HAS_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ret = af9005_read_register_bits(state->d, xd_p_fd_tpsd_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) fd_tpsd_lock_pos, fd_tpsd_lock_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *stat |= FE_HAS_CARRIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = af9005_read_register_bits(state->d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) xd_r_mp2if_sync_byte_locked,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mp2if_sync_byte_locked_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mp2if_sync_byte_locked_pos, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) *stat |= FE_HAS_SYNC | FE_HAS_VITERBI | FE_HAS_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (state->opened)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) af9005_led_control(state->d, *stat & FE_HAS_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) af9005_read_register_bits(state->d, xd_p_reg_strong_sginal_detected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) reg_strong_sginal_detected_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) reg_strong_sginal_detected_len, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (temp != state->strong) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) deb_info("adjust for strong signal %d\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) state->strong = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int af9005_fe_read_ber(struct dvb_frontend *fe, u32 * ber)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (fe->ops.tuner_ops.release == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) af9005_fe_refresh_state(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) *ber = state->ber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int af9005_fe_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (fe->ops.tuner_ops.release == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) af9005_fe_refresh_state(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) *unc = state->unc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int af9005_fe_read_signal_strength(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u16 * strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 if_gain, rf_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (fe->ops.tuner_ops.release == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) af9005_read_ofdm_register(state->d, xd_r_reg_aagc_rf_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) &rf_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) af9005_read_ofdm_register(state->d, xd_r_reg_aagc_if_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &if_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* this value has no real meaning, but i don't have the tables that relate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) the rf and if gain with the dbm, so I just scale the value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) *strength = (512 - rf_gain - if_gain) << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int af9005_fe_read_snr(struct dvb_frontend *fe, u16 * snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* the snr can be derived from the ber and the modulation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) but I don't think this kind of complex calculations belong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) in the driver. I may be wrong.... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int af9005_fe_program_cfoe(struct dvb_usb_device *d, u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u8 temp0, temp1, temp2, temp3, buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 NS_coeff1_2048Nu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 NS_coeff1_8191Nu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 NS_coeff1_8192Nu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 NS_coeff1_8193Nu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 NS_coeff2_2k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 NS_coeff2_8k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) switch (bw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) NS_coeff1_2048Nu = 0x2ADB6DC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) NS_coeff1_8191Nu = 0xAB7313;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) NS_coeff1_8192Nu = 0xAB6DB7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) NS_coeff1_8193Nu = 0xAB685C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) NS_coeff2_2k = 0x156DB6E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) NS_coeff2_8k = 0x55B6DC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) NS_coeff1_2048Nu = 0x3200001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) NS_coeff1_8191Nu = 0xC80640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) NS_coeff1_8192Nu = 0xC80000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) NS_coeff1_8193Nu = 0xC7F9C0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) NS_coeff2_2k = 0x1900000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) NS_coeff2_8k = 0x640000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) NS_coeff1_2048Nu = 0x3924926;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) NS_coeff1_8191Nu = 0xE4996E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) NS_coeff1_8192Nu = 0xE49249;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) NS_coeff1_8193Nu = 0xE48B25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) NS_coeff2_2k = 0x1C92493;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) NS_coeff2_8k = 0x724925;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) err("Invalid bandwidth %d.", bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * write NS_coeff1_2048Nu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) temp0 = (u8) (NS_coeff1_2048Nu & 0x000000FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) temp1 = (u8) ((NS_coeff1_2048Nu & 0x0000FF00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) temp2 = (u8) ((NS_coeff1_2048Nu & 0x00FF0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) temp3 = (u8) ((NS_coeff1_2048Nu & 0x03000000) >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* big endian to make 8051 happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) buf[0] = temp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) buf[1] = temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) buf[2] = temp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) buf[3] = temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* cfoe_NS_2k_coeff1_25_24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = af9005_write_ofdm_register(d, 0xAE00, buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* cfoe_NS_2k_coeff1_23_16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = af9005_write_ofdm_register(d, 0xAE01, buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* cfoe_NS_2k_coeff1_15_8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ret = af9005_write_ofdm_register(d, 0xAE02, buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* cfoe_NS_2k_coeff1_7_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = af9005_write_ofdm_register(d, 0xAE03, buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * write NS_coeff2_2k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) temp0 = (u8) ((NS_coeff2_2k & 0x0000003F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) temp1 = (u8) ((NS_coeff2_2k & 0x00003FC0) >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) temp2 = (u8) ((NS_coeff2_2k & 0x003FC000) >> 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) temp3 = (u8) ((NS_coeff2_2k & 0x01C00000) >> 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* big endian to make 8051 happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) buf[0] = temp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) buf[1] = temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) buf[2] = temp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) buf[3] = temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = af9005_write_ofdm_register(d, 0xAE04, buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret = af9005_write_ofdm_register(d, 0xAE05, buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = af9005_write_ofdm_register(d, 0xAE06, buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ret = af9005_write_ofdm_register(d, 0xAE07, buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * write NS_coeff1_8191Nu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) temp0 = (u8) ((NS_coeff1_8191Nu & 0x000000FF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) temp1 = (u8) ((NS_coeff1_8191Nu & 0x0000FF00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) temp2 = (u8) ((NS_coeff1_8191Nu & 0x00FFC000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) temp3 = (u8) ((NS_coeff1_8191Nu & 0x03000000) >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* big endian to make 8051 happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) buf[0] = temp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) buf[1] = temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) buf[2] = temp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) buf[3] = temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret = af9005_write_ofdm_register(d, 0xAE08, buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = af9005_write_ofdm_register(d, 0xAE09, buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = af9005_write_ofdm_register(d, 0xAE0A, buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = af9005_write_ofdm_register(d, 0xAE0B, buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * write NS_coeff1_8192Nu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) temp0 = (u8) (NS_coeff1_8192Nu & 0x000000FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) temp1 = (u8) ((NS_coeff1_8192Nu & 0x0000FF00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) temp2 = (u8) ((NS_coeff1_8192Nu & 0x00FFC000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) temp3 = (u8) ((NS_coeff1_8192Nu & 0x03000000) >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* big endian to make 8051 happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) buf[0] = temp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) buf[1] = temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) buf[2] = temp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) buf[3] = temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = af9005_write_ofdm_register(d, 0xAE0C, buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret = af9005_write_ofdm_register(d, 0xAE0D, buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = af9005_write_ofdm_register(d, 0xAE0E, buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = af9005_write_ofdm_register(d, 0xAE0F, buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * write NS_coeff1_8193Nu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) temp0 = (u8) ((NS_coeff1_8193Nu & 0x000000FF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) temp1 = (u8) ((NS_coeff1_8193Nu & 0x0000FF00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) temp2 = (u8) ((NS_coeff1_8193Nu & 0x00FFC000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) temp3 = (u8) ((NS_coeff1_8193Nu & 0x03000000) >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* big endian to make 8051 happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) buf[0] = temp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) buf[1] = temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) buf[2] = temp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) buf[3] = temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = af9005_write_ofdm_register(d, 0xAE10, buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ret = af9005_write_ofdm_register(d, 0xAE11, buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = af9005_write_ofdm_register(d, 0xAE12, buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = af9005_write_ofdm_register(d, 0xAE13, buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * write NS_coeff2_8k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) temp0 = (u8) ((NS_coeff2_8k & 0x0000003F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) temp1 = (u8) ((NS_coeff2_8k & 0x00003FC0) >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) temp2 = (u8) ((NS_coeff2_8k & 0x003FC000) >> 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) temp3 = (u8) ((NS_coeff2_8k & 0x01C00000) >> 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* big endian to make 8051 happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) buf[0] = temp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) buf[1] = temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) buf[2] = temp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) buf[3] = temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = af9005_write_ofdm_register(d, 0xAE14, buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = af9005_write_ofdm_register(d, 0xAE15, buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = af9005_write_ofdm_register(d, 0xAE16, buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = af9005_write_ofdm_register(d, 0xAE17, buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int af9005_fe_select_bw(struct dvb_usb_device *d, u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) switch (bw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) temp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) temp = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) err("Invalid bandwidth %d.", bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return af9005_write_register_bits(d, xd_g_reg_bw, reg_bw_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) reg_bw_len, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int af9005_fe_power(struct dvb_frontend *fe, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u8 temp = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) deb_info("power %s tuner\n", on ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static struct mt2060_config af9005_mt2060_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static struct qt1010_config af9005_qt1010_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static int af9005_fe_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct dvb_usb_adapter *adap = fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int ret, i, scriptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u8 temp, temp0 = 0, temp1 = 0, temp2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u16 if1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) deb_info("in af9005_fe_init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) deb_info("reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if ((ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 4, 1, 0x01)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if ((ret = af9005_write_ofdm_register(state->d, APO_REG_RESET, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* clear ofdm reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) deb_info("clear ofdm reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) for (i = 0; i < 150; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if ((ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) af9005_read_ofdm_register(state->d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) xd_I2C_reg_ofdm_rst, &temp)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (temp & (regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (i == 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /*FIXME in the dump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) write B200 A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) write xd_g_reg_ofsm_clk 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) read eepr c6 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) read eepr c7 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) misc ctrl 3 -> 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) read eepr ca (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) write xd_g_reg_ofsm_clk 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) write B200 a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) temp = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) temp = regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if ((ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) reg_ofdm_rst_pos, reg_ofdm_rst_len, 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) reg_ofdm_rst_pos, reg_ofdm_rst_len, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* don't know what register aefc is, but this is what the windows driver does */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ret = af9005_write_ofdm_register(state->d, 0xaefc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* set stand alone chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) deb_info("set stand alone chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if ((ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) af9005_write_register_bits(state->d, xd_p_reg_dca_stand_alone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) reg_dca_stand_alone_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) reg_dca_stand_alone_len, 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* set dca upper & lower chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) deb_info("set dca upper & lower chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if ((ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) af9005_write_register_bits(state->d, xd_p_reg_dca_upper_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) reg_dca_upper_chip_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) reg_dca_upper_chip_len, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if ((ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) af9005_write_register_bits(state->d, xd_p_reg_dca_lower_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) reg_dca_lower_chip_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) reg_dca_lower_chip_len, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* set 2wire master clock to 0x14 (for 60KHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) deb_info("set 2wire master clock to 0x14 (for 60KHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if ((ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) af9005_write_ofdm_register(state->d, xd_I2C_i2c_m_period, 0x14)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* clear dca enable chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) deb_info("clear dca enable chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if ((ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) af9005_write_register_bits(state->d, xd_p_reg_dca_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) reg_dca_en_pos, reg_dca_en_len, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* FIXME these are register bits, but I don't know which ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = af9005_write_ofdm_register(state->d, 0xa16c, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ret = af9005_write_ofdm_register(state->d, 0xa3c1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* init other parameters: program cfoe and select bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) deb_info("program cfoe\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ret = af9005_fe_program_cfoe(state->d, 6000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* set read-update bit for modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) deb_info("set read-update bit for modulation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if ((ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) af9005_write_register_bits(state->d, xd_p_reg_feq_read_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) reg_feq_read_update_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) reg_feq_read_update_len, 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* sample code has a set MPEG TS code here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) but sniffing reveals that it doesn't do it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* set read-update bit to 1 for DCA modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) deb_info("set read-update bit 1 for DCA modulation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if ((ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) af9005_write_register_bits(state->d, xd_p_reg_dca_read_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) reg_dca_read_update_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) reg_dca_read_update_len, 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* enable fec monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) deb_info("enable fec monitor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if ((ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) af9005_write_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) fec_vtb_rsd_mon_en_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) fec_vtb_rsd_mon_en_len, 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* FIXME should be register bits, I don't know which ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = af9005_write_ofdm_register(state->d, 0xa601, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* set api_retrain_never_freeze */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) deb_info("set api_retrain_never_freeze\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* load init script */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) deb_info("load init script\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) scriptlen = sizeof(script) / sizeof(RegDesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) for (i = 0; i < scriptlen; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if ((ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) af9005_write_register_bits(state->d, script[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) script[i].pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) script[i].len, script[i].val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* save 3 bytes of original fcw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (script[i].reg == 0xae18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) temp2 = script[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (script[i].reg == 0xae19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) temp1 = script[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (script[i].reg == 0xae1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) temp0 = script[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* save original unplug threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (script[i].reg == xd_p_reg_unplug_th)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) state->original_if_unplug_th = script[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (script[i].reg == xd_p_reg_unplug_rf_gain_th)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) state->original_rf_unplug_th = script[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (script[i].reg == xd_p_reg_unplug_dtop_if_gain_th)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) state->original_dtop_if_unplug_th = script[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (script[i].reg == xd_p_reg_unplug_dtop_rf_gain_th)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) state->original_dtop_rf_unplug_th = script[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) state->original_fcw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ((u32) temp2 << 16) + ((u32) temp1 << 8) + (u32) temp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* save original TOPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) deb_info("save original TOPs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* RF TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) af9005_read_word_agc(state->d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) xd_p_reg_aagc_rf_top_numerator_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) &state->original_rf_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* IF TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) af9005_read_word_agc(state->d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) xd_p_reg_aagc_if_top_numerator_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) &state->original_if_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* ACI 0 IF TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) af9005_read_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) &state->original_aci0_if_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* ACI 1 IF TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) af9005_read_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) &state->original_aci1_if_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* attach tuner and init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (fe->ops.tuner_ops.release == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* read tuner and board id from eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ret = af9005_read_eeprom(adap->dev, 0xc6, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) err("Impossible to read EEPROM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) deb_info("Tuner id %d, board id %d\n", buf[0], buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) switch (buf[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) case 2: /* MT2060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* read if1 from eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = af9005_read_eeprom(adap->dev, 0xc8, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) err("Impossible to read EEPROM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if1 = (u16) (buf[0] << 8) + buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (dvb_attach(mt2060_attach, fe, &adap->dev->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) &af9005_mt2060_config, if1) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) deb_info("MT2060 attach failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) case 3: /* QT1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) case 9: /* QT1010B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (dvb_attach(qt1010_attach, fe, &adap->dev->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) &af9005_qt1010_config) ==NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) deb_info("QT1010 attach failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) err("Unsupported tuner type %d", buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ret = fe->ops.tuner_ops.init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) deb_info("profit!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static int af9005_fe_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return af9005_fe_power(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static int af9005_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (acquire) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) state->opened++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) state->opened--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (!state->opened)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) af9005_led_control(state->d, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static int af9005_fe_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) u8 temp, temp0, temp1, temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) deb_info("af9005_fe_set_frontend freq %d bw %d\n", fep->frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) fep->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (fe->ops.tuner_ops.release == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) err("Tuner not attached");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) deb_info("turn off led\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* not in the log */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ret = af9005_led_control(state->d, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* not sure about the bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ret = af9005_write_register_bits(state->d, XD_MP2IF_MISC, 2, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /* set FCW to default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) deb_info("set FCW to default value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) temp0 = (u8) (state->original_fcw & 0x000000ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) temp1 = (u8) ((state->original_fcw & 0x0000ff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) temp2 = (u8) ((state->original_fcw & 0x00ff0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ret = af9005_write_ofdm_register(state->d, 0xae1a, temp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ret = af9005_write_ofdm_register(state->d, 0xae19, temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret = af9005_write_ofdm_register(state->d, 0xae18, temp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* restore original TOPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) deb_info("restore original TOPs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) af9005_write_word_agc(state->d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) xd_p_reg_aagc_rf_top_numerator_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) state->original_rf_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) af9005_write_word_agc(state->d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) xd_p_reg_aagc_if_top_numerator_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) state->original_if_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) af9005_write_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) state->original_aci0_if_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) af9005_write_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) state->original_aci1_if_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* select bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) deb_info("select bandwidth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ret = af9005_fe_select_bw(state->d, fep->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ret = af9005_fe_program_cfoe(state->d, fep->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* clear easy mode flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) deb_info("clear easy mode flag\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ret = af9005_write_ofdm_register(state->d, 0xaefd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* set unplug threshold to original value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) deb_info("set unplug threshold to original value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) af9005_write_ofdm_register(state->d, xd_p_reg_unplug_th,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) state->original_if_unplug_th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* set tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) deb_info("set tuner\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ret = fe->ops.tuner_ops.set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* trigger ofsm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) deb_info("trigger ofsm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ret = af9005_write_tuner_registers(state->d, 0xffff, &temp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /* clear retrain and freeze flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) deb_info("clear retrain and freeze flag\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) af9005_write_register_bits(state->d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) xd_p_reg_api_retrain_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) reg_api_retrain_request_pos, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* reset pre viterbi and post viterbi registers and statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) af9005_reset_pre_viterbi(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) af9005_reset_post_viterbi(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) state->pre_vit_error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) state->pre_vit_bit_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) state->ber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) state->post_vit_error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* state->unc = 0; commented out since it should be ever increasing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) state->abort_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) state->next_status_check = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) state->strong = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static int af9005_fe_get_frontend(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct dtv_frontend_properties *fep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct af9005_fe_state *state = fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /* mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) reg_tpsd_const_pos, reg_tpsd_const_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) deb_info("===== fe_get_frontend_legacy = =============\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) deb_info("CONSTELLATION ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) switch (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) fep->modulation = QPSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) deb_info("QPSK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) fep->modulation = QAM_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) deb_info("QAM_16\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) fep->modulation = QAM_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) deb_info("QAM_64\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* tps hierarchy and alpha value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) af9005_read_register_bits(state->d, xd_g_reg_tpsd_hier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) reg_tpsd_hier_pos, reg_tpsd_hier_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) deb_info("HIERARCHY ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) switch (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) fep->hierarchy = HIERARCHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) deb_info("NONE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) fep->hierarchy = HIERARCHY_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) deb_info("1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) fep->hierarchy = HIERARCHY_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) deb_info("2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) fep->hierarchy = HIERARCHY_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) deb_info("4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* high/low priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) af9005_read_register_bits(state->d, xd_g_reg_dec_pri,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) reg_dec_pri_pos, reg_dec_pri_len, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* if temp is set = high priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) deb_info("PRIORITY %s\n", temp ? "high" : "low");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* high coderate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) af9005_read_register_bits(state->d, xd_g_reg_tpsd_hpcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) deb_info("CODERATE HP ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) switch (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) fep->code_rate_HP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) deb_info("FEC_1_2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) fep->code_rate_HP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) deb_info("FEC_2_3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) fep->code_rate_HP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) deb_info("FEC_3_4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) fep->code_rate_HP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) deb_info("FEC_5_6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) fep->code_rate_HP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) deb_info("FEC_7_8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* low coderate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) af9005_read_register_bits(state->d, xd_g_reg_tpsd_lpcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) deb_info("CODERATE LP ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) switch (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) fep->code_rate_LP = FEC_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) deb_info("FEC_1_2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) fep->code_rate_LP = FEC_2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) deb_info("FEC_2_3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) fep->code_rate_LP = FEC_3_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) deb_info("FEC_3_4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) fep->code_rate_LP = FEC_5_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) deb_info("FEC_5_6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) fep->code_rate_LP = FEC_7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) deb_info("FEC_7_8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /* guard interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) af9005_read_register_bits(state->d, xd_g_reg_tpsd_gi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) reg_tpsd_gi_pos, reg_tpsd_gi_len, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) deb_info("GUARD INTERVAL ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) switch (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) fep->guard_interval = GUARD_INTERVAL_1_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) deb_info("1_32\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) fep->guard_interval = GUARD_INTERVAL_1_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) deb_info("1_16\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) fep->guard_interval = GUARD_INTERVAL_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) deb_info("1_8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) fep->guard_interval = GUARD_INTERVAL_1_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) deb_info("1_4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /* fft */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) deb_info("TRANSMISSION MODE ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) switch (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) fep->transmission_mode = TRANSMISSION_MODE_2K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) deb_info("2K\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) fep->transmission_mode = TRANSMISSION_MODE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) deb_info("8K\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) af9005_read_register_bits(state->d, xd_g_reg_bw, reg_bw_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) reg_bw_len, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) deb_info("BANDWIDTH ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) switch (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) fep->bandwidth_hz = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) deb_info("6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) fep->bandwidth_hz = 7000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) deb_info("7\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) fep->bandwidth_hz = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) deb_info("8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static void af9005_fe_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) struct af9005_fe_state *state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) (struct af9005_fe_state *)fe->demodulator_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static const struct dvb_frontend_ops af9005_fe_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) struct af9005_fe_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* allocate memory for the internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) state = kzalloc(sizeof(struct af9005_fe_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) deb_info("attaching frontend af9005\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) state->d = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) state->opened = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) memcpy(&state->frontend.ops, &af9005_fe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) sizeof(struct dvb_frontend_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) state->frontend.demodulator_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return &state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static const struct dvb_frontend_ops af9005_fe_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .delsys = { SYS_DVBT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .name = "AF9005 USB DVB-T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .frequency_min_hz = 44250 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .frequency_max_hz = 867250 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .frequency_stepsize_hz = 250 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .caps = FE_CAN_INVERSION_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) FE_CAN_HIERARCHY_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .release = af9005_fe_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .init = af9005_fe_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .sleep = af9005_fe_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .ts_bus_ctrl = af9005_ts_bus_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .set_frontend = af9005_fe_set_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .get_frontend = af9005_fe_get_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .read_status = af9005_fe_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .read_ber = af9005_fe_read_ber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .read_signal_strength = af9005_fe_read_signal_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .read_snr = af9005_fe_read_snr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .read_ucblocks = af9005_fe_read_unc_blocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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