Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Realtek RTL28xxU DVB USB driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef RTL28XXU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define RTL28XXU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "dvb_usb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "rtl2830.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "rtl2832.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "rtl2832_sdr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "mn88472.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "mn88473.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "cxd2841er.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "qt1010.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "mt2060.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "mxl5005s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "fc0012.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "fc0013.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include "e4000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include "fc2580.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include "tua9001.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include "r820t.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include "si2168.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include "si2157.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * USB commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * (usb_control_msg() index parameter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DEMOD            0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define USB              0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SYS              0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define I2C              0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define I2C_DA           0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CMD_WR_FLAG      0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CMD_DEMOD_RD     0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CMD_DEMOD_WR     0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CMD_USB_RD       0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CMD_USB_WR       0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CMD_SYS_RD       0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CMD_IR_RD        0x0201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CMD_IR_WR        0x0211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CMD_SYS_WR       0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CMD_I2C_RD       0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CMD_I2C_WR       0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CMD_I2C_DA_RD    0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CMD_I2C_DA_WR    0x0610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) struct rtl28xxu_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u8 buf[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u8 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u8 tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	char *tuner_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u8 page; /* integrated demod active register page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct i2c_adapter *demod_i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	bool rc_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	bool new_i2c_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct i2c_client *i2c_client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct i2c_client *i2c_client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct i2c_client *i2c_client_slave_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct platform_device *platform_device_sdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	#define SLAVE_DEMOD_NONE           0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	#define SLAVE_DEMOD_MN88472        1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	#define SLAVE_DEMOD_MN88473        2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	#define SLAVE_DEMOD_SI2168         3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	#define SLAVE_DEMOD_CXD2837ER      4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned int slave_demod:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		struct rtl2830_platform_data rtl2830_platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		struct rtl2832_platform_data rtl2832_platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) enum rtl28xxu_chip_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	CHIP_ID_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	CHIP_ID_RTL2831U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	CHIP_ID_RTL2832U,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* XXX: Hack. This must be keep sync with rtl2832 demod driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) enum rtl28xxu_tuner {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	TUNER_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	TUNER_RTL2830_QT1010          = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	TUNER_RTL2830_MT2060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	TUNER_RTL2830_MXL5005S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	TUNER_RTL2832_MT2266          = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	TUNER_RTL2832_FC2580,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	TUNER_RTL2832_MT2063,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	TUNER_RTL2832_MAX3543,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	TUNER_RTL2832_TUA9001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	TUNER_RTL2832_MXL5007T,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	TUNER_RTL2832_FC0012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	TUNER_RTL2832_E4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	TUNER_RTL2832_TDA18272,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	TUNER_RTL2832_FC0013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	TUNER_RTL2832_R820T,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	TUNER_RTL2832_R828D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	TUNER_RTL2832_SI2157,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct rtl28xxu_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u16 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct rtl28xxu_reg_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct rtl28xxu_reg_val_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * memory map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * 0x0000 DEMOD : demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  * 0x2000 USB   : SIE, USB endpoint, debug, DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  * 0x3000 SYS   : system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * 0xfc00 RC    : remote controller (not RTL2831U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * USB registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* SIE Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define USB_SYSCTL         0x2000 /* USB system control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define USB_SYSCTL_0       0x2000 /* USB system control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define USB_SYSCTL_1       0x2001 /* USB system control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define USB_SYSCTL_2       0x2002 /* USB system control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define USB_SYSCTL_3       0x2003 /* USB system control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define USB_IRQSTAT        0x2008 /* SIE interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define USB_IRQEN          0x200C /* SIE interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define USB_CTRL           0x2010 /* USB control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define USB_STAT           0x2014 /* USB status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define USB_DEVADDR        0x2018 /* USB device address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define USB_TEST           0x201C /* USB test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define USB_FRAME_NUMBER   0x2020 /* frame number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define USB_FIFO_ADDR      0x2028 /* address of SIE FIFO RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define USB_FIFO_CMD       0x202A /* SIE FIFO RAM access command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define USB_FIFO_DATA      0x2030 /* SIE FIFO RAM data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Endpoint Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define EP0_SETUPA         0x20F8 /* EP 0 setup packet lower byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define EP0_SETUPB         0x20FC /* EP 0 setup packet higher byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define USB_EP0_CFG        0x2104 /* EP 0 configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define USB_EP0_CTL        0x2108 /* EP 0 control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define USB_EP0_STAT       0x210C /* EP 0 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define USB_EP0_IRQSTAT    0x2110 /* EP 0 interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define USB_EP0_IRQEN      0x2114 /* EP 0 interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define USB_EP0_MAXPKT     0x2118 /* EP 0 max packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define USB_EP0_BC         0x2120 /* EP 0 FIFO byte counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define USB_EPA_CFG        0x2144 /* EP A configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define USB_EPA_CFG_0      0x2144 /* EP A configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define USB_EPA_CFG_1      0x2145 /* EP A configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define USB_EPA_CFG_2      0x2146 /* EP A configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define USB_EPA_CFG_3      0x2147 /* EP A configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define USB_EPA_CTL        0x2148 /* EP A control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define USB_EPA_CTL_0      0x2148 /* EP A control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define USB_EPA_CTL_1      0x2149 /* EP A control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define USB_EPA_CTL_2      0x214A /* EP A control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define USB_EPA_CTL_3      0x214B /* EP A control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define USB_EPA_STAT       0x214C /* EP A status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define USB_EPA_IRQSTAT    0x2150 /* EP A interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define USB_EPA_IRQEN      0x2154 /* EP A interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define USB_EPA_MAXPKT     0x2158 /* EP A max packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define USB_EPA_MAXPKT_0   0x2158 /* EP A max packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define USB_EPA_MAXPKT_1   0x2159 /* EP A max packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define USB_EPA_MAXPKT_2   0x215A /* EP A max packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define USB_EPA_MAXPKT_3   0x215B /* EP A max packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define USB_EPA_FIFO_CFG   0x2160 /* EP A FIFO configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define USB_EPA_FIFO_CFG_0 0x2160 /* EP A FIFO configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define USB_EPA_FIFO_CFG_1 0x2161 /* EP A FIFO configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define USB_EPA_FIFO_CFG_2 0x2162 /* EP A FIFO configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define USB_EPA_FIFO_CFG_3 0x2163 /* EP A FIFO configure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Debug Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define USB_PHYTSTDIS      0x2F04 /* PHY test disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define USB_TOUT_VAL       0x2F08 /* USB time-out time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define USB_VDRCTRL        0x2F10 /* UTMI vendor signal control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define USB_VSTAIN         0x2F14 /* UTMI vendor signal status in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define USB_VLOADM         0x2F18 /* UTMI load vendor signal status in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define USB_VSTAOUT        0x2F1C /* UTMI vendor signal status out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define USB_UTMI_TST       0x2F80 /* UTMI test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define USB_UTMI_STATUS    0x2F84 /* UTMI status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define USB_TSTCTL         0x2F88 /* test control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define USB_TSTCTL2        0x2F8C /* test control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define USB_PID_FORCE      0x2F90 /* force PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define USB_PKTERR_CNT     0x2F94 /* packet error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define USB_RXERR_CNT      0x2F98 /* RX error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define USB_MEM_BIST       0x2F9C /* MEM BIST test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define USB_SLBBIST        0x2FA0 /* self-loop-back BIST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define USB_CNTTEST        0x2FA4 /* counter test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define USB_PHYTST         0x2FC0 /* USB PHY test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define USB_DBGIDX         0x2FF0 /* select individual block debug signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define USB_DBGMUX         0x2FF4 /* debug signal module mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * SYS registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* demod control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SYS_SYS0           0x3000 /* include DEMOD_CTL, GPO, GPI, GPOE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SYS_DEMOD_CTL      0x3000 /* control register for DVB-T demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* GPIO registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SYS_GPIO_OUT_VAL   0x3001 /* output value of GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SYS_GPIO_IN_VAL    0x3002 /* input value of GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SYS_GPIO_OUT_EN    0x3003 /* output enable of GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SYS_SYS1           0x3004 /* include GPD, SYSINTE, SYSINTS, GP_CFG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SYS_GPIO_DIR       0x3004 /* direction control for GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SYS_SYSINTE        0x3005 /* system interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SYS_SYSINTS        0x3006 /* system interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SYS_GPIO_CFG0      0x3007 /* PAD configuration for GPIO0-GPIO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SYS_SYS2           0x3008 /* include GP_CFG1 and 3 reserved bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SYS_GPIO_CFG1      0x3008 /* PAD configuration for GPIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SYS_DEMOD_CTL1     0x300B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* IrDA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SYS_IRRC_PSR       0x3020 /* IR protocol selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SYS_IRRC_PER       0x3024 /* IR protocol extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SYS_IRRC_SF        0x3028 /* IR sampling frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SYS_IRRC_DPIR      0x302C /* IR data package interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SYS_IRRC_CR        0x3030 /* IR control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SYS_IRRC_RP        0x3034 /* IR read port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SYS_IRRC_SR        0x3038 /* IR status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* I2C master registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SYS_I2CCR          0x3040 /* I2C clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SYS_I2CMCR         0x3044 /* I2C master control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SYS_I2CMSTR        0x3048 /* I2C master SCL timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SYS_I2CMSR         0x304C /* I2C master status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SYS_I2CMFR         0x3050 /* I2C master FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * IR registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IR_RX_BUF          0xFC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IR_RX_IE           0xFD00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IR_RX_IF           0xFD01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IR_RX_CTRL         0xFD02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IR_RX_CFG          0xFD03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IR_MAX_DURATION0   0xFD04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IR_MAX_DURATION1   0xFD05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IR_IDLE_LEN0       0xFD06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IR_IDLE_LEN1       0xFD07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IR_GLITCH_LEN      0xFD08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IR_RX_BUF_CTRL     0xFD09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IR_RX_BUF_DATA     0xFD0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IR_RX_BC           0xFD0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IR_RX_CLK          0xFD0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IR_RX_C_COUNT_L    0xFD0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IR_RX_C_COUNT_H    0xFD0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IR_SUSPEND_CTRL    0xFD10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IR_ERR_TOL_CTRL    0xFD11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IR_UNIT_LEN        0xFD12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IR_ERR_TOL_LEN     0xFD13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IR_MAX_H_TOL_LEN   0xFD14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IR_MAX_L_TOL_LEN   0xFD15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IR_MASK_CTRL       0xFD16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IR_MASK_DATA       0xFD17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IR_RES_MASK_ADDR   0xFD18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IR_RES_MASK_T_LEN  0xFD19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #endif