^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010-2014 Michael Krufky (mkrufky@linuxtv.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DVB_USB_MXL111SF_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DVB_USB_MXL111SF_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifdef DVB_USB_LOG_PREFIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #undef DVB_USB_LOG_PREFIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DVB_USB_LOG_PREFIX "mxl111sf"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "dvb_usb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <media/tveeprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Max transfer size done by I2C transfer functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MXL_MAX_XFER_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MXL_EP1_REG_READ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MXL_EP2_REG_WRITE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MXL_EP3_INTERRUPT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MXL_EP4_MPEG2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MXL_EP5_I2S 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MXL_EP6_656 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MXL_EP6_MPEG2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifdef USING_ENUM_mxl111sf_current_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum mxl111sf_current_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) mxl_mode_dvbt = MXL_EP4_MPEG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) mxl_mode_mh = MXL_EP5_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) mxl_mode_atsc = MXL_EP6_MPEG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum mxl111sf_gpio_port_expander {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) mxl111sf_gpio_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) mxl111sf_PCA9534,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct mxl111sf_adap_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int alt_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int gpio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int device_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int ep6_clockphase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int (*fe_init)(struct dvb_frontend *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int (*fe_sleep)(struct dvb_frontend *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) enum mxl111sf_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MXL111SF_PAD_RF_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MXL111SF_PAD_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MXL111SF_NUM_PADS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct mxl111sf_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct dvb_usb_device *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum mxl111sf_gpio_port_expander gpio_port_expander;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 port_expander_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 chip_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MXL111SF_V6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MXL111SF_V8_100 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MXL111SF_V8_200 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 chip_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifdef USING_ENUM_mxl111sf_current_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) enum mxl111sf_current_mode current_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MXL_TUNER_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MXL_SOC_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MXL_DEV_MODE_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int device_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* use usb alt setting 1 for EP4 ISOC transfer (dvb-t),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) EP5 BULK transfer (atsc-mh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) EP6 BULK transfer (atsc/qam),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) use usb alt setting 2 for EP4 BULK transfer (dvb-t),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) EP5 ISOC transfer (atsc-mh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) EP6 ISOC transfer (atsc/qam),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int alt_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int gpio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct tveeprom tv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct mutex fe_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 num_frontends;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct mxl111sf_adap_state adap_state[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 sndbuf[MXL_MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 rcvbuf[MXL_MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct mutex msg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifdef CONFIG_MEDIA_CONTROLLER_DVB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct media_entity tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct media_pad tuner_pads[MXL111SF_NUM_PADS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int mxl111sf_read_reg(struct mxl111sf_state *state, u8 addr, u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int mxl111sf_write_reg(struct mxl111sf_state *state, u8 addr, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct mxl111sf_reg_ctrl_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int mxl111sf_write_reg_mask(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 addr, u8 mask, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int mxl111sf_ctrl_program_regs(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct mxl111sf_reg_ctrl_info *ctrl_reg_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* needed for hardware i2c functions in mxl111sf-i2c.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * mxl111sf_i2c_send_data / mxl111sf_i2c_get_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int mxl111sf_ctrl_msg(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 cmd, u8 *wbuf, int wlen, u8 *rbuf, int rlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define mxl_printk(kern, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) printk(kern "%s: " fmt "\n", __func__, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define mxl_info(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mxl_printk(KERN_INFO, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) extern int dvb_usb_mxl111sf_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define mxl_debug(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (dvb_usb_mxl111sf_debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mxl_printk(KERN_DEBUG, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MXL_I2C_DBG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MXL_ADV_DBG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define mxl_debug_adv(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (dvb_usb_mxl111sf_debug & MXL_ADV_DBG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mxl_printk(KERN_DEBUG, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define mxl_i2c(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (dvb_usb_mxl111sf_debug & MXL_I2C_DBG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mxl_printk(KERN_DEBUG, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define mxl_i2c_adv(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if ((dvb_usb_mxl111sf_debug & (MXL_I2C_DBG | MXL_ADV_DBG)) == \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) (MXL_I2C_DBG | MXL_ADV_DBG)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mxl_printk(KERN_DEBUG, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* The following allows the mxl_fail() macro defined below to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * in externel modules, such as mxl111sf-tuner.ko, even though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * dvb_usb_mxl111sf_debug is not defined within those modules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #if (defined(__MXL111SF_TUNER_H__)) || (defined(__MXL111SF_DEMOD_H__))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MXL_ADV_DEBUG_ENABLED MXL_ADV_DBG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MXL_ADV_DEBUG_ENABLED dvb_usb_mxl111sf_debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define mxl_fail(ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int __ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __ret = (ret < 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if ((__ret) && (MXL_ADV_DEBUG_ENABLED & MXL_ADV_DBG)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mxl_printk(KERN_ERR, "error %d on line %d", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret, __LINE__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif /* _DVB_USB_MXL111SF_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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