^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mxl111sf-tuner.c - driver for the MaxLinear MXL111SF CMOS tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2014 Michael Krufky <mkrufky@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "mxl111sf-tuner.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "mxl111sf-phy.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "mxl111sf-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static int mxl111sf_tuner_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) module_param_named(debug, mxl111sf_tuner_debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define mxl_dbg(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) if (mxl111sf_tuner_debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) mxl_printk(KERN_DEBUG, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct mxl111sf_tuner_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct mxl111sf_state *mxl_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) const struct mxl111sf_tuner_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum mxl_if_freq if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int mxl111sf_tuner_read_reg(struct mxl111sf_tuner_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 addr, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return (state->cfg->read_reg) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) state->cfg->read_reg(state->mxl_state, addr, data) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int mxl111sf_tuner_write_reg(struct mxl111sf_tuner_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return (state->cfg->write_reg) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) state->cfg->write_reg(state->mxl_state, addr, data) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int mxl111sf_tuner_program_regs(struct mxl111sf_tuner_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct mxl111sf_reg_ctrl_info *ctrl_reg_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return (state->cfg->program_regs) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) state->cfg->program_regs(state->mxl_state, ctrl_reg_info) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int mxl1x1sf_tuner_top_master_ctrl(struct mxl111sf_tuner_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return (state->cfg->top_master_ctrl) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) state->cfg->top_master_ctrl(state->mxl_state, onoff) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct mxl111sf_reg_ctrl_info mxl_phy_tune_rf[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {0x1d, 0x7f, 0x00}, /* channel bandwidth section 1/2/3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DIG_MODEINDEX, _A, _CSF, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {0x1e, 0xff, 0x00}, /* channel frequency (lo and fractional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {0x1f, 0xff, 0x00}, /* channel frequency (hi for integer portion) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {0, 0, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct mxl111sf_reg_ctrl_info *mxl111sf_calc_phy_tune_regs(u32 freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 filt_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* set channel bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) switch (bw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case 0: /* ATSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) filt_bw = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case 1: /* QAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) filt_bw = 69;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) filt_bw = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) filt_bw = 42;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) filt_bw = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pr_err("%s: invalid bandwidth setting!", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* calculate RF channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) freq /= 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) freq *= 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* do round */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) freq += 0.5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* set bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mxl_phy_tune_rf[0].data = filt_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* set RF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mxl_phy_tune_rf[1].data = (freq & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mxl_phy_tune_rf[2].data = (freq >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* start tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return mxl_phy_tune_rf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int mxl1x1sf_tuner_set_if_output_freq(struct mxl111sf_tuner_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u16 iffcw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mxl_dbg("(IF polarity = %d, IF freq = 0x%02x)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) state->cfg->invert_spectrum, state->cfg->if_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* set IF polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ctrl = state->cfg->invert_spectrum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ctrl |= state->cfg->if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = mxl111sf_tuner_write_reg(state, V6_TUNER_IF_SEL_REG, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if_freq /= 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* do round */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if_freq += 0.5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (MXL_IF_LO == state->cfg->if_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ctrl = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) iffcw = (u16)(if_freq / (108 * 4096));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) } else if (MXL_IF_HI == state->cfg->if_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ctrl = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) iffcw = (u16)(if_freq / (216 * 4096));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) iffcw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ctrl |= (iffcw >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ret = mxl111sf_tuner_read_reg(state, V6_TUNER_IF_FCW_BYP_REG, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ctrl &= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ctrl |= 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = mxl111sf_tuner_write_reg(state, V6_TUNER_IF_FCW_BYP_REG, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ctrl = iffcw & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = mxl111sf_tuner_write_reg(state, V6_TUNER_IF_FCW_REG, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) state->if_freq = state->cfg->if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int mxl1x1sf_tune_rf(struct dvb_frontend *fe, u32 freq, u8 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct mxl111sf_tuner_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct mxl111sf_reg_ctrl_info *reg_ctrl_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 mxl_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mxl_dbg("(freq = %d, bw = 0x%x)", freq, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* stop tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = mxl111sf_tuner_write_reg(state, START_TUNE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* check device mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = mxl111sf_tuner_read_reg(state, MXL_MODE_REG, &mxl_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Fill out registers for channel tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) reg_ctrl_array = mxl111sf_calc_phy_tune_regs(freq, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!reg_ctrl_array)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = mxl111sf_tuner_program_regs(state, reg_ctrl_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if ((mxl_mode & MXL_DEV_MODE_MASK) == MXL_TUNER_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* IF tuner mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mxl1x1sf_tuner_top_master_ctrl(state, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mxl1x1sf_tuner_top_master_ctrl(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mxl1x1sf_tuner_set_if_output_freq(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = mxl111sf_tuner_write_reg(state, START_TUNE_REG, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (state->cfg->ant_hunt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) state->cfg->ant_hunt(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int mxl1x1sf_tuner_get_lock_status(struct mxl111sf_tuner_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int *rf_synth_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int *ref_synth_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *rf_synth_lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *ref_synth_lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = mxl111sf_tuner_read_reg(state, V6_RF_LOCK_STATUS_REG, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *ref_synth_lock = ((data & 0x03) == 0x03) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *rf_synth_lock = ((data & 0x0c) == 0x0c) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int mxl1x1sf_tuner_loop_thru_ctrl(struct mxl111sf_tuner_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return mxl111sf_tuner_write_reg(state, V6_TUNER_LOOP_THRU_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) onoff ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int mxl111sf_tuner_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 delsys = c->delivery_system;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct mxl111sf_tuner_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u8 bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mxl_dbg("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) switch (delsys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case SYS_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case SYS_ATSCMH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) bw = 0; /* ATSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case SYS_DVBC_ANNEX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bw = 1; /* US CABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) switch (c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) bw = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bw = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) bw = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pr_err("%s: bandwidth not set!", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pr_err("%s: modulation type not supported!", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ret = mxl1x1sf_tune_rf(fe, c->frequency, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) state->frequency = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) state->bandwidth = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int mxl111sf_tuner_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct mxl111sf_tuner_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* wake from standby handled by usb driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int mxl111sf_tuner_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct mxl111sf_tuner_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* enter standby mode handled by usb driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int mxl111sf_tuner_get_status(struct dvb_frontend *fe, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct mxl111sf_tuner_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int rf_locked, ref_locked, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = mxl1x1sf_tuner_get_lock_status(state, &rf_locked, &ref_locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mxl_info("%s%s", rf_locked ? "rf locked " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ref_locked ? "ref locked" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if ((rf_locked) || (ref_locked))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) *status |= TUNER_STATUS_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int mxl111sf_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct mxl111sf_tuner_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u8 val1, val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ret = mxl111sf_tuner_write_reg(state, 0x00, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = mxl111sf_tuner_read_reg(state, V6_DIG_RF_PWR_LSB_REG, &val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = mxl111sf_tuner_read_reg(state, V6_DIG_RF_PWR_MSB_REG, &val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *strength = val1 | ((val2 & 0x07) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = mxl111sf_tuner_write_reg(state, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mxl_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int mxl111sf_tuner_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct mxl111sf_tuner_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *frequency = state->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int mxl111sf_tuner_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct mxl111sf_tuner_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *bandwidth = state->bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int mxl111sf_tuner_get_if_frequency(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct mxl111sf_tuner_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) switch (state->if_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case MXL_IF_4_0: /* 4.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *frequency = 4000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case MXL_IF_4_5: /* 4.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *frequency = 4500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case MXL_IF_4_57: /* 4.57 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *frequency = 4570000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case MXL_IF_5_0: /* 5.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) *frequency = 5000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case MXL_IF_5_38: /* 5.38 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *frequency = 5380000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case MXL_IF_6_0: /* 6.0 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *frequency = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case MXL_IF_6_28: /* 6.28 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) *frequency = 6280000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case MXL_IF_7_2: /* 7.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) *frequency = 7200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case MXL_IF_35_25: /* 35.25 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *frequency = 35250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case MXL_IF_36: /* 36 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *frequency = 36000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case MXL_IF_36_15: /* 36.15 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) *frequency = 36150000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case MXL_IF_44: /* 44 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *frequency = 44000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void mxl111sf_tuner_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct mxl111sf_tuner_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mxl_dbg("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct dvb_tuner_ops mxl111sf_tuner_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .name = "MaxLinear MxL111SF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .frequency_min_hz = ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .frequency_max_hz = ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .frequency_step_hz = ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .init = mxl111sf_tuner_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .sleep = mxl111sf_tuner_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .set_params = mxl111sf_tuner_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .get_status = mxl111sf_tuner_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .get_rf_strength = mxl111sf_get_rf_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .get_frequency = mxl111sf_tuner_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .get_bandwidth = mxl111sf_tuner_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .get_if_frequency = mxl111sf_tuner_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .release = mxl111sf_tuner_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct dvb_frontend *mxl111sf_tuner_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct mxl111sf_state *mxl_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) const struct mxl111sf_tuner_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct mxl111sf_tuner_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) mxl_dbg("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) state = kzalloc(sizeof(struct mxl111sf_tuner_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) state->mxl_state = mxl_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) state->cfg = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) memcpy(&fe->ops.tuner_ops, &mxl111sf_tuner_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) fe->tuner_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) EXPORT_SYMBOL_GPL(mxl111sf_tuner_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MODULE_DESCRIPTION("MaxLinear MxL111SF CMOS tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MODULE_VERSION("0.1");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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