^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mxl111sf-reg.h - driver for the MaxLinear MXL111SF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2014 Michael Krufky <mkrufky@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DVB_USB_MXL111SF_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DVB_USB_MXL111SF_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CHIP_ID_REG 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TOP_CHIP_REV_ID_REG 0xFA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define V6_SNR_RB_LSB_REG 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define V6_SNR_RB_MSB_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define V6_N_ACCUMULATE_REG 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define V6_RS_AVG_ERRORS_LSB_REG 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define V6_RS_AVG_ERRORS_MSB_REG 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define V6_IRQ_STATUS_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IRQ_MASK_FEC_LOCK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define V6_SYNC_LOCK_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SYNC_LOCK_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define V6_RS_LOCK_DET_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RS_LOCK_DET_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define V6_INITACQ_NODETECT_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define V6_FORCE_NFFT_CPSIZE_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define V6_CODE_RATE_TPS_REG 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define V6_CODE_RATE_TPS_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define V6_CP_LOCK_DET_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define V6_CP_LOCK_DET_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define V6_TPS_HIERACHY_REG 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define V6_TPS_HIERARCHY_INFO_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define V6_MODORDER_TPS_REG 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define V6_PARAM_CONSTELLATION_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define V6_MODE_TPS_REG 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define V6_PARAM_FFT_MODE_MASK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define V6_CP_TPS_REG 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define V6_PARAM_GI_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define V6_TPS_LOCK_REG 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define V6_PARAM_TPS_LOCK_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define V6_FEC_PER_COUNT_REG 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define V6_FEC_PER_SCALE_REG 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define V6_FEC_PER_SCALE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define V6_FEC_PER_CLR_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define V6_FEC_PER_CLR_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define V6_PIN_MUX_MODE_REG 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define V6_ENABLE_PIN_MUX 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define V6_I2S_NUM_SAMPLES_REG 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define V6_MPEG_IN_CLK_INV_REG 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define V6_MPEG_IN_CTRL_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define V6_INVERTED_CLK_PHASE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define V6_MPEG_IN_DATA_PARALLEL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define V6_MPEG_IN_DATA_SERIAL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define V6_INVERTED_MPEG_SYNC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define V6_INVERTED_MPEG_VALID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TSIF_INPUT_PARALLEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TSIF_INPUT_SERIAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TSIF_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define V6_MPEG_INOUT_BIT_ORDER_CTRL_REG 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define V6_MPEG_SER_MSB_FIRST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MPEG_SER_MSB_FIRST_ENABLED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define V6_656_I2S_BUFF_STATUS_REG 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define V6_656_OVERFLOW_MASK_BIT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define V6_I2S_OVERFLOW_MASK_BIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define V6_I2S_STREAM_START_BIT_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define V6_I2S_STREAM_END_BIT_REG 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define I2S_RIGHT_JUSTIFIED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define I2S_LEFT_JUSTIFIED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define I2S_DATA_FORMAT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define V6_TUNER_LOOP_THRU_CONTROL_REG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define V6_ENABLE_LOOP_THRU 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TOTAL_NUM_IF_OUTPUT_FREQ 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TUNER_NORMAL_IF_SPECTRUM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TUNER_INVERT_IF_SPECTRUM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define V6_TUNER_IF_SEL_REG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define V6_TUNER_IF_FCW_REG 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define V6_TUNER_IF_FCW_BYP_REG 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define V6_RF_LOCK_STATUS_REG 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define NUM_DIG_TV_CHANNEL 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define V6_DIG_CLK_FREQ_SEL_REG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define V6_REF_SYNTH_INT_REG 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define V6_REF_SYNTH_REMAIN_REG 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define V6_DIG_RFREFSELECT_REG 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define V6_XTAL_CLK_OUT_GAIN_REG 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define V6_TUNER_LOOP_THRU_CTRL_REG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define V6_DIG_XTAL_ENABLE_REG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define V6_DIG_XTAL_BIAS_REG 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define V6_XTAL_CAP_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define V6_GPO_CTRL_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MXL_GPO_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MXL_GPO_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define V6_GPO_0_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define V6_GPO_1_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define V6_111SF_GPO_CTRL_REG 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MXL_111SF_GPO_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MXL_111SF_GPO_2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MXL_111SF_GPO_3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MXL_111SF_GPO_4 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MXL_111SF_GPO_5 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MXL_111SF_GPO_6 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MXL_111SF_GPO_7 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MXL_111SF_GPO_0_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MXL_111SF_GPO_1_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MXL_111SF_GPO_2_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MXL_111SF_GPO_3_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MXL_111SF_GPO_4_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MXL_111SF_GPO_5_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MXL_111SF_GPO_6_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define V6_ATSC_CONFIG_REG 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MXL_MODE_REG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define START_TUNE_REG 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define V6_IDAC_HYSTERESIS_REG 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define V6_IDAC_SETTINGS_REG 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IDAC_MANUAL_CONTROL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IDAC_CURRENT_SINKING_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IDAC_MANUAL_CONTROL_BIT_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IDAC_CURRENT_SINKING_BIT_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define V8_SPI_MODE_REG 0xE9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define V6_DIG_RF_PWR_LSB_REG 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define V6_DIG_RF_PWR_MSB_REG 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif /* _DVB_USB_MXL111SF_REG_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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