^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mxl111sf-i2c.c - driver for the MaxLinear MXL111SF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2014 Michael Krufky <mkrufky@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "mxl111sf-i2c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "mxl111sf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* SW-I2C ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SW_I2C_ADDR 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SW_I2C_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SW_SCL_OUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SW_SDA_OUT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SW_SDA_IN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SW_I2C_BUSY_ADDR 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SW_I2C_BUSY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static int mxl111sf_i2c_bitbang_sendbyte(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u8 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) mxl_i2c("(0x%02x)", byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ret = mxl111sf_read_reg(state, SW_I2C_BUSY_ADDR, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) data = (byte & (0x80 >> i)) ? SW_SDA_OUT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0x10 | SW_I2C_EN | data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 0x10 | SW_I2C_EN | data | SW_SCL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0x10 | SW_I2C_EN | data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* last bit was 0 so we need to release SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (!(byte & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 0x10 | SW_I2C_EN | SW_SDA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* CLK high for ACK readback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0x10 | SW_I2C_EN | SW_SCL_OUT | SW_SDA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = mxl111sf_read_reg(state, SW_I2C_BUSY_ADDR, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* drop the CLK after getting ACK, SDA will go high right away */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0x10 | SW_I2C_EN | SW_SDA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (data & SW_SDA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int mxl111sf_i2c_bitbang_recvbyte(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 *pbyte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 byte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mxl_i2c("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *pbyte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0x10 | SW_I2C_EN | SW_SDA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0x10 | SW_I2C_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SW_SCL_OUT | SW_SDA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = mxl111sf_read_reg(state, SW_I2C_BUSY_ADDR, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (data & SW_SDA_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) byte |= (0x80 >> i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0x10 | SW_I2C_EN | SW_SDA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *pbyte = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int mxl111sf_i2c_start(struct mxl111sf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mxl_i2c("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0x10 | SW_I2C_EN | SW_SCL_OUT | SW_SDA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0x10 | SW_I2C_EN | SW_SCL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0x10 | SW_I2C_EN); /* start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mxl_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int mxl111sf_i2c_stop(struct mxl111sf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mxl_i2c("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 0x10 | SW_I2C_EN); /* stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0x10 | SW_I2C_EN | SW_SCL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 0x10 | SW_I2C_EN | SW_SCL_OUT | SW_SDA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 0x10 | SW_SCL_OUT | SW_SDA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mxl_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int mxl111sf_i2c_ack(struct mxl111sf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mxl_i2c("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = mxl111sf_read_reg(state, SW_I2C_BUSY_ADDR, &b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 0x10 | SW_I2C_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* pull SDA low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 0x10 | SW_I2C_EN | SW_SCL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0x10 | SW_I2C_EN | SW_SDA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mxl_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int mxl111sf_i2c_nack(struct mxl111sf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mxl_i2c("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* SDA high to signal last byte read from slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0x10 | SW_I2C_EN | SW_SCL_OUT | SW_SDA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = mxl111sf_write_reg(state, SW_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 0x10 | SW_I2C_EN | SW_SDA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mxl_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int mxl111sf_i2c_sw_xfer_msg(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mxl_i2c("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = mxl111sf_i2c_start(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = mxl111sf_i2c_bitbang_sendbyte(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) (msg->addr << 1) | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (mxl_fail(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mxl111sf_i2c_stop(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) for (i = 0; i < msg->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = mxl111sf_i2c_bitbang_recvbyte(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) &msg->buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (mxl_fail(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) mxl111sf_i2c_stop(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (i < msg->len - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mxl111sf_i2c_ack(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mxl111sf_i2c_nack(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = mxl111sf_i2c_stop(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = mxl111sf_i2c_start(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = mxl111sf_i2c_bitbang_sendbyte(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) (msg->addr << 1) & 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (mxl_fail(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mxl111sf_i2c_stop(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) for (i = 0; i < msg->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = mxl111sf_i2c_bitbang_sendbyte(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) msg->buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (mxl_fail(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mxl111sf_i2c_stop(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* FIXME: we only want to do this on the last transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mxl111sf_i2c_stop(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* HW-I2C ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define USB_WRITE_I2C_CMD 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define USB_READ_I2C_CMD 0xdd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define USB_END_I2C_CMD 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define USB_WRITE_I2C_CMD_LEN 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define USB_READ_I2C_CMD_LEN 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define I2C_MUX_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define I2C_CONTROL_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define I2C_SLAVE_ADDR_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define I2C_DATA_REG 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define I2C_INT_STATUS_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int mxl111sf_i2c_send_data(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u8 index, u8 *wdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int ret = mxl111sf_ctrl_msg(state, wdata[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) &wdata[1], 25, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mxl_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int mxl111sf_i2c_get_data(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u8 index, u8 *wdata, u8 *rdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int ret = mxl111sf_ctrl_msg(state, wdata[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) &wdata[1], 25, rdata, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mxl_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static u8 mxl111sf_i2c_check_status(struct mxl111sf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 buf[26];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mxl_i2c_adv("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) buf[0] = USB_READ_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) buf[2] = I2C_INT_STATUS_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) buf[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) buf[4] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) buf[5] = USB_END_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mxl111sf_i2c_get_data(state, 0, buf, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (buf[1] & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) status = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static u8 mxl111sf_i2c_check_fifo(struct mxl111sf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 buf[26];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) mxl_i2c("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) buf[0] = USB_READ_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) buf[2] = I2C_MUX_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) buf[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) buf[4] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) buf[5] = I2C_INT_STATUS_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) buf[6] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) buf[7] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) buf[8] = USB_END_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mxl111sf_i2c_get_data(state, 0, buf, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (0x08 == (buf[1] & 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) status = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if ((buf[5] & 0x02) == 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mxl_i2c("(buf[5] & 0x02) == 0x02"); /* FIXME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int mxl111sf_i2c_readagain(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u8 count, u8 *rbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 i2c_w_data[26];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u8 i2c_r_data[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u8 fifo_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mxl_i2c("read %d bytes", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) while ((fifo_status == 0) && (i++ < 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) fifo_status = mxl111sf_i2c_check_fifo(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) i2c_w_data[0] = 0xDD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) i2c_w_data[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) for (i = 2; i < 26; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) i2c_w_data[i] = 0xFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) i2c_w_data[2+(i*3)] = 0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) i2c_w_data[3+(i*3)] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) i2c_w_data[4+(i*3)] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mxl111sf_i2c_get_data(state, 0, i2c_w_data, i2c_r_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Check for I2C NACK status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (mxl111sf_i2c_check_status(state) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mxl_i2c("error!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) rbuf[i] = i2c_r_data[(i*3)+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mxl_i2c("%02x\t %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) i2c_r_data[(i*3)+1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) i2c_r_data[(i*3)+2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) status = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define HWI2C400 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int mxl111sf_i2c_hw_xfer_msg(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int i, k, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u16 index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u8 buf[26];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u8 i2c_r_data[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u16 block_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u16 left_over_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u8 rd_status[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u8 ret_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u8 readbuff[26];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mxl_i2c("addr: 0x%02x, read buff len: %d, write buff len: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) msg->addr, (msg->flags & I2C_M_RD) ? msg->len : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) (!(msg->flags & I2C_M_RD)) ? msg->len : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) for (index = 0; index < 26; index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) buf[index] = USB_END_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* command to indicate data payload is destined for I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) buf[0] = USB_WRITE_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* enable I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) buf[2] = I2C_MUX_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) buf[3] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) buf[4] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* enable I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) buf[5] = I2C_MUX_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) buf[6] = 0x81;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) buf[7] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* set Timeout register on I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) buf[8] = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) buf[9] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) buf[10] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* enable Interrupts on I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) buf[8] = 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) buf[9] = 0xF7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) buf[10] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) buf[11] = 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) buf[12] = 0xF7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) buf[13] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = mxl111sf_i2c_send_data(state, 0, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* write data on I2C bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (!(msg->flags & I2C_M_RD) && (msg->len > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) mxl_i2c("%d\t%02x", msg->len, msg->buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* control register on I2C interface to initialize I2C bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) buf[2] = I2C_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) buf[3] = 0x5E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) buf[4] = (HWI2C400) ? 0x03 : 0x0D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* I2C Slave device Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) buf[5] = I2C_SLAVE_ADDR_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) buf[6] = (msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) buf[7] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) buf[8] = USB_END_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = mxl111sf_i2c_send_data(state, 0, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* check for slave device status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (mxl111sf_i2c_check_status(state) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) mxl_i2c("NACK writing slave address %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* if NACK, stop I2C bus and exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) buf[2] = I2C_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) buf[3] = 0x4E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) buf[4] = (HWI2C400) ? 0x03 : 0x0D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* I2C interface can do I2C operations in block of 8 bytes of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) I2C data. calculation to figure out number of blocks of i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) data required to program */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) block_len = (msg->len / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) left_over_len = (msg->len % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) mxl_i2c("block_len %d, left_over_len %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) block_len, left_over_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) for (index = 0; index < block_len; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* write data on I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) buf[2+(i*3)] = I2C_DATA_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) buf[3+(i*3)] = msg->buf[(index*8)+i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) buf[4+(i*3)] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = mxl111sf_i2c_send_data(state, 0, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* check for I2C NACK status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (mxl111sf_i2c_check_status(state) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mxl_i2c("NACK writing slave address %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* if NACK, stop I2C bus and exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) buf[2] = I2C_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) buf[3] = 0x4E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) buf[4] = (HWI2C400) ? 0x03 : 0x0D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (left_over_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) for (k = 0; k < 26; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) buf[k] = USB_END_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) buf[0] = 0x99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) for (i = 0; i < left_over_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) buf[2+(i*3)] = I2C_DATA_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) buf[3+(i*3)] = msg->buf[(index*8)+i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mxl_i2c("index = %d %d data %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) index, i, msg->buf[(index*8)+i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) buf[4+(i*3)] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = mxl111sf_i2c_send_data(state, 0, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* check for I2C NACK status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (mxl111sf_i2c_check_status(state) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mxl_i2c("NACK writing slave address %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* if NACK, stop I2C bus and exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) buf[2] = I2C_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) buf[3] = 0x4E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) buf[4] = (HWI2C400) ? 0x03 : 0x0D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* issue I2C STOP after write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) buf[2] = I2C_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) buf[3] = 0x4E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) buf[4] = (HWI2C400) ? 0x03 : 0x0D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* read data from I2C bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if ((msg->flags & I2C_M_RD) && (msg->len > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mxl_i2c("read buf len %d", msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* command to indicate data payload is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) destined for I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) buf[2] = I2C_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) buf[3] = 0xDF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) buf[4] = (HWI2C400) ? 0x03 : 0x0D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* I2C xfer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) buf[5] = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) buf[6] = (msg->len & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) buf[7] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* I2C slave device Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) buf[8] = I2C_SLAVE_ADDR_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) buf[9] = msg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) buf[10] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) buf[11] = USB_END_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = mxl111sf_i2c_send_data(state, 0, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* check for I2C NACK status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (mxl111sf_i2c_check_status(state) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mxl_i2c("NACK reading slave address %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* if NACK, stop I2C bus and exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) buf[2] = I2C_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) buf[3] = 0xC7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) buf[4] = (HWI2C400) ? 0x03 : 0x0D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* I2C interface can do I2C operations in block of 8 bytes of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) I2C data. calculation to figure out number of blocks of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) i2c data required to program */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) block_len = ((msg->len) / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) left_over_len = ((msg->len) % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mxl_i2c("block_len %d, left_over_len %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) block_len, left_over_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* command to read data from I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) buf[0] = USB_READ_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) for (index = 0; index < block_len; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* setup I2C read request packet on I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) buf[2+(i*3)] = I2C_DATA_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) buf[3+(i*3)] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) buf[4+(i*3)] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = mxl111sf_i2c_get_data(state, 0, buf, i2c_r_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* check for I2C NACK status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (mxl111sf_i2c_check_status(state) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) mxl_i2c("NACK reading slave address %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* if NACK, stop I2C bus and exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) buf[2] = I2C_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) buf[3] = 0xC7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) buf[4] = (HWI2C400) ? 0x03 : 0x0D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* copy data from i2c data payload to read buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) rd_status[i] = i2c_r_data[(i*3)+2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (rd_status[i] == 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (i < 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) mxl_i2c("i2c fifo empty! @ %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) msg->buf[(index*8)+i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) i2c_r_data[(i*3)+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* read again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret_status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) mxl111sf_i2c_readagain(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) state, 8-(i+1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) readbuff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (ret_status == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) for (k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) k < 8-(i+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) msg->buf[(index*8)+(k+i+1)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) readbuff[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) mxl_i2c("read data: %02x\t %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) msg->buf[(index*8)+(k+i)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) (index*8)+(k+i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mxl_i2c("read data: %02x\t %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) msg->buf[(index*8)+(k+i+1)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) readbuff[k]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) goto stop_copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mxl_i2c("readagain ERROR!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) msg->buf[(index*8)+i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) i2c_r_data[(i*3)+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) msg->buf[(index*8)+i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) i2c_r_data[(i*3)+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) stop_copy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (left_over_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) for (k = 0; k < 26; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) buf[k] = USB_END_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) buf[0] = 0xDD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) for (i = 0; i < left_over_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) buf[2+(i*3)] = I2C_DATA_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) buf[3+(i*3)] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) buf[4+(i*3)] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = mxl111sf_i2c_get_data(state, 0, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) i2c_r_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* check for I2C NACK status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (mxl111sf_i2c_check_status(state) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) mxl_i2c("NACK reading slave address %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* if NACK, stop I2C bus and exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) buf[2] = I2C_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) buf[3] = 0xC7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) buf[4] = (HWI2C400) ? 0x03 : 0x0D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) for (i = 0; i < left_over_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) msg->buf[(block_len*8)+i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) i2c_r_data[(i*3)+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) mxl_i2c("read data: %02x\t %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) i2c_r_data[(i*3)+1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) i2c_r_data[(i*3)+2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* indicate I2C interface to issue NACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) after next I2C read op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) buf[0] = USB_WRITE_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) buf[2] = I2C_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) buf[3] = 0x17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) buf[4] = (HWI2C400) ? 0x03 : 0x0D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) buf[5] = USB_END_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ret = mxl111sf_i2c_send_data(state, 0, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) buf[2] = I2C_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) buf[3] = 0xC7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) buf[4] = (HWI2C400) ? 0x03 : 0x0D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* STOP and disable I2C MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) buf[0] = USB_WRITE_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) buf[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* de-initilize I2C BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) buf[5] = USB_END_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mxl111sf_i2c_send_data(state, 0, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) buf[2] = I2C_CONTROL_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) buf[3] = 0xDF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) buf[4] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* disable I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) buf[5] = I2C_MUX_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) buf[6] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) buf[7] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* de-initilize I2C BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) buf[8] = USB_END_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mxl111sf_i2c_send_data(state, 0, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* disable I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) buf[2] = I2C_MUX_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) buf[3] = 0x81;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) buf[4] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* disable I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) buf[5] = I2C_MUX_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) buf[6] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) buf[7] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* disable I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) buf[8] = I2C_MUX_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) buf[9] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) buf[10] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) buf[11] = USB_END_I2C_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mxl111sf_i2c_send_data(state, 0, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int mxl111sf_i2c_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct i2c_msg msg[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct dvb_usb_device *d = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct mxl111sf_state *state = d->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int hwi2c = (state->chip_rev > MXL111SF_V6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = (hwi2c) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) mxl111sf_i2c_hw_xfer_msg(state, &msg[i]) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mxl111sf_i2c_sw_xfer_msg(state, &msg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (mxl_fail(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) mxl_debug_adv("failed with error %d on i2c transaction %d of %d, %sing %d bytes to/from 0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ret, i+1, num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) (msg[i].flags & I2C_M_RD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) "read" : "writ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) msg[i].len, msg[i].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) mutex_unlock(&d->i2c_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return i == num ? num : -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags