^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mxl111sf-gpio.c - driver for the MaxLinear MXL111SF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2014 Michael Krufky <mkrufky@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "mxl111sf-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "mxl111sf-i2c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "mxl111sf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MXL_GPIO_MUX_REG_0 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MXL_GPIO_MUX_REG_1 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MXL_GPIO_MUX_REG_2 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MXL_GPIO_DIR_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MXL_GPIO_DIR_OUTPUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static int mxl111sf_set_gpo_state(struct mxl111sf_state *state, u8 pin, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) mxl_debug_adv("(%d, %d)", pin, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if ((pin > 0) && (pin < 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ret = mxl111sf_read_reg(state, 0x19, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) tmp &= ~(1 << (pin - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) tmp |= (val << (pin - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ret = mxl111sf_write_reg(state, 0x19, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) } else if (pin <= 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (pin == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) pin += 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ret = mxl111sf_read_reg(state, 0x30, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) tmp &= ~(1 << (pin - 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) tmp |= (val << (pin - 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ret = mxl111sf_write_reg(state, 0x30, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int mxl111sf_get_gpi_state(struct mxl111sf_state *state, u8 pin, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mxl_debug("(0x%02x)", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) switch (pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ret = mxl111sf_read_reg(state, 0x23, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *val = (tmp >> (pin + 4)) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret = mxl111sf_read_reg(state, 0x2f, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *val = (tmp >> pin) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ret = mxl111sf_read_reg(state, 0x22, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *val = (tmp >> (pin - 3)) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -EINVAL; /* invalid pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct mxl_gpio_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int mxl111sf_config_gpio_pins(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct mxl_gpio_cfg *gpio_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mxl_debug_adv("(%d, %d)", gpio_cfg->pin, gpio_cfg->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) switch (gpio_cfg->pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ret = mxl111sf_read_reg(state, MXL_GPIO_MUX_REG_0, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tmp &= ~(1 << (gpio_cfg->pin + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tmp |= (gpio_cfg->dir << (gpio_cfg->pin + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = mxl111sf_write_reg(state, MXL_GPIO_MUX_REG_0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = mxl111sf_read_reg(state, MXL_GPIO_MUX_REG_1, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tmp &= ~(1 << gpio_cfg->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) tmp |= (gpio_cfg->dir << gpio_cfg->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = mxl111sf_write_reg(state, MXL_GPIO_MUX_REG_1, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = mxl111sf_read_reg(state, MXL_GPIO_MUX_REG_2, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) tmp &= ~(1 << (gpio_cfg->pin - 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) tmp |= (gpio_cfg->dir << (gpio_cfg->pin - 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = mxl111sf_write_reg(state, MXL_GPIO_MUX_REG_2, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -EINVAL; /* invalid pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = (MXL_GPIO_DIR_OUTPUT == gpio_cfg->dir) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mxl111sf_set_gpo_state(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) gpio_cfg->pin, gpio_cfg->val) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mxl111sf_get_gpi_state(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) gpio_cfg->pin, &gpio_cfg->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mxl_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int mxl111sf_hw_do_set_gpio(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int gpio, int direction, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct mxl_gpio_cfg gpio_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .pin = gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .dir = direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .val = val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mxl_debug("(%d, %d, %d)", gpio, direction, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return mxl111sf_config_gpio_pins(state, &gpio_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PIN_MUX_MPEG_MODE_MASK 0x40 /* 0x17 <6> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PIN_MUX_MPEG_PAR_EN_MASK 0x01 /* 0x18 <0> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PIN_MUX_MPEG_SER_EN_MASK 0x02 /* 0x18 <1> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PIN_MUX_MPG_IN_MUX_MASK 0x80 /* 0x3D <7> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PIN_MUX_BT656_ENABLE_MASK 0x04 /* 0x12 <2> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PIN_MUX_I2S_ENABLE_MASK 0x40 /* 0x15 <6> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PIN_MUX_SPI_MODE_MASK 0x10 /* 0x3D <4> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PIN_MUX_MCLK_EN_CTRL_MASK 0x10 /* 0x82 <4> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PIN_MUX_MPSYN_EN_CTRL_MASK 0x20 /* 0x82 <5> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PIN_MUX_MDVAL_EN_CTRL_MASK 0x40 /* 0x82 <6> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PIN_MUX_MPERR_EN_CTRL_MASK 0x80 /* 0x82 <7> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PIN_MUX_MDAT_EN_0_MASK 0x10 /* 0x84 <4> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PIN_MUX_MDAT_EN_1_MASK 0x20 /* 0x84 <5> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PIN_MUX_MDAT_EN_2_MASK 0x40 /* 0x84 <6> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PIN_MUX_MDAT_EN_3_MASK 0x80 /* 0x84 <7> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PIN_MUX_MDAT_EN_4_MASK 0x10 /* 0x89 <4> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PIN_MUX_MDAT_EN_5_MASK 0x20 /* 0x89 <5> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PIN_MUX_MDAT_EN_6_MASK 0x40 /* 0x89 <6> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PIN_MUX_MDAT_EN_7_MASK 0x80 /* 0x89 <7> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int mxl111sf_config_pin_mux_modes(struct mxl111sf_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) enum mxl111sf_mux_config pin_mux_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 r12, r15, r17, r18, r3D, r82, r84, r89;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mxl_debug("(%d)", pin_mux_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret = mxl111sf_read_reg(state, 0x17, &r17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = mxl111sf_read_reg(state, 0x18, &r18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = mxl111sf_read_reg(state, 0x12, &r12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = mxl111sf_read_reg(state, 0x15, &r15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = mxl111sf_read_reg(state, 0x82, &r82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = mxl111sf_read_reg(state, 0x84, &r84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = mxl111sf_read_reg(state, 0x89, &r89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = mxl111sf_read_reg(state, 0x3D, &r3D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) switch (pin_mux_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case PIN_MUX_TS_OUT_PARALLEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* mpeg_mode = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) r17 |= PIN_MUX_MPEG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* mpeg_par_en = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) r18 |= PIN_MUX_MPEG_PAR_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* mpeg_ser_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) r18 &= ~PIN_MUX_MPEG_SER_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* mpg_in_mux = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* bt656_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) r12 &= ~PIN_MUX_BT656_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* i2s_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) r15 &= ~PIN_MUX_I2S_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* spi_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) r3D &= ~PIN_MUX_SPI_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* mclk_en_ctrl = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) r82 |= PIN_MUX_MCLK_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* mperr_en_ctrl = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) r82 |= PIN_MUX_MPERR_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* mdval_en_ctrl = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) r82 |= PIN_MUX_MDVAL_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* mpsyn_en_ctrl = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) r82 |= PIN_MUX_MPSYN_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* mdat_en_ctrl[3:0] = 0xF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) r84 |= 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* mdat_en_ctrl[7:4] = 0xF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) r89 |= 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case PIN_MUX_TS_OUT_SERIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* mpeg_mode = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) r17 |= PIN_MUX_MPEG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* mpeg_par_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) r18 &= ~PIN_MUX_MPEG_PAR_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* mpeg_ser_en = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) r18 |= PIN_MUX_MPEG_SER_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* mpg_in_mux = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* bt656_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) r12 &= ~PIN_MUX_BT656_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* i2s_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) r15 &= ~PIN_MUX_I2S_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* spi_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) r3D &= ~PIN_MUX_SPI_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* mclk_en_ctrl = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) r82 |= PIN_MUX_MCLK_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* mperr_en_ctrl = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) r82 |= PIN_MUX_MPERR_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* mdval_en_ctrl = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) r82 |= PIN_MUX_MDVAL_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* mpsyn_en_ctrl = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) r82 |= PIN_MUX_MPSYN_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* mdat_en_ctrl[3:0] = 0xF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) r84 |= 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* mdat_en_ctrl[7:4] = 0xF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) r89 |= 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case PIN_MUX_GPIO_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* mpeg_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) r17 &= ~PIN_MUX_MPEG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* mpeg_par_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) r18 &= ~PIN_MUX_MPEG_PAR_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* mpeg_ser_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) r18 &= ~PIN_MUX_MPEG_SER_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* mpg_in_mux = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* bt656_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) r12 &= ~PIN_MUX_BT656_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* i2s_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) r15 &= ~PIN_MUX_I2S_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* spi_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) r3D &= ~PIN_MUX_SPI_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* mclk_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* mperr_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* mdval_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* mpsyn_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* mdat_en_ctrl[3:0] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) r84 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* mdat_en_ctrl[7:4] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) r89 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case PIN_MUX_TS_SERIAL_IN_MODE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* mpeg_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) r17 &= ~PIN_MUX_MPEG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* mpeg_par_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) r18 &= ~PIN_MUX_MPEG_PAR_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* mpeg_ser_en = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) r18 |= PIN_MUX_MPEG_SER_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* mpg_in_mux = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* bt656_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) r12 &= ~PIN_MUX_BT656_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* i2s_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) r15 &= ~PIN_MUX_I2S_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* spi_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) r3D &= ~PIN_MUX_SPI_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* mclk_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* mperr_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* mdval_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* mpsyn_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* mdat_en_ctrl[3:0] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) r84 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* mdat_en_ctrl[7:4] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) r89 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case PIN_MUX_TS_SERIAL_IN_MODE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* mpeg_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) r17 &= ~PIN_MUX_MPEG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* mpeg_par_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) r18 &= ~PIN_MUX_MPEG_PAR_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* mpeg_ser_en = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) r18 |= PIN_MUX_MPEG_SER_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* mpg_in_mux = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) r3D |= PIN_MUX_MPG_IN_MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* bt656_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) r12 &= ~PIN_MUX_BT656_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* i2s_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) r15 &= ~PIN_MUX_I2S_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* spi_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) r3D &= ~PIN_MUX_SPI_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* mclk_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* mperr_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* mdval_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* mpsyn_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* mdat_en_ctrl[3:0] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) r84 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* mdat_en_ctrl[7:4] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) r89 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case PIN_MUX_TS_SPI_IN_MODE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* mpeg_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) r17 &= ~PIN_MUX_MPEG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* mpeg_par_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) r18 &= ~PIN_MUX_MPEG_PAR_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* mpeg_ser_en = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) r18 |= PIN_MUX_MPEG_SER_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* mpg_in_mux = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) r3D |= PIN_MUX_MPG_IN_MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* bt656_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) r12 &= ~PIN_MUX_BT656_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* i2s_enable = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) r15 |= PIN_MUX_I2S_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* spi_mode = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) r3D |= PIN_MUX_SPI_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* mclk_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* mperr_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* mdval_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* mpsyn_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* mdat_en_ctrl[3:0] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) r84 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* mdat_en_ctrl[7:4] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) r89 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case PIN_MUX_TS_SPI_IN_MODE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* mpeg_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) r17 &= ~PIN_MUX_MPEG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* mpeg_par_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) r18 &= ~PIN_MUX_MPEG_PAR_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* mpeg_ser_en = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) r18 |= PIN_MUX_MPEG_SER_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* mpg_in_mux = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* bt656_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) r12 &= ~PIN_MUX_BT656_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* i2s_enable = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) r15 |= PIN_MUX_I2S_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* spi_mode = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) r3D |= PIN_MUX_SPI_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* mclk_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* mperr_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* mdval_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* mpsyn_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* mdat_en_ctrl[3:0] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) r84 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* mdat_en_ctrl[7:4] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) r89 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case PIN_MUX_TS_PARALLEL_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* mpeg_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) r17 &= ~PIN_MUX_MPEG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* mpeg_par_en = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) r18 |= PIN_MUX_MPEG_PAR_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* mpeg_ser_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) r18 &= ~PIN_MUX_MPEG_SER_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* mpg_in_mux = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* bt656_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) r12 &= ~PIN_MUX_BT656_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* i2s_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) r15 &= ~PIN_MUX_I2S_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* spi_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) r3D &= ~PIN_MUX_SPI_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* mclk_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* mperr_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* mdval_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* mpsyn_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* mdat_en_ctrl[3:0] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) r84 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* mdat_en_ctrl[7:4] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) r89 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case PIN_MUX_BT656_I2S_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* mpeg_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) r17 &= ~PIN_MUX_MPEG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* mpeg_par_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) r18 &= ~PIN_MUX_MPEG_PAR_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* mpeg_ser_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) r18 &= ~PIN_MUX_MPEG_SER_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* mpg_in_mux = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* bt656_enable = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) r12 |= PIN_MUX_BT656_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* i2s_enable = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) r15 |= PIN_MUX_I2S_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* spi_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) r3D &= ~PIN_MUX_SPI_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* mclk_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* mperr_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* mdval_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* mpsyn_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* mdat_en_ctrl[3:0] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) r84 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* mdat_en_ctrl[7:4] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) r89 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case PIN_MUX_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* mpeg_mode = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) r17 |= PIN_MUX_MPEG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* mpeg_par_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) r18 &= ~PIN_MUX_MPEG_PAR_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* mpeg_ser_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) r18 &= ~PIN_MUX_MPEG_SER_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* mpg_in_mux = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* bt656_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) r12 &= ~PIN_MUX_BT656_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* i2s_enable = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) r15 &= ~PIN_MUX_I2S_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* spi_mode = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) r3D &= ~PIN_MUX_SPI_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* mclk_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) r82 &= ~PIN_MUX_MCLK_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* mperr_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) r82 &= ~PIN_MUX_MPERR_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* mdval_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) r82 &= ~PIN_MUX_MDVAL_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* mpsyn_en_ctrl = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) r82 &= ~PIN_MUX_MPSYN_EN_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* mdat_en_ctrl[3:0] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) r84 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* mdat_en_ctrl[7:4] = 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) r89 &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = mxl111sf_write_reg(state, 0x17, r17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = mxl111sf_write_reg(state, 0x18, r18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = mxl111sf_write_reg(state, 0x12, r12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = mxl111sf_write_reg(state, 0x15, r15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = mxl111sf_write_reg(state, 0x82, r82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = mxl111sf_write_reg(state, 0x84, r84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = mxl111sf_write_reg(state, 0x89, r89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = mxl111sf_write_reg(state, 0x3D, r3D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int mxl111sf_hw_set_gpio(struct mxl111sf_state *state, int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return mxl111sf_hw_do_set_gpio(state, gpio, MXL_GPIO_DIR_OUTPUT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int mxl111sf_hw_gpio_initialize(struct mxl111sf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u8 gpioval = 0x07; /* write protect enabled, signal LEDs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mxl_debug("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) for (i = 3; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ret = mxl111sf_hw_set_gpio(state, i, (gpioval >> i) & 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define PCA9534_I2C_ADDR (0x40 >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int pca9534_set_gpio(struct mxl111sf_state *state, int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u8 w[2] = { 1, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u8 r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { .addr = PCA9534_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .flags = 0, .buf = w, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { .addr = PCA9534_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .flags = I2C_M_RD, .buf = &r, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mxl_debug("(%d, %d)", gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* read current GPIO levels from flip-flop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) i2c_transfer(&state->d->i2c_adap, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* prepare write buffer with current GPIO levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) msg[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) w[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) w[1] = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* clear the desired GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) w[1] &= ~(1 << gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* set the desired GPIO value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) w[1] |= ((val ? 1 : 0) << gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* write new GPIO levels to flip-flop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) i2c_transfer(&state->d->i2c_adap, &msg[0], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int pca9534_init_port_expander(struct mxl111sf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u8 w[2] = { 1, 0x07 }; /* write protect enabled, signal LEDs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .addr = PCA9534_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .flags = 0, .buf = w, .len = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mxl_debug("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) i2c_transfer(&state->d->i2c_adap, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* configure all pins as outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) w[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) w[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) i2c_transfer(&state->d->i2c_adap, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int mxl111sf_set_gpio(struct mxl111sf_state *state, int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mxl_debug("(%d, %d)", gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) switch (state->gpio_port_expander) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) mxl_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) "gpio_port_expander undefined, assuming PCA9534");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) case mxl111sf_PCA9534:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return pca9534_set_gpio(state, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) case mxl111sf_gpio_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return mxl111sf_hw_set_gpio(state, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static int mxl111sf_probe_port_expander(struct mxl111sf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u8 w = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u8 r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { .flags = 0, .buf = &w, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { .flags = I2C_M_RD, .buf = &r, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) mxl_debug("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) msg[0].addr = 0x70 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) msg[1].addr = 0x70 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* read current GPIO levels from flip-flop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = i2c_transfer(&state->d->i2c_adap, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (ret == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) state->port_expander_addr = msg[0].addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) state->gpio_port_expander = mxl111sf_PCA9534;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) mxl_debug("found port expander at 0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) state->port_expander_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) msg[0].addr = 0x40 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) msg[1].addr = 0x40 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = i2c_transfer(&state->d->i2c_adap, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ret == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) state->port_expander_addr = msg[0].addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) state->gpio_port_expander = mxl111sf_PCA9534;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mxl_debug("found port expander at 0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) state->port_expander_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) state->port_expander_addr = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) state->gpio_port_expander = mxl111sf_gpio_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mxl_debug("using hardware gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int mxl111sf_init_port_expander(struct mxl111sf_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mxl_debug("()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (0x00 == state->port_expander_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) mxl111sf_probe_port_expander(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) switch (state->gpio_port_expander) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) mxl_printk(KERN_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "gpio_port_expander undefined, assuming PCA9534");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case mxl111sf_PCA9534:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return pca9534_init_port_expander(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) case mxl111sf_gpio_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return mxl111sf_hw_gpio_initialize(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) int mxl111sf_gpio_mode_switch(struct mxl111sf_state *state, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* GPO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * 3 - ATSC/MH# | 1 = ATSC transport, 0 = MH transport | default 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * 4 - ATSC_RST## | 1 = ATSC enable, 0 = ATSC Reset | default 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * 5 - ATSC_EN | 1 = ATSC power enable, 0 = ATSC power off | default 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * 6 - MH_RESET# | 1 = MH enable, 0 = MH Reset | default 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * 7 - MH_EN | 1 = MH power enable, 0 = MH power off | default 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) mxl_debug("(%d)", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) case MXL111SF_GPIO_MOD_MH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) mxl111sf_set_gpio(state, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) mxl111sf_set_gpio(state, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) mxl111sf_set_gpio(state, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mxl111sf_set_gpio(state, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) mxl111sf_set_gpio(state, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) case MXL111SF_GPIO_MOD_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mxl111sf_set_gpio(state, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) mxl111sf_set_gpio(state, 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) mxl111sf_set_gpio(state, 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) mxl111sf_set_gpio(state, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) mxl111sf_set_gpio(state, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) default: /* DVBT / STANDBY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mxl111sf_init_port_expander(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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