^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) cx231xx.h - driver for Conexant Cx23100/101/102 USB video capture devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Based on em28xx driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _CX231XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _CX231XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/drv-intf/cx2341x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/videobuf2-vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-fh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/rc-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/i2c/ir-kbd-i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "cx231xx-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "cx231xx-pcb-cfg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "cx231xx-conf-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRIVER_NAME "cx231xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PWR_SLEEP_INTERVAL 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* I2C addresses for control block in Cx231xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AFE_DEVICE_ADDRESS 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2S_BLK_DEVICE_ADDRESS 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VID_BLK_I2C_ADDRESS 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VERVE_I2C_ADDRESS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DIF_USE_BASEBAND 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Boards supported by driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CX231XX_BOARD_UNKNOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CX231XX_BOARD_CNXT_CARRAERA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CX231XX_BOARD_CNXT_SHELBY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CX231XX_BOARD_CNXT_RDE_253S 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CX231XX_BOARD_CNXT_RDU_253S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CX231XX_BOARD_CNXT_VIDEO_GRABBER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CX231XX_BOARD_CNXT_RDE_250 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CX231XX_BOARD_CNXT_RDU_250 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CX231XX_BOARD_HAUPPAUGE_EXETER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CX231XX_BOARD_HAUPPAUGE_USBLIVE2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CX231XX_BOARD_PV_PLAYTV_USB_HYBRID 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CX231XX_BOARD_PV_XCAPTURE_USB 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CX231XX_BOARD_KWORLD_UB430_USB_HYBRID 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CX231XX_BOARD_ICONBIT_U100 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CX231XX_BOARD_ELGATO_VIDEO_CAPTURE_V2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CX231XX_BOARD_OTG102 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CX231XX_BOARD_KWORLD_UB445_USB_HYBRID 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CX231XX_BOARD_HAUPPAUGE_930C_HD_1114xx 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CX231XX_BOARD_HAUPPAUGE_955Q 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CX231XX_BOARD_TERRATEC_GRABBY 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CX231XX_BOARD_EVROMEDIA_FULL_HYBRID_FULLHD 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CX231XX_BOARD_ASTROMETA_T2HYBRID 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CX231XX_BOARD_THE_IMAGING_SOURCE_DFG_USB2_PRO 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CX231XX_BOARD_HAUPPAUGE_935C 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CX231XX_BOARD_HAUPPAUGE_975 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Limits minimum and default number of buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CX231XX_MIN_BUF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CX231XX_DEF_BUF 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CX231XX_DEF_VBI_BUF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VBI_LINE_COUNT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VBI_LINE_LENGTH 1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*Limits the max URB message size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define URB_MAX_CTRL_SIZE 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Params for validated field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CX231XX_BOARD_NOT_VALIDATED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CX231XX_BOARD_VALIDATED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* maximum number of cx231xx boards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CX231XX_MAXBOARDS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* maximum number of frames that can be queued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CX231XX_NUM_FRAMES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* number of buffers for isoc transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CX231XX_NUM_BUFS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* number of packets for each buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) windows requests only 40 packets .. so we better do the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) this is what I found out for all alternate numbers there!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CX231XX_NUM_PACKETS 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* default alternate; 0 means choose the best */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CX231XX_PINOUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CX231XX_INTERLACED_DEFAULT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* time to wait when stopping the isoc transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CX231XX_URB_TIMEOUT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) msecs_to_jiffies(CX231XX_NUM_BUFS * CX231XX_NUM_PACKETS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CX231xx_NORMS (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SLEEP_S5H1432 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CX23417_OSC_EN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CX23417_RESET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct cx23417_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 fourcc; /* v4l2 format id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 cxformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum cx231xx_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CX231XX_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CX231XX_ANALOG_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) CX231XX_DIGITAL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) enum cx231xx_std_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CX231XX_TV_AIR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CX231XX_TV_CABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enum cx231xx_stream_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) STREAM_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) STREAM_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) STREAM_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct cx231xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct cx231xx_isoc_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* max packet size of isoc transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int max_pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* number of allocated urbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int num_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* urb for isoc transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct urb **urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* transfer buffers for isoc transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) char **transfer_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Last buffer command and region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int pos, size, pktsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Last field: ODD or EVEN? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Stores incomplete commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 tmp_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int tmp_buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Stores already requested buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct cx231xx_buffer *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Stores the number of received fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int nfields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* isoc urb callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int (*isoc_copy) (struct cx231xx *dev, struct urb *urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct cx231xx_bulk_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* max packet size of bulk transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int max_pkt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* number of allocated urbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int num_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* urb for bulk transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct urb **urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* transfer buffers for bulk transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) char **transfer_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Last buffer command and region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int pos, size, pktsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Last field: ODD or EVEN? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Stores incomplete commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 tmp_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int tmp_buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Stores already requested buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct cx231xx_buffer *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Stores the number of received fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int nfields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* bulk urb callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int (*bulk_copy) (struct cx231xx *dev, struct urb *urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct cx231xx_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 fourcc; /* v4l2 format id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* buffer for one video frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct cx231xx_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* common v4l buffer stuff -- must be first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct vb2_v4l2_buffer vb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct list_head frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int top_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int receiving;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) enum ps_package_head {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CX231XX_NEED_ADD_PS_PACKAGE_HEAD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CX231XX_NONEED_PS_PACKAGE_HEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct cx231xx_dmaqueue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct list_head active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) wait_queue_head_t wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Counters to control buffer fill */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 is_partial_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 partial_buf[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 last_sav;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int current_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 bytes_left_in_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 lines_completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 field1_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 lines_per_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*Mpeg2 control buffer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 *p_left_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 left_data_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u8 mpeg_buffer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 mpeg_buffer_completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) enum ps_package_head add_ps_package_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) char ps_head[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MAX_CX231XX_INPUT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) enum cx231xx_itype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) CX231XX_VMUX_COMPOSITE1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) CX231XX_VMUX_SVIDEO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) CX231XX_VMUX_TELEVISION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) CX231XX_VMUX_CABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) CX231XX_RADIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) CX231XX_VMUX_DVB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) enum cx231xx_v_input {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) CX231XX_VIN_1_1 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) CX231XX_VIN_2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) CX231XX_VIN_3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) CX231XX_VIN_4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) CX231XX_VIN_1_2 = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) CX231XX_VIN_2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) CX231XX_VIN_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) CX231XX_VIN_1_3 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) CX231XX_VIN_2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) CX231XX_VIN_3_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* cx231xx has two audio inputs: tuner and line in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) enum cx231xx_amux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* This is the only entry for cx231xx tuner input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) CX231XX_AMUX_VIDEO, /* cx231xx tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) CX231XX_AMUX_LINE_IN, /* Line In */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct cx231xx_reg_seq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned char bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct cx231xx_input {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) enum cx231xx_itype type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int vmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) enum cx231xx_amux amux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct cx231xx_reg_seq *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define INPUT(nr) (&cx231xx_boards[dev->model].input[nr])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) enum cx231xx_decoder {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) CX231XX_NODECODER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) CX231XX_AVDECODER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) enum CX231XX_I2C_MASTER_PORT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) I2C_0 = 0, /* master 0 - internal connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) I2C_1 = 1, /* master 1 - used with mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) I2C_2 = 2, /* master 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) I2C_1_MUX_1 = 3, /* master 1 - port 1 (I2C_DEMOD_EN = 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) I2C_1_MUX_3 = 4 /* master 1 - port 3 (I2C_DEMOD_EN = 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct cx231xx_board {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int vchannels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int tuner_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int tuner_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) v4l2_std_id norm; /* tv norm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* demod related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int demod_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int demod_addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 demod_xfer_mode; /* 0 - Serial; 1 - parallel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* GPIO Pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct cx231xx_reg_seq *dvb_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct cx231xx_reg_seq *suspend_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct cx231xx_reg_seq *tuner_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Negative means don't use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) s8 tuner_sif_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) s8 tuner_scl_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) s8 tuner_sda_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* PIN ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 ctl_pin_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u8 agc_analog_digital_select_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 gpio_pin_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* i2c masters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 tuner_i2c_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 demod_i2c_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 ir_i2c_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* for devices with I2C chips for IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) char *rc_map_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned int max_range_640_480:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int has_dvb:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned int has_417:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned int valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int no_alt_vanc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned int external_av:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned char xclk, i2c_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) enum cx231xx_decoder decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int output_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct cx231xx_input input[MAX_CX231XX_INPUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct cx231xx_input radio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct rc_map *ir_codes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* device states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) enum cx231xx_dev_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DEV_INITIALIZED = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) DEV_DISCONNECTED = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) enum AFE_MODE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) AFE_MODE_LOW_IF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) AFE_MODE_BASEBAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) AFE_MODE_EU_HI_IF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) AFE_MODE_US_HI_IF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) AFE_MODE_JAPAN_HI_IF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) enum AUDIO_INPUT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) AUDIO_INPUT_MUTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) AUDIO_INPUT_LINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) AUDIO_INPUT_TUNER_TV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) AUDIO_INPUT_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) AUDIO_INPUT_TUNER_FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CX231XX_AUDIO_BUFS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define CX231XX_NUM_AUDIO_PACKETS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define CX231XX_ISO_NUM_AUDIO_PACKETS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* cx231xx extensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CX231XX_AUDIO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define CX231XX_DVB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct cx231xx_audio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) char name[50];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) char *transfer_buffer[CX231XX_AUDIO_BUFS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct urb *urb[CX231XX_AUDIO_BUFS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int capture_transfer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct snd_pcm_substream *capture_pcm_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int hwptr_done_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct snd_card *sndcard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int users, shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* locks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int alt; /* alternate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int max_pkt_size; /* max packet size of isoc transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int num_alt; /* Number of alternative settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u16 end_point_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct cx231xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* set/get i2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* 00--1Mb/s, 01-400kb/s, 10--100kb/s, 11--5Mb/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define I2C_SPEED_1M 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define I2C_SPEED_400K 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define I2C_SPEED_100K 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define I2C_SPEED_5M 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* 0-- STOP transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define I2C_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* 1-- do not transmit STOP at end of transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define I2C_NOSTOP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* 1--allow slave to insert clock wait states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define I2C_SYNC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct cx231xx_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct cx231xx *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* i2c i/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct i2c_adapter i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int i2c_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* different settings for each bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u8 i2c_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u8 i2c_nostop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 i2c_reserve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct cx231xx_i2c_xfer_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u8 dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 direction; /* 1 - IN, 0 - OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 saddr_len; /* sub address len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u16 saddr_dat; /* sub addr data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u8 buf_size; /* buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u8 *p_buffer; /* pointer to the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct VENDOR_REQUEST_IN {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u8 bRequest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u16 wValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u16 wIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u16 wLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u8 direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u8 bData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u8 *pBuff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct cx231xx_tvnorm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) v4l2_std_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 cxiformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 cxoformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) enum TRANSFER_TYPE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) Raw_Video = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) Audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) Vbi, /* VANC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) Sliced_cc, /* HANC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) TS1_serial_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) TS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) TS1_parallel_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct cx231xx_video_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Isoc control struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct cx231xx_dmaqueue vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct cx231xx_isoc_ctl isoc_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct cx231xx_bulk_ctl bulk_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* locks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* usb transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int alt; /* alternate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) int max_pkt_size; /* max packet size of isoc transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int num_alt; /* Number of alternative settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u16 end_point_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct cx231xx_tsport {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct cx231xx *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int sram_chno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* dma queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 ts_packet_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 ts_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* locks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 reg_gpcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 reg_gpcnt_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 reg_dma_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 reg_lngth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 reg_hw_sop_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 reg_gen_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 reg_bd_pkt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 reg_sop_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 reg_fifo_ovfl_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 reg_vld_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 reg_ts_clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 reg_ts_int_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u32 reg_ts_int_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 reg_src_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Default register vals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int pci_irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 dma_ctl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 ts_int_msk_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 gen_ctrl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 ts_clk_en_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 src_sel_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 vld_misc_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 hw_sop_ctrl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* Allow a single tsport to have multiple frontends */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 num_frontends;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) void *port_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* main device struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct cx231xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* generic device properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) char name[30]; /* name (including minor) of the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int model; /* index in the device_data struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int devno; /* marks the number of this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct device *dev; /* pointer to USB interface's dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct cx231xx_board board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* For I2C IR support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct IR_i2c_init_data init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct i2c_client *ir_i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned int stream_on:1; /* Locks streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned int vbi_stream_on:1; /* Locks streams for VBI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned int has_audio_class:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned int has_alsa_audio:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned int i2c_scan_running:1; /* true only during i2c_scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct cx231xx_fmt *format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct v4l2_device v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct v4l2_subdev *sd_cx25840;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct v4l2_subdev *sd_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct v4l2_ctrl_handler radio_ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct cx2341x_handler mpeg_ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct work_struct wq_trigger; /* Trigger to start/stop audio for alsa module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) atomic_t stream_started; /* stream should be running if true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct list_head devlist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int tuner_type; /* type of the tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int tuner_addr; /* tuner address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct cx231xx_i2c i2c_bus[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct i2c_mux_core *muxc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct i2c_adapter *i2c_mux_adap[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned int xc_fw_load_done:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int port_3_switch_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* locks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct mutex gpio_i2c_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct mutex i2c_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* video for linux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int users; /* user count for exclusive use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct video_device vdev; /* video for linux device struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) v4l2_std_id norm; /* selected tv norm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int ctl_freq; /* selected frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) unsigned int ctl_ainput; /* selected audio input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* frame properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int width; /* current frame width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int height; /* current frame height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int interlaced; /* 1=interlace fields, 0=just top fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct cx231xx_audio adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) enum cx231xx_dev_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct work_struct request_module_wk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* locks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct mutex ctrl_urb_lock; /* protects urb_buf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct list_head inqueue, outqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) wait_queue_head_t open, wait_frame, wait_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct video_device vbi_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct video_device radio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct media_device *media_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct media_pad video_pad, vbi_pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct media_entity input_ent[MAX_CX231XX_INPUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct media_pad input_pad[MAX_CX231XX_INPUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct vb2_queue vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct vb2_queue vbiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned char eedata[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct cx231xx_video_mode video_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct cx231xx_video_mode vbi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct cx231xx_video_mode sliced_cc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct cx231xx_video_mode ts1_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) atomic_t devlist_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct usb_device *udev; /* the usb device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) char urb_buf[URB_MAX_CTRL_SIZE]; /* urb control msg buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* helper funcs that call usb_control_msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int (*cx231xx_read_ctrl_reg) (struct cx231xx *dev, u8 req, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) char *buf, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int (*cx231xx_write_ctrl_reg) (struct cx231xx *dev, u8 req, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) char *buf, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int (*cx231xx_send_usb_command) (struct cx231xx_i2c *i2c_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct cx231xx_i2c_xfer_data *req_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int (*cx231xx_gpio_i2c_read) (struct cx231xx *dev, u8 dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u8 *buf, u8 len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int (*cx231xx_gpio_i2c_write) (struct cx231xx *dev, u8 dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u8 *buf, u8 len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) int (*cx231xx_set_analog_freq) (struct cx231xx *dev, u32 freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int (*cx231xx_reset_analog_tuner) (struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) enum cx231xx_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct cx231xx_dvb *dvb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Cx231xx supported PCB config's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct pcb_config current_pcb_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u8 current_scenario_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u8 interface_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u8 max_iad_interface_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* GPIO related register direction and values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u32 gpio_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 gpio_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Power Modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* afe parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) enum AFE_MODE afe_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 afe_ref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* video related parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u32 video_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u32 active_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u8 vbi_or_sliced_cc_mode; /* 0 - vbi ; 1 - sliced cc mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) enum cx231xx_std_mode std_mode; /* 0 - Air; 1 - cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /*mode: digital=1 or analog=0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u8 mode_tv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u8 USE_ISO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct cx231xx_tvnorm encodernorm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct cx231xx_tsport ts1, ts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct vb2_queue mpegq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct video_device v4l_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) atomic_t v4l_reader_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) unsigned int input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u32 cx23417_mailbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u32 __iomem *lmmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u8 __iomem *bmmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) extern struct list_head cx231xx_devlist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define cx25840_call(cx231xx, o, f, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) v4l2_subdev_call(cx231xx->sd_cx25840, o, f, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define tuner_call(cx231xx, o, f, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) v4l2_subdev_call(cx231xx->sd_tuner, o, f, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define call_all(dev, o, f, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) v4l2_device_call_until_err(&dev->v4l2_dev, 0, o, f, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct cx231xx_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct list_head next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int (*init) (struct cx231xx *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int (*fini) (struct cx231xx *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* call back functions in dvb module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int cx231xx_set_analog_freq(struct cx231xx *dev, u32 freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int cx231xx_reset_analog_tuner(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Provided by cx231xx-i2c.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) void cx231xx_do_i2c_scan(struct cx231xx *dev, int i2c_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int cx231xx_i2c_register(struct cx231xx_i2c *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) void cx231xx_i2c_unregister(struct cx231xx_i2c *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int cx231xx_i2c_mux_create(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int cx231xx_i2c_mux_register(struct cx231xx *dev, int mux_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) void cx231xx_i2c_mux_unregister(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct i2c_adapter *cx231xx_get_i2c_adap(struct cx231xx *dev, int i2c_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Internal block control functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) int cx231xx_read_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u8 saddr_len, u32 *data, u8 data_len, int master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int cx231xx_write_i2c_master(struct cx231xx *dev, u8 dev_addr, u16 saddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u8 saddr_len, u32 data, u8 data_len, int master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int cx231xx_read_i2c_data(struct cx231xx *dev, u8 dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u16 saddr, u8 saddr_len, u32 *data, u8 data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int cx231xx_write_i2c_data(struct cx231xx *dev, u8 dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u16 saddr, u8 saddr_len, u32 data, u8 data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int cx231xx_reg_mask_write(struct cx231xx *dev, u8 dev_addr, u8 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u16 register_address, u8 bit_start, u8 bit_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int cx231xx_read_modify_write_i2c_dword(struct cx231xx *dev, u8 dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u16 saddr, u32 mask, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 cx231xx_set_field(u32 field_mask, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /*verve r/w*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) void initGPIO(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) void uninitGPIO(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* afe related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) int cx231xx_afe_init_channels(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int cx231xx_afe_update_power_control(struct cx231xx *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) enum AV_MODE avmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* i2s block related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) int cx231xx_i2s_blk_initialize(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) enum AV_MODE avmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* DIF related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u32 function_mode, u32 standard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u8 spectral_invert, u32 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u8 spectral_invert, u32 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) void reset_s5h1432_demod(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) void cx231xx_dump_HH_reg(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) void update_HH_register_after_set_DIF(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int cx231xx_tuner_pre_channel_change(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int cx231xx_tuner_post_channel_change(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* video parser functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u8 cx231xx_find_next_SAV_EAV(u8 *p_buffer, u32 buffer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u32 *p_bytes_used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u8 cx231xx_find_boundary_SAV_EAV(u8 *p_buffer, u8 *partial_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u32 *p_bytes_used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int cx231xx_do_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u8 *p_buffer, u32 bytes_to_copy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) void cx231xx_reset_video_buffer(struct cx231xx *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct cx231xx_dmaqueue *dma_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u8 cx231xx_is_buffer_done(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 cx231xx_copy_video_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u8 *p_line, u32 length, int field_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u32 cx231xx_get_video_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u8 sav_eav, u8 *p_buffer, u32 buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) void cx231xx_swab(u16 *from, u16 *to, u16 len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* Provided by cx231xx-core.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 cx231xx_request_buffers(struct cx231xx *dev, u32 count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) void cx231xx_queue_unusedframes(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) void cx231xx_release_buffers(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* read from control pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) char *buf, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* write to control pipe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) int cx231xx_write_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) char *buf, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int cx231xx_mode_register(struct cx231xx *dev, u16 address, u32 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int cx231xx_send_vendor_cmd(struct cx231xx *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct VENDOR_REQUEST_IN *ven_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) int cx231xx_send_usb_command(struct cx231xx_i2c *i2c_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct cx231xx_i2c_xfer_data *req_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* Gpio related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) int cx231xx_send_gpio_cmd(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u8 len, u8 request, u8 direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int cx231xx_set_gpio_direction(struct cx231xx *dev, int pin_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int pin_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) int cx231xx_gpio_i2c_start(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int cx231xx_gpio_i2c_end(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* audio related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) enum AUDIO_INPUT audio_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) int cx231xx_set_video_alternate(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) int cx231xx_set_alt_setting(struct cx231xx *dev, u8 index, u8 alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int is_fw_load(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int cx231xx_check_fw(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int num_bufs, int max_pkt_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int (*isoc_copy) (struct cx231xx *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct urb *urb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int cx231xx_init_bulk(struct cx231xx *dev, int max_packets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int num_bufs, int max_pkt_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int (*bulk_copy) (struct cx231xx *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct urb *urb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) void cx231xx_stop_TS1(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) void cx231xx_start_TS1(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) void cx231xx_uninit_isoc(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) void cx231xx_uninit_bulk(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int cx231xx_unmute_audio(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int cx231xx_ep5_bulkout(struct cx231xx *dev, u8 *firmware, u16 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) void cx231xx_disable656(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) void cx231xx_enable656(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) int cx231xx_demod_reset(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int cx231xx_gpio_set(struct cx231xx *dev, struct cx231xx_reg_seq *gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Device list functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) void cx231xx_release_resources(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) void cx231xx_release_analog_resources(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) int cx231xx_register_analog_devices(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) void cx231xx_remove_from_devlist(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) void cx231xx_add_into_devlist(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) void cx231xx_init_extension(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) void cx231xx_close_extension(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* hardware init functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int cx231xx_dev_init(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) void cx231xx_dev_uninit(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) void cx231xx_config_i2c(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) int cx231xx_config(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* Stream control functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* Power control functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int cx231xx_power_suspend(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* chip specific control functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int cx231xx_init_ctrl_pin_status(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u8 analog_or_digital);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* video audio decoder related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) void video_mux(struct cx231xx *dev, int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) int cx231xx_set_audio_input(struct cx231xx *dev, u8 input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* Provided by cx231xx-video.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) int cx231xx_register_extension(struct cx231xx_ops *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) void cx231xx_unregister_extension(struct cx231xx_ops *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) void cx231xx_init_extension(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) void cx231xx_close_extension(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) void cx231xx_v4l2_create_entities(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) int cx231xx_querycap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct v4l2_capability *cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) int cx231xx_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) int cx231xx_s_tuner(struct file *file, void *priv, const struct v4l2_tuner *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) int cx231xx_g_frequency(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct v4l2_frequency *f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) int cx231xx_s_frequency(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) const struct v4l2_frequency *f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) int cx231xx_enum_input(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct v4l2_input *i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) int cx231xx_g_input(struct file *file, void *priv, unsigned int *i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int cx231xx_s_input(struct file *file, void *priv, unsigned int i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) int cx231xx_g_chip_info(struct file *file, void *fh, struct v4l2_dbg_chip_info *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) int cx231xx_g_register(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct v4l2_dbg_register *reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int cx231xx_s_register(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) const struct v4l2_dbg_register *reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* Provided by cx231xx-cards.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) extern void cx231xx_pre_card_setup(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) extern void cx231xx_card_setup(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) extern struct cx231xx_board cx231xx_boards[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) extern struct usb_device_id cx231xx_id_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) extern const unsigned int cx231xx_bcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) int cx231xx_tuner_callback(void *ptr, int component, int command, int arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* cx23885-417.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) extern int cx231xx_417_register(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) extern void cx231xx_417_unregister(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* cx23885-input.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #if defined(CONFIG_VIDEO_CX231XX_RC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) int cx231xx_ir_init(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) void cx231xx_ir_exit(struct cx231xx *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static inline int cx231xx_ir_init(struct cx231xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static inline void cx231xx_ir_exit(struct cx231xx *dev) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static inline unsigned int norm_maxw(struct cx231xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (dev->board.max_range_640_480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static inline unsigned int norm_maxh(struct cx231xx *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (dev->board.max_range_640_480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return (dev->norm & V4L2_STD_625_50) ? 576 : 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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