^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) cx231xx-reg.h - driver for Conexant Cx23100/101/102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) USB video capture devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _CX231XX_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _CX231XX_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * VBI codes *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SAV_ACTIVE_VIDEO_FIELD1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EAV_ACTIVE_VIDEO_FIELD1 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SAV_ACTIVE_VIDEO_FIELD2 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EAV_ACTIVE_VIDEO_FIELD2 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SAV_VBLANK_FIELD1 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EAV_VBLANK_FIELD1 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SAV_VBLANK_FIELD2 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EAV_VBLANK_FIELD2 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SAV_VBI_FIELD1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EAV_VBI_FIELD1 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SAV_VBI_FIELD2 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EAV_VBI_FIELD2 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Audio ADC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CH_PWR_CTRL1 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CH_PWR_CTRL2 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HOST_REG1 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FLD_FORCE_CHIP_SEL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FLD_AUTO_INC_DIS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FLD_PREFETCH_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Reserved [2:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FLD_DIGITAL_PWR_DN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FLD_SLEEP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HOST_REG2 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HOST_REG3 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* added for polaris */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GPIO_PIN_CTL0 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GPIO_PIN_CTL1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GPIO_PIN_CTL2 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPIO_PIN_CTL3 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TS1_PIN_CTL0 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TS1_PIN_CTL1 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FLD_CLK_IN_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FLD_XTAL_CTRL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FLD_BB_CLK_MODE 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FLD_REF_DIV_PLL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FLD_REF_SEL_PLL1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CHIP_CTRL 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Reserved [27] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Reserved [31:21] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FLD_CHIP_ACFG_DIS 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Reserved [19] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FLD_DUAL_MODE_ADC2 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FLD_SIF_EN 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FLD_SOFT_RST 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FLD_DEVICE_ID 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AFE_CTRL 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AFE_CTRL_C2HH_SRC_CTRL 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define FLD_DIF_OUT_SEL 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define FLD_AUX_PLL_CLK_ALT_SEL 0x3c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define FLD_UV_ORDER_MODE 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define FLD_FUNC_MODE 0x01800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define FLD_ROT1_PHASE_CTL 0x007f8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define FLD_AUD_IN_SEL 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define FLD_LUMA_IN_SEL 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define FLD_CHROMA_IN_SEL 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* reserve [11:10] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define FLD_INV_SPEC_DIS 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define FLD_VGA_SEL_CH3 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FLD_VGA_SEL_CH2 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define FLD_VGA_SEL_CH1 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define FLD_DCR_BYP_CH1 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FLD_DCR_BYP_CH2 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FLD_DCR_BYP_CH3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FLD_EN_12DB_CH3 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define FLD_EN_12DB_CH2 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define FLD_EN_12DB_CH1 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* redefine in Cx231xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DC_CTRL1 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* reserve [31:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define FLD_CLAMP_LVL_CH1 0x3fff8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define FLD_CLAMP_LVL_CH2 0x00007fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DC_CTRL2 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* reserve [31:28] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define FLD_CLAMP_LVL_CH3 0x00fffe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define FLD_CLAMP_WIND_LENTH 0x000001e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define FLD_C2HH_SAT_MIN 0x0000001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define FLD_FLT_BYP_SEL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DC_CTRL3 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* reserve [31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define FLD_ERR_GAIN_CTL 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define FLD_LPF_MIN 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DC_CTRL4 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* reserve [31:31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define FLD_INTG_CH1 0x7fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DC_CTRL5 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* reserve [31:31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define FLD_INTG_CH2 0x7fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DC_CTRL6 0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* reserve [31:31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FLD_INTG_CH3 0x7fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PIN_CTRL 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define FLD_OEF_AGC_RF 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define FLD_OEF_AGC_IFVGA 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define FLD_OEF_AGC_IF 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define FLD_REG_BO_PUD 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FLD_IR_IRQ_STAT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define FLD_AUD_IRQ_STAT 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define FLD_VID_IRQ_STAT 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Reserved [27:26] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define FLD_IRQ_N_OUT_EN 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define FLD_IRQ_N_POLAR 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Reserved [23:6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define FLD_OE_AUX_PLL_CLK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define FLD_OE_I2S_BCLK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FLD_OE_I2S_WCLK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define FLD_OE_AGC_IF 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FLD_OE_AGC_IFVGA 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define FLD_OE_AGC_RF 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AUD_IO_CTRL 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Reserved [31:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define FLD_I2S_PORT_DIR 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define FLD_I2S_OUT_SRC 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define FLD_AUD_CHAN3_SRC 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FLD_AUD_CHAN2_SRC 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FLD_AUD_CHAN1_SRC 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AUD_LOCK1 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define FLD_AUD_LOCK_KI_SHIFT 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define FLD_AUD_LOCK_KD_SHIFT 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Reserved [27:25] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define FLD_EN_AV_LOCK 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define FLD_VID_COUNT 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AUD_LOCK2 0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define FLD_AUD_LOCK_KI_MULT 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define FLD_AUD_LOCK_KD_MULT 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Reserved [23:22] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define FLD_AUD_LOCK_FREQ_SHIFT 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define FLD_AUD_COUNT 0x000fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AFE_DIAG_CTRL1 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Reserved [31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define FLD_CUV_DLY_LENGTH 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define FLD_YC_DLY_LENGTH 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Poalris redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AFE_DIAG_CTRL3 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Reserved [31:26] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define FLD_AUD_DUAL_FLAG_POL 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define FLD_VID_DUAL_FLAG_POL 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Reserved [23:23] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define FLD_COL_CLAMP_DIS_CH1 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define FLD_COL_CLAMP_DIS_CH2 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define FLD_COL_CLAMP_DIS_CH3 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TEST_CTRL1 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Reserved [31:29] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define FLD_LBIST_EN 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Reserved [27:10] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define FLD_FI_BIST_INTR_R 0x0000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define FLD_FI_BIST_INTR_L 0x0000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define FLD_BIST_FAIL_AUD_PLL 0x0000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define FLD_BIST_INTR_AUD_PLL 0x0000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define FLD_BIST_FAIL_VID_PLL 0x0000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define FLD_BIST_INTR_VID_PLL 0x0000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Reserved [3:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define FLD_CIR_TEST_DIS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TEST_CTRL2 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define FLD_TSXCLK_POL_CTL 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define FLD_ISO_CTL_SEL 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define FLD_ISO_CTL_EN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define FLD_BIST_DEBUGZ 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define FLD_AUD_BIST_TEST_H 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Reserved [23:22] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define FLD_FLTRN_BIST_TEST_H 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define FLD_VID_BIST_TEST_H 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Reserved [19:17] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define FLD_BIST_TEST_H 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Reserved [15:13] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define FLD_TAB_EN 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Reserved [11:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define BIST_STAT 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define FLD_AUD_BIST_FAIL_H 0xfff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define FLD_FLTRN_BIST_FAIL_H 0x00180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define FLD_VID_BIST_FAIL_H 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define FLD_AUD_BIST_TST_DONE 0x0000fff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define FLD_FLTRN_BIST_TST_DONE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define FLD_VID_BIST_TST_DONE 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* DirectIF registers definition have been moved to DIF_reg.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MODE_CTRL 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define FLD_AFD_PAL60_DIS 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define FLD_AFD_FORCE_SECAM 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define FLD_AFD_FORCE_PALNC 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define FLD_AFD_FORCE_PAL 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define FLD_AFD_PALM_SEL 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define FLD_CKILL_MODE 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define FLD_CLR_LOCK_STAT 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define FLD_FAST_LOCK_MD 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define FLD_WCEN 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define FLD_CAGCEN 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define FLD_CKILLEN 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define FLD_AUTO_SC_LOCK 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define FLD_MAN_SC_FAST_LOCK 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define FLD_INPUT_MODE 0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define FLD_AFD_ACQUIRE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define FLD_AFD_NTSC_SEL 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define FLD_AFD_PAL_SEL 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define FLD_ACFG_DIS 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define FLD_SQ_PIXEL 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define FLD_VID_FMT_SEL 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define OUT_CTRL1 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define FLD_POLAR 0x7f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Reserved [23] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define FLD_RND_MODE 0x00600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define FLD_VIPCLAMP_EN 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define FLD_VIPBLANK_EN 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define FLD_VIP_OPT_AL 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define FLD_IDID0_SOURCE 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define FLD_DCMODE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define FLD_CLK_GATING 0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define FLD_CLK_INVERT 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define FLD_HSFMT 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define FLD_VALIDFMT 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define FLD_ACTFMT 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define FLD_SWAPRAW 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define FLD_CLAMPRAW_EN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define FLD_BLUE_FIELD_EN 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define FLD_BLUE_FIELD_ACT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define FLD_TASKBIT_VAL 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define FLD_ANC_DATA_EN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define FLD_VBIHACTRAW_EN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define FLD_MODE10B 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define FLD_OUT_MODE 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define OUT_CTRL2 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define FLD_AUD_GRP 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define FLD_SAMPLE_RATE 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define FLD_AUD_ANC_EN 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define FLD_EN_C 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define FLD_EN_B 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define FLD_EN_A 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Reserved [23:20] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define FLD_IDID1_LSB 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define FLD_IDID0_LSB 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define FLD_IDID1_MSB 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define FLD_IDID0_MSB 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define GEN_STAT 0x40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define FLD_VCR_DETECT 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define FLD_SPECIAL_PLAY_N 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define FLD_VPRES 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define FLD_AGC_LOCK 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define FLD_CSC_LOCK 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define FLD_VLOCK 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define FLD_SRC_LOCK 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define FLD_HLOCK 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define FLD_VSYNC_N 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define FLD_SRC_FIFO_UFLOW 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define FLD_SRC_FIFO_OFLOW 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define FLD_FIELD 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define FLD_AFD_FMT_STAT 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define FLD_MV_TYPE2_PAIR 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define FLD_MV_T3CS 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define FLD_MV_CS 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define FLD_MV_PSP 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Reserved [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define FLD_MV_CDAT 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define INT_STAT_MASK 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define FLD_COMB_3D_FIFO_MSK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define FLD_WSS_DAT_AVAIL_MSK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define FLD_GS2_DAT_AVAIL_MSK 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define FLD_GS1_DAT_AVAIL_MSK 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define FLD_CC_DAT_AVAIL_MSK 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define FLD_VPRES_CHANGE_MSK 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define FLD_MV_CHANGE_MSK 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define FLD_END_VBI_EVEN_MSK 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define FLD_END_VBI_ODD_MSK 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define FLD_FMT_CHANGE_MSK 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define FLD_VSYNC_TRAIL_MSK 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define FLD_HLOCK_CHANGE_MSK 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define FLD_VLOCK_CHANGE_MSK 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define FLD_CSC_LOCK_CHANGE_MSK 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define FLD_SRC_FIFO_UFLOW_MSK 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define FLD_SRC_FIFO_OFLOW_MSK 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define FLD_COMB_3D_FIFO_STAT 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define FLD_WSS_DAT_AVAIL_STAT 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define FLD_GS2_DAT_AVAIL_STAT 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define FLD_GS1_DAT_AVAIL_STAT 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define FLD_CC_DAT_AVAIL_STAT 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define FLD_VPRES_CHANGE_STAT 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define FLD_MV_CHANGE_STAT 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define FLD_END_VBI_EVEN_STAT 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define FLD_END_VBI_ODD_STAT 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define FLD_FMT_CHANGE_STAT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define FLD_VSYNC_TRAIL_STAT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define FLD_HLOCK_CHANGE_STAT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define FLD_VLOCK_CHANGE_STAT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define FLD_CSC_LOCK_CHANGE_STAT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define FLD_SRC_FIFO_UFLOW_STAT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define FLD_SRC_FIFO_OFLOW_STAT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define LUMA_CTRL 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define BRIGHTNESS_CTRL_BYTE 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CONTRAST_CTRL_BYTE 0x415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define LUMA_CTRL_BYTE_3 0x416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define FLD_LUMA_CORE_SEL 0x00c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define FLD_RANGE 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Reserved [19] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define FLD_PEAK_EN 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define FLD_PEAK_SEL 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define FLD_CNTRST 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define FLD_BRITE 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define HSCALE_CTRL 0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define FLD_HFILT 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define FLD_HSCALE 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define VSCALE_CTRL 0x41c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define FLD_LINE_AVG_DIS 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Reserved [23:20] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define FLD_VS_INTRLACE 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define FLD_VFILT 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Reserved [15:13] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define FLD_VSCALE 0x00001fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define CHROMA_CTRL 0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define USAT_CTRL_BYTE 0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define VSAT_CTRL_BYTE 0x421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define HUE_CTRL_BYTE 0x422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define FLD_C_LPF_EN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define FLD_CHR_DELAY 0x1c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define FLD_C_CORE_SEL 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define FLD_HUE 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define FLD_VSAT 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define FLD_USAT 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define VBI_LINE_CTRL1 0x424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define FLD_VBI_MD_LINE4 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define FLD_VBI_MD_LINE3 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define FLD_VBI_MD_LINE2 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define FLD_VBI_MD_LINE1 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define VBI_LINE_CTRL2 0x428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define FLD_VBI_MD_LINE8 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define FLD_VBI_MD_LINE7 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define FLD_VBI_MD_LINE6 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define FLD_VBI_MD_LINE5 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define VBI_LINE_CTRL3 0x42c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define FLD_VBI_MD_LINE12 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define FLD_VBI_MD_LINE11 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define FLD_VBI_MD_LINE10 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define FLD_VBI_MD_LINE9 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define VBI_LINE_CTRL4 0x430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define FLD_VBI_MD_LINE16 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define FLD_VBI_MD_LINE15 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define FLD_VBI_MD_LINE14 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define FLD_VBI_MD_LINE13 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define VBI_LINE_CTRL5 0x434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define FLD_VBI_MD_LINE17 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define VBI_FC_CFG 0x438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define FLD_FC_ALT2 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define FLD_FC_ALT1 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define FLD_FC_ALT2_TYPE 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define FLD_FC_ALT1_TYPE 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Reserved [7:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define FLD_FC_SEARCH_MODE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define VBI_MISC_CFG1 0x43c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define FLD_TTX_PKTADRU 0xfff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define FLD_TTX_PKTADRL 0x000fff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Reserved [7:6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define FLD_MOJI_PACK_DIS 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define FLD_VPS_DEC_DIS 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define FLD_CRI_MARG_SCALE 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define FLD_EDGE_RESYNC_EN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define FLD_ADAPT_SLICE_DIS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define VBI_MISC_CFG2 0x440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define FLD_HAMMING_TYPE 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Reserved [23:20] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define FLD_WSS_FIFO_RST 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define FLD_GS2_FIFO_RST 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define FLD_GS1_FIFO_RST 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define FLD_CC_FIFO_RST 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Reserved [15:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define FLD_VBI3_SDID 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define FLD_VBI2_SDID 0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define FLD_VBI1_SDID 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define VBI_PAY1 0x444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define FLD_GS1_FIFO_DAT 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define FLD_GS1_STAT 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define FLD_CC_FIFO_DAT 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define FLD_CC_STAT 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define VBI_PAY2 0x448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define FLD_WSS_FIFO_DAT 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define FLD_WSS_STAT 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define FLD_GS2_FIFO_DAT 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define FLD_GS2_STAT 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define VBI_CUST1_CFG1 0x44c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Reserved [31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define FLD_VBI1_CRIWIN 0x7f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define FLD_VBI1_SLICE_DIST 0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define FLD_VBI1_BITINC 0x000fff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define FLD_VBI1_HDELAY 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define VBI_CUST1_CFG2 0x450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define FLD_VBI1_FC_LENGTH 0x1f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define FLD_VBI1_FRAME_CODE 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define VBI_CUST1_CFG3 0x454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define FLD_VBI1_HAM_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define FLD_VBI1_FIFO_MODE 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define FLD_VBI1_FORMAT_TYPE 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define FLD_VBI1_PAYLD_LENGTH 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define FLD_VBI1_CRI_LENGTH 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define FLD_VBI1_CRI_MARGIN 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define FLD_VBI1_CRI_TIME 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define VBI_CUST2_CFG1 0x458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Reserved [31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define FLD_VBI2_CRIWIN 0x7f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define FLD_VBI2_SLICE_DIST 0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define FLD_VBI2_BITINC 0x000fff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define FLD_VBI2_HDELAY 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define VBI_CUST2_CFG2 0x45c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define FLD_VBI2_FC_LENGTH 0x1f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define FLD_VBI2_FRAME_CODE 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define VBI_CUST2_CFG3 0x460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define FLD_VBI2_HAM_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define FLD_VBI2_FIFO_MODE 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define FLD_VBI2_FORMAT_TYPE 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define FLD_VBI2_PAYLD_LENGTH 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define FLD_VBI2_CRI_LENGTH 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define FLD_VBI2_CRI_MARGIN 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define FLD_VBI2_CRI_TIME 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define VBI_CUST3_CFG1 0x464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Reserved [31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define FLD_VBI3_CRIWIN 0x7f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define FLD_VBI3_SLICE_DIST 0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define FLD_VBI3_BITINC 0x000fff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define FLD_VBI3_HDELAY 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define VBI_CUST3_CFG2 0x468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define FLD_VBI3_FC_LENGTH 0x1f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define FLD_VBI3_FRAME_CODE 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define VBI_CUST3_CFG3 0x46c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define FLD_VBI3_HAM_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define FLD_VBI3_FIFO_MODE 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define FLD_VBI3_FORMAT_TYPE 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define FLD_VBI3_PAYLD_LENGTH 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define FLD_VBI3_CRI_LENGTH 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define FLD_VBI3_CRI_MARGIN 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define FLD_VBI3_CRI_TIME 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define HORIZ_TIM_CTRL 0x470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define FLD_BGDEL_CNT 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Reserved [23:22] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define FLD_HACTIVE_CNT 0x003ff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Reserved [11:10] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define FLD_HBLANK_CNT 0x000003ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define VERT_TIM_CTRL 0x474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define FLD_V656BLANK_CNT 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Reserved [23:22] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define FLD_VACTIVE_CNT 0x003ff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Reserved [11:10] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define FLD_VBLANK_CNT 0x000003ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define SRC_COMB_CFG 0x478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define FLD_CCOMB_2LN_CHECK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define FLD_CCOMB_3LN_EN 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define FLD_CCOMB_2LN_EN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define FLD_CCOMB_3D_EN 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Reserved [27] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define FLD_LCOMB_3LN_EN 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define FLD_LCOMB_2LN_EN 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define FLD_LCOMB_3D_EN 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define FLD_LUMA_LPF_SEL 0x00c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define FLD_UV_LPF_SEL 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define FLD_BLEND_SLOPE 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define FLD_CCOMB_REDUCE_EN 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Reserved [14:10] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define FLD_SRC_DECIM_RATIO 0x000003ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define CHROMA_VBIOFF_CFG 0x47c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define FLD_VBI_VOFFSET 0x1f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Reserved [23:20] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define FLD_SC_STEP 0x000fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define FIELD_COUNT 0x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define FLD_FIELD_COUNT_FLD 0x000003ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define MISC_TIM_CTRL 0x484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define FLD_DEBOUNCE_COUNT 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define FLD_VT_LINE_CNT_HYST 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Reserved [27] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define FLD_AFD_STAT 0x07ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define FLD_VPRES_VERT_EN 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Reserved [14:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define FLD_HR32 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define FLD_TDALGN 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define FLD_TDFIELD 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Reserved [8:6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define FLD_TEMPDEC 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define DFE_CTRL1 0x488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define FLD_CLAMP_AUTO_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define FLD_AGC_AUTO_EN 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define FLD_VGA_CRUSH_EN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define FLD_VGA_AUTO_EN 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define FLD_VBI_GATE_EN 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define FLD_CLAMP_LEVEL 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Reserved [23:22] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define FLD_CLAMP_SKIP_CNT 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define FLD_AGC_GAIN 0x000fff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Reserved [7:6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define FLD_VGA_GAIN 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define DFE_CTRL2 0x48c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define FLD_VGA_ACQUIRE_RANGE 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define FLD_VGA_TRACK_RANGE 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define FLD_VGA_SYNC 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define DFE_CTRL3 0x490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define FLD_BP_PERCENT 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define FLD_DFT_THRESHOLD 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* Reserved [15:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define FLD_SYNC_WIDTH_SEL 0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define FLD_BP_LOOP_GAIN 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define FLD_SYNC_LOOP_GAIN 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Reserved [5:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define FLD_AGC_LOOP_GAIN 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define FLD_DCC_LOOP_GAIN 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define PLL_CTRL 0x494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define FLD_PLL_KD 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define FLD_PLL_KI 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define FLD_PLL_MAX_OFFSET 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define HTL_CTRL 0x498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* Reserved [31:24] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define FLD_AUTO_LOCK_SPD 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define FLD_MAN_FAST_LOCK 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define FLD_HTL_15K_EN 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define FLD_HTL_500K_EN 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define FLD_HTL_KD 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define FLD_HTL_KI 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define COMB_CTRL 0x49c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define FLD_COMB_PHASE_LIMIT 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define FLD_CCOMB_ERR_LIMIT 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define FLD_LUMA_THRESHOLD 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define FLD_LCOMB_ERR_LIMIT 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define CRUSH_CTRL 0x4a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define FLD_WTW_EN 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define FLD_CRUSH_FREQ 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define FLD_MAJ_SEL_EN 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define FLD_MAJ_SEL 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Reserved [17:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define FLD_SYNC_TIP_REDUCE 0x00007e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Reserved [8:6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define FLD_SYNC_TIP_INC 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define SOFT_RST_CTRL 0x4a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define FLD_VD_SOFT_RST 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Reserved [14:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define FLD_REG_RST_MSK 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define FLD_VOF_RST_MSK 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define FLD_MVDET_RST_MSK 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define FLD_VBI_RST_MSK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define FLD_SCALE_RST_MSK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define FLD_CHROMA_RST_MSK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define FLD_LUMA_RST_MSK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define FLD_VTG_RST_MSK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define FLD_YCSEP_RST_MSK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define FLD_SRC_RST_MSK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define FLD_DFE_RST_MSK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* Reserved [0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define MV_DT_CTRL1 0x4a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Reserved [31:29] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define FLD_PSP_STOP_LINE 0x1f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* Reserved [23:21] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define FLD_PSP_STRT_LINE 0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* Reserved [15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define FLD_PSP_LLIMW 0x00007f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Reserved [7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define FLD_PSP_ULIMW 0x0000007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define MV_DT_CTRL2 0x4aC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define FLD_CS_STOPWIN 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define FLD_CS_STRTWIN 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define FLD_CS_WIDTH 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define FLD_PSP_SPEC_VAL 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define MV_DT_CTRL3 0x4B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define FLD_AUTO_RATE_DIS 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define FLD_HLOCK_DIS 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define FLD_SEL_FIELD_CNT 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define FLD_CS_TYPE2_SEL 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define FLD_CS_LINE_THRSH_SEL 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define FLD_CS_ATHRESH_SEL 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define FLD_PSP_SPEC_SEL 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define FLD_PSP_LINES_SEL 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define FLD_FIELD_CNT 0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define FLD_CS_TYPE2_CNT 0x000fc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define FLD_CS_LINE_CNT 0x00003f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define FLD_CS_ATHRESH_LEV 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define CHIP_VERSION 0x4b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define VERSION 0x4b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define FLD_REV_ID 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define MISC_DIAG_CTRL 0x4b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Reserved [31:24] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define FLD_SC_CONVERGE_THRESH 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define FLD_CCOMB_ERR_LIMIT_3D 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define FLD_LCOMB_ERR_LIMIT_3D 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define VBI_PASS_CTRL 0x4bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define FLD_VBI_PASS_MD 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define FLD_VBI_SETUP_DIS 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define FLD_PASS_LINE_CTRL 0x000fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define VCR_DET_CTRL 0x4c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define FLD_EN_FIELD_PHASE_DET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define FLD_EN_HEAD_SW_DET 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define FLD_FIELD_PHASE_LENGTH 0x01ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Reserved [29:25] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define FLD_FIELD_PHASE_DELAY 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define FLD_FIELD_PHASE_LIMIT 0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define FLD_HEAD_SW_DET_LIMIT 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define DL_CTL 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Reserved [31:5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define FLD_START_8051 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define FLD_DL_ENABLE 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define FLD_DL_AUTO_INC 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define FLD_DL_MAP 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define STD_DET_STATUS 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define FLD_SPARE_STATUS1 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define FLD_SPARE_STATUS0 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define FLD_MOD_DET_STATUS1 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define FLD_MOD_DET_STATUS0 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define AUD_BUILD_NUM 0x806
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define AUD_VER_NUM 0x807
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define STD_DET_CTL 0x808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define FLD_SPARE_CTL0 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define FLD_DIS_DBX 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define FLD_DIS_BTSC 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define FLD_DIS_NICAM_A2 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define FLD_VIDEO_PRESENT 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define FLD_DW8051_VIDEO_FORMAT 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define FLD_PREF_DEC_MODE 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define FLD_AUD_CONFIG 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define DW8051_INT 0x80c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define FLD_VIDEO_PRESENT_CHANGE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define FLD_VIDEO_CHANGE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define FLD_RDS_READY 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define FLD_AC97_INT 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define FLD_NICAM_BIT_ERROR_TOO_HIGH 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define FLD_NICAM_LOCK 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define FLD_NICAM_UNLOCK 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define FLD_DFT4_TH_CMP 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* Reserved [23:22] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define FLD_LOCK_IND_INT 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define FLD_DFT3_TH_CMP 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define FLD_DFT2_TH_CMP 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define FLD_DFT1_TH_CMP 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define FLD_FM2_DFT_TH_CMP 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define FLD_FM1_DFT_TH_CMP 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define FLD_VIDEO_PRESENT_EN 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define FLD_VIDEO_CHANGE_EN 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define FLD_RDS_READY_EN 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define FLD_AC97_INT_EN 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define FLD_NICAM_BIT_ERROR_TOO_HIGH_EN 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define FLD_NICAM_LOCK_EN 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define FLD_NICAM_UNLOCK_EN 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define FLD_DFT4_TH_CMP_EN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Reserved [7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define FLD_DW8051_INT6_CTL1 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define FLD_DW8051_INT5_CTL1 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define FLD_DW8051_INT4_CTL1 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define FLD_DW8051_INT3_CTL1 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define FLD_DW8051_INT2_CTL1 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define FLD_DW8051_INT1_CTL1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define FLD_DW8051_INT0_CTL1 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define GENERAL_CTL 0x810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define FLD_RDS_INT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define FLD_NBER_INT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define FLD_NLL_INT 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define FLD_IFL_INT 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define FLD_FDL_INT 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define FLD_AFC_INT 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define FLD_AMC_INT 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define FLD_AC97_INT_CTL 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define FLD_RDS_INT_DIS 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define FLD_NBER_INT_DIS 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define FLD_NLL_INT_DIS 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define FLD_IFL_INT_DIS 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define FLD_FDL_INT_DIS 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define FLD_FC_INT_DIS 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define FLD_AMC_INT_DIS 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define FLD_AC97_INT_DIS 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define FLD_REV_NUM 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* Reserved [7:5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define FLD_DBX_SOFT_RESET_REG 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define FLD_AD_SOFT_RESET_REG 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define FLD_SRC_SOFT_RESET_REG 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define FLD_CDMOD_SOFT_RESET 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define FLD_8051_SOFT_RESET 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define AAGC_CTL 0x814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define FLD_AFE_12DB_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define FLD_AAGC_DEFAULT_EN 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define FLD_AAGC_DEFAULT 0x3f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* Reserved [23] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define FLD_AAGC_GAIN 0x00600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define FLD_AAGC_TH 0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* Reserved [15:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define FLD_AAGC_HYST2 0x00003f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* Reserved [7:6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define FLD_AAGC_HYST1 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define IF_SRC_CTL 0x818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define FLD_DBX_BYPASS 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Reserved [30:25] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define FLD_IF_SRC_MODE 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Reserved [23:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define FLD_IF_SRC_PHASE_INC 0x0001ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define ANALOG_DEMOD_CTL 0x81c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define FLD_ROT1_PHACC_PROG 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* Reserved [15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define FLD_FM1_DELAY_FIX 0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define FLD_PDF4_SHIFT 0x00000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define FLD_PDF3_SHIFT 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define FLD_PDF2_SHIFT 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define FLD_PDF1_SHIFT 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define FLD_FMBYPASS_MODE2 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define FLD_FMBYPASS_MODE1 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define FLD_NICAM_MODE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define FLD_BTSC_FMRADIO_MODE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define ROT_FREQ_CTL 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define FLD_ROT3_PHACC_PROG 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define FLD_ROT2_PHACC_PROG 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define FM_CTL 0x824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define FLD_FM2_DC_FB_SHIFT 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define FLD_FM2_DC_INT_SHIFT 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define FLD_FM2_AFC_RESET 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define FLD_FM2_DC_PASS_IN 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define FLD_FM2_DAGC_SHIFT 0x00380000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define FLD_FM2_CORDIC_SHIFT 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define FLD_FM1_DC_FB_SHIFT 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define FLD_FM1_DC_INT_SHIFT 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define FLD_FM1_AFC_RESET 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define FLD_FM1_DC_PASS_IN 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define FLD_FM1_DAGC_SHIFT 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define FLD_FM1_CORDIC_SHIFT 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define LPF_PDF_CTL 0x828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* Reserved [31:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define FLD_LPF32_SHIFT1 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define FLD_LPF32_SHIFT2 0x0c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define FLD_LPF160_SHIFTA 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define FLD_LPF160_SHIFTB 0x00c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define FLD_LPF160_SHIFTC 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define FLD_LPF32_COEF_SEL2 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define FLD_LPF32_COEF_SEL1 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define FLD_LPF160_COEF_SELC 0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define FLD_LPF160_COEF_SELB 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define FLD_LPF160_COEF_SELA 0x00000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define FLD_LPF160_IN_EN_REG 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define FLD_PDF4_PDF_SEL 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define FLD_PDF3_PDF_SEL 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define FLD_PDF2_PDF_SEL 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define FLD_PDF1_PDF_SEL 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define DFT1_CTL1 0x82c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define FLD_DFT1_DWELL 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define FLD_DFT1_FREQ 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define DFT1_CTL2 0x830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define FLD_DFT1_THRESHOLD 0xffffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define FLD_DFT1_CMP_CTL 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define FLD_DFT1_AVG 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Reserved [3:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define FLD_DFT1_START 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define DFT1_STATUS 0x834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define FLD_DFT1_DONE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define FLD_DFT1_TH_CMP_STAT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define FLD_DFT1_RESULT 0x3fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define DFT2_CTL1 0x838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define FLD_DFT2_DWELL 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define FLD_DFT2_FREQ 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define DFT2_CTL2 0x83C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define FLD_DFT2_THRESHOLD 0xffffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define FLD_DFT2_CMP_CTL 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define FLD_DFT2_AVG 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* Reserved [3:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define FLD_DFT2_START 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define DFT2_STATUS 0x840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define FLD_DFT2_DONE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define FLD_DFT2_TH_CMP_STAT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define FLD_DFT2_RESULT 0x3fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define DFT3_CTL1 0x844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define FLD_DFT3_DWELL 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define FLD_DFT3_FREQ 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define DFT3_CTL2 0x848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define FLD_DFT3_THRESHOLD 0xffffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define FLD_DFT3_CMP_CTL 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define FLD_DFT3_AVG 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Reserved [3:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define FLD_DFT3_START 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define DFT3_STATUS 0x84c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define FLD_DFT3_DONE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define FLD_DFT3_TH_CMP_STAT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define FLD_DFT3_RESULT 0x3fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define DFT4_CTL1 0x850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define FLD_DFT4_DWELL 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define FLD_DFT4_FREQ 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define DFT4_CTL2 0x854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define FLD_DFT4_THRESHOLD 0xffffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define FLD_DFT4_CMP_CTL 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define FLD_DFT4_AVG 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* Reserved [3:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define FLD_DFT4_START 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define DFT4_STATUS 0x858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define FLD_DFT4_DONE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define FLD_DFT4_TH_CMP_STAT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define FLD_DFT4_RESULT 0x3fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define AM_MTS_DET 0x85c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define FLD_AM_MTS_MODE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* Reserved [30:26] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define FLD_AM_SUB 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define FLD_AM_GAIN_EN 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* Reserved [23:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define FLD_AMMTS_GAIN_SCALE 0x0000e000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define FLD_MTS_PDF_SHIFT 0x00001800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define FLD_AM_REG_GAIN 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define FLD_AGC_REF 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define ANALOG_MUX_CTL 0x860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* Reserved [31:29] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define FLD_MUX21_SEL 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define FLD_MUX20_SEL 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define FLD_MUX19_SEL 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define FLD_MUX18_SEL 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define FLD_MUX17_SEL 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define FLD_MUX16_SEL 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define FLD_MUX15_SEL 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define FLD_MUX14_SEL 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define FLD_MUX13_SEL 0x000C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define FLD_MUX12_SEL 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define FLD_MUX11_SEL 0x00018000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define FLD_MUX10_SEL 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define FLD_MUX9_SEL 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define FLD_MUX8_SEL 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define FLD_MUX7_SEL 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define FLD_MUX6_SEL 0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define FLD_MUX5_SEL 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define FLD_MUX4_SEL 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define FLD_MUX3_SEL 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define FLD_MUX2_SEL 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define FLD_MUX1_SEL 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define DPLL_CTRL1 0x864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define DIG_PLL_CTL1 0x864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define FLD_PLL_STATUS 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define FLD_BANDWIDTH_SELECT 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define FLD_PLL_SHIFT_REG 0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define FLD_PHASE_SHIFT 0x000007ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define DPLL_CTRL2 0x868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define DIG_PLL_CTL2 0x868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define FLD_PLL_UNLOCK_THR 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define FLD_PLL_LOCK_THR 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Reserved [15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define FLD_AM_PDF_SEL2 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define FLD_AM_PDF_SEL1 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define FLD_DPLL_FSM_CTRL 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* Reserved [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define FLD_PLL_PILOT_DET 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define DPLL_CTRL3 0x86c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define DIG_PLL_CTL3 0x86c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define FLD_DISABLE_LOOP 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define FLD_A1_DS1_SEL 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define FLD_A1_DS2_SEL 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define FLD_A1_KI 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define FLD_A1_KD 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define DPLL_CTRL4 0x870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define DIG_PLL_CTL4 0x870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define FLD_A2_DS1_SEL 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define FLD_A2_DS2_SEL 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define FLD_A2_KI 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define FLD_A2_KD 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define DPLL_CTRL5 0x874
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define DIG_PLL_CTL5 0x874
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define FLD_TRK_DS1_SEL 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define FLD_TRK_DS2_SEL 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define FLD_TRK_KI 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define FLD_TRK_KD 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define DEEMPH_GAIN_CTL 0x878
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define FLD_DEEMPH2_GAIN 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define FLD_DEEMPH1_GAIN 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define DEEMPH_COEFF1 0x87c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define DEEMPH_COEF1 0x87c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define FLD_DEEMPH_B0 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define FLD_DEEMPH_A0 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define DEEMPH_COEFF2 0x880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define DEEMPH_COEF2 0x880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define FLD_DEEMPH_B1 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define FLD_DEEMPH_A1 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define DBX1_CTL1 0x884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define FLD_DBX1_WBE_GAIN 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define FLD_DBX1_IN_GAIN 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define DBX1_CTL2 0x888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define FLD_DBX1_SE_BYPASS 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define FLD_DBX1_SE_GAIN 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define DBX1_RMS_SE 0x88C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define FLD_DBX1_RMS_WBE 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define FLD_DBX1_RMS_SE_FLD 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define DBX2_CTL1 0x890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define FLD_DBX2_WBE_GAIN 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define FLD_DBX2_IN_GAIN 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define DBX2_CTL2 0x894
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define FLD_DBX2_SE_BYPASS 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define FLD_DBX2_SE_GAIN 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define DBX2_RMS_SE 0x898
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define FLD_DBX2_RMS_WBE 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define FLD_DBX2_RMS_SE_FLD 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define AM_FM_DIFF 0x89c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* Reserved [31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define FLD_FM_DIFF_OUT 0x7fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* Reserved [15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define FLD_AM_DIFF_OUT 0x00007fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define NICAM_FAW 0x8a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define FLD_FAWDETWINEND 0xFc000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define FLD_FAWDETWINSTR 0x03ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* Reserved [15:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define FLD_FAWDETTHRSHLD3 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define FLD_FAWDETTHRSHLD2 0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define FLD_FAWDETTHRSHLD1 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define DEEMPH_GAIN 0x8a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define NICAM_DEEMPHGAIN 0x8a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* Reserved [31:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define FLD_DEEMPHGAIN 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define DEEMPH_NUMER1 0x8a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define NICAM_DEEMPHNUMER1 0x8a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* Reserved [31:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define FLD_DEEMPHNUMER1 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define DEEMPH_NUMER2 0x8ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define NICAM_DEEMPHNUMER2 0x8ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* Reserved [31:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define FLD_DEEMPHNUMER2 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define DEEMPH_DENOM1 0x8b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define NICAM_DEEMPHDENOM1 0x8b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* Reserved [31:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define FLD_DEEMPHDENOM1 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define DEEMPH_DENOM2 0x8b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define NICAM_DEEMPHDENOM2 0x8b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* Reserved [31:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define FLD_DEEMPHDENOM2 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define NICAM_ERRLOG_CTL1 0x8B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* Reserved [31:28] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define FLD_ERRINTRPTTHSHLD1 0x0fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* Reserved [15:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define FLD_ERRLOGPERIOD 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define NICAM_ERRLOG_CTL2 0x8bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /* Reserved [31:28] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define FLD_ERRINTRPTTHSHLD3 0x0fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* Reserved [15:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define FLD_ERRINTRPTTHSHLD2 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define NICAM_ERRLOG_STS1 0x8c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* Reserved [31:28] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define FLD_ERRLOG2 0x0fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* Reserved [15:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define FLD_ERRLOG1 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define NICAM_ERRLOG_STS2 0x8c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* Reserved [31:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define FLD_ERRLOG3 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define NICAM_STATUS 0x8c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* Reserved [31:20] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define FLD_NICAM_CIB 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define FLD_NICAM_LOCK_STAT 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define FLD_NICAM_MUTE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define FLD_NICAMADDIT_DATA 0x0000ffe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define FLD_NICAMCNTRL 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define DEMATRIX_CTL 0x8cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define FLD_AC97_IN_SHIFT 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define FLD_I2S_IN_SHIFT 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define FLD_DEMATRIX_SEL_CTL 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* Reserved [15:11] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define FLD_DMTRX_BYPASS 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define FLD_DEMATRIX_MODE 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* Reserved [7:6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define FLD_PH_DBX_SEL 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define FLD_PH_CH_SEL 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define FLD_PHASE_FIX 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define PATH1_CTL1 0x8d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Reserved [31:29] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define FLD_PATH1_MUTE_CTL 0x1f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* Reserved [23:22] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define FLD_PATH1_AVC_CG 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define FLD_PATH1_AVC_RT 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define FLD_PATH1_AVC_AT 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define FLD_PATH1_AVC_STEREO 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define FLD_PATH1_AVC_CR 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define FLD_PATH1_AVC_RMS_CON 0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define FLD_PATH1_SEL_CTL 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define PATH1_VOL_CTL 0x8d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define FLD_PATH1_AVC_THRESHOLD 0x7fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define FLD_PATH1_BAL_LEFT 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define FLD_PATH1_BAL_LEVEL 0x00007f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define FLD_PATH1_VOLUME 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define PATH1_EQ_CTL 0x8d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* Reserved [31:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define FLD_PATH1_EQ_TREBLE_VOL 0x3f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* Reserved [23:22] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define FLD_PATH1_EQ_MID_VOL 0x003f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* Reserved [15:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define FLD_PATH1_EQ_BASS_VOL 0x00003f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* Reserved [7:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define FLD_PATH1_EQ_BAND_SEL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define PATH1_SC_CTL 0x8dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define FLD_PATH1_SC_THRESHOLD 0x7fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define FLD_PATH1_SC_RT 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define FLD_PATH1_SC_AT 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define FLD_PATH1_SC_STEREO 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define FLD_PATH1_SC_CR 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define FLD_PATH1_SC_RMS_CON 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define PATH2_CTL1 0x8e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* Reserved [31:26] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define FLD_PATH2_MUTE_CTL 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* Reserved [23:22] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define FLD_PATH2_AVC_CG 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define FLD_PATH2_AVC_RT 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define FLD_PATH2_AVC_AT 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define FLD_PATH2_AVC_STEREO 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define FLD_PATH2_AVC_CR 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define FLD_PATH2_AVC_RMS_CON 0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define FLD_PATH2_SEL_CTL 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define PATH2_VOL_CTL 0x8e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define FLD_PATH2_AVC_THRESHOLD 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define FLD_PATH2_BAL_LEFT 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define FLD_PATH2_BAL_LEVEL 0x00007f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define FLD_PATH2_VOLUME 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define PATH2_EQ_CTL 0x8e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /* Reserved [31:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define FLD_PATH2_EQ_TREBLE_VOL 0x3f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* Reserved [23:22] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define FLD_PATH2_EQ_MID_VOL 0x003f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* Reserved [15:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define FLD_PATH2_EQ_BASS_VOL 0x00003f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /* Reserved [7:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define FLD_PATH2_EQ_BAND_SEL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define PATH2_SC_CTL 0x8eC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define FLD_PATH2_SC_THRESHOLD 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define FLD_PATH2_SC_RT 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define FLD_PATH2_SC_AT 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define FLD_PATH2_SC_STEREO 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define FLD_PATH2_SC_CR 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define FLD_PATH2_SC_RMS_CON 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define SRC_CTL 0x8f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define FLD_SRC_STATUS 0xffffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define FLD_FIFO_LF_EN 0x000000fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define FLD_BYPASS_LI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define FLD_BYPASS_PF 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define SRC_LF_COEF 0x8f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define FLD_LOOP_FILTER_COEF2 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define FLD_LOOP_FILTER_COEF1 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define SRC1_CTL 0x8f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* Reserved [31:28] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define FLD_SRC1_FIFO_RD_TH 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* Reserved [23:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define FLD_SRC1_PHASE_INC 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define SRC2_CTL 0x8fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /* Reserved [31:28] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define FLD_SRC2_FIFO_RD_TH 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* Reserved [23:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define FLD_SRC2_PHASE_INC 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define SRC3_CTL 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* Reserved [31:28] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define FLD_SRC3_FIFO_RD_TH 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /* Reserved [23:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define FLD_SRC3_PHASE_INC 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define SRC4_CTL 0x904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* Reserved [31:28] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define FLD_SRC4_FIFO_RD_TH 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* Reserved [23:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define FLD_SRC4_PHASE_INC 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define SRC5_CTL 0x908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /* Reserved [31:28] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define FLD_SRC5_FIFO_RD_TH 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /* Reserved [23:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define FLD_SRC5_PHASE_INC 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define SRC6_CTL 0x90c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* Reserved [31:28] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define FLD_SRC6_FIFO_RD_TH 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /* Reserved [23:18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define FLD_SRC6_PHASE_INC 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define BAND_OUT_SEL 0x910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define FLD_SRC6_IN_SEL 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define FLD_SRC6_CLK_SEL 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define FLD_SRC5_IN_SEL 0x0c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define FLD_SRC5_CLK_SEL 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define FLD_SRC4_IN_SEL 0x00c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define FLD_SRC4_CLK_SEL 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define FLD_SRC3_IN_SEL 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define FLD_SRC3_CLK_SEL 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define FLD_BASEBAND_BYPASS_CTL 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define FLD_AC97_SRC_SEL 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define FLD_I2S_SRC_SEL 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define FLD_PARALLEL2_SRC_SEL 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define FLD_PARALLEL1_SRC_SEL 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define I2S_IN_CTL 0x914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* Reserved [31:11] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define FLD_I2S_UP2X_BW20K 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define FLD_I2S_UP2X_BYPASS 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define FLD_I2S_IN_MASTER_MODE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define FLD_I2S_IN_SONY_MODE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define FLD_I2S_IN_RIGHT_JUST 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #define FLD_I2S_IN_WS_SEL 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define FLD_I2S_IN_BCN_DEL 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define I2S_OUT_CTL 0x918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /* Reserved [31:17] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define FLD_I2S_OUT_SOFT_RESET_EN 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /* Reserved [15:9] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define FLD_I2S_OUT_MASTER_MODE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define FLD_I2S_OUT_SONY_MODE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define FLD_I2S_OUT_RIGHT_JUST 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define FLD_I2S_OUT_WS_SEL 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define FLD_I2S_OUT_BCN_DEL 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define AC97_CTL 0x91c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* Reserved [31:26] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define FLD_AC97_UP2X_BW20K 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define FLD_AC97_UP2X_BYPASS 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* Reserved [23:17] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define FLD_AC97_RST_ACL 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* Reserved [15:9] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define FLD_AC97_WAKE_UP_SYNC 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* Reserved [7:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define FLD_AC97_SHUTDOWN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define QPSK_IAGC_CTL1 0x94c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define QPSK_IAGC_CTL2 0x950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) #define QPSK_FEPR_FREQ 0x954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #define QPSK_BTL_CTL1 0x958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define QPSK_BTL_CTL2 0x95c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define QPSK_CTL_CTL1 0x960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define QPSK_CTL_CTL2 0x964
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define QPSK_MF_FAGC_CTL 0x968
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define QPSK_EQ_CTL 0x96c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define QPSK_LOCK_CTL 0x970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define FM1_DFT_CTL 0x9a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define FLD_FM1_DFT_THRESHOLD 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* Reserved [15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define FLD_FM1_DFT_CMP_CTL 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) #define FLD_FM1_DFT_AVG 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* Reserved [3:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define FLD_FM1_DFT_START 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define FM1_DFT_STATUS 0x9ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define FLD_FM1_DFT_DONE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* Reserved [30:19] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define FLD_FM_DFT_TH_CMP 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define FLD_FM1_DFT 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define FM2_DFT_CTL 0x9b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define FLD_FM2_DFT_THRESHOLD 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* Reserved [15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define FLD_FM2_DFT_CMP_CTL 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define FLD_FM2_DFT_AVG 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /* Reserved [3:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define FLD_FM2_DFT_START 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define FM2_DFT_STATUS 0x9b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define FLD_FM2_DFT_DONE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* Reserved [30:19] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define FLD_FM2_DFT_TH_CMP_STAT 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define FLD_FM2_DFT 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define AAGC_STATUS_REG 0x9b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define AAGC_STATUS 0x9b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* Reserved [31:27] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define FLD_FM2_DAGC_OUT 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* Reserved [23:19] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define FLD_FM1_DAGC_OUT 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* Reserved [15:6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define FLD_AFE_VGA_OUT 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define MTS_GAIN_STATUS 0x9bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* Reserved [31:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define FLD_MTS_GAIN 0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define RDS_OUT 0x9c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define FLD_RDS_Q 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define FLD_RDS_I 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define AUTOCONFIG_REG 0x9c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* Reserved [31:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define FLD_AUTOCONFIG_MODE 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define FM_AFC 0x9c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define FLD_FM2_AFC 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #define FLD_FM1_AFC 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* Cx231xx redefine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #define NEW_SPARE 0x9cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define NEW_SPARE_REG 0x9cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define DBX_ADJ 0x9d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /* Reserved [31:28] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define FLD_DBX2_ADJ 0x0fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* Reserved [15:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define FLD_DBX1_ADJ 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define VID_FMT_AUTO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define VID_FMT_NTSC_M 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define VID_FMT_NTSC_J 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define VID_FMT_NTSC_443 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define VID_FMT_PAL_BDGHI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define VID_FMT_PAL_M 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define VID_FMT_PAL_N 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define VID_FMT_PAL_NC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define VID_FMT_PAL_60 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define VID_FMT_SECAM 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define VID_FMT_SECAM_60 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #define UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #define TWO_TAP_FILT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define THREE_TAP_FILT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #define FOUR_TAP_FILT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define FIVE_TAP_FILT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) #define AUD_CHAN_SRC_PARALLEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #define AUD_CHAN_SRC_I2S_INPUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) #define AUD_CHAN_SRC_FLATIRON 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #define AUD_CHAN_SRC_PARALLEL3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define OUT_MODE_601 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #define OUT_MODE_656 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) #define OUT_MODE_VIP11 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #define OUT_MODE_VIP20 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #define PHASE_INC_49MHZ 0x0df22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define PHASE_INC_56MHZ 0x0fa5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #define PHASE_INC_28MHZ 0x010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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