^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) cx231xx-pcb-cfg.h - driver for Conexant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Cx23100/101/102 USB video capture devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _PCB_CONFIG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _PCB_CONFIG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Class Information *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLASS_DEFAULT 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum VENDOR_REQUEST_TYPE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Set/Get I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) VRT_SET_I2C0 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) VRT_SET_I2C1 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) VRT_SET_I2C2 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) VRT_GET_I2C0 = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) VRT_GET_I2C1 = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) VRT_GET_I2C2 = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Set/Get GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) VRT_SET_GPIO = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) VRT_GET_GPIO = 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Set/Get GPIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) VRT_SET_GPIE = 0xA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) VRT_GET_GPIE = 0xB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Set/Get Register Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) VRT_SET_REGISTER = 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) VRT_GET_REGISTER = 0xD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Get Extended Compat ID Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) VRT_GET_EXTCID_DESC = 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) enum BYTE_ENABLE_MASK {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ENABLE_ONE_BYTE = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ENABLE_TWE_BYTE = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ENABLE_THREE_BYTE = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ENABLE_FOUR_BYTE = 0xF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPEED_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum USB_SPEED{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FULL_SPEED = 0x0, /* 0: full speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) HIGH_SPEED = 0x1 /* 1: high speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TS_MASK 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum TS_PORT{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) NO_TS_PORT = 0x0, /* 2'b00: Neither port used. PCB not a Hybrid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) only offers Analog TV or Video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) TS1_PORT = 0x4, /* 2'b10: TS1 Input (Hybrid mode :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Digital or External Analog/Compressed source) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) TS1_TS2_PORT = 0x6, /* 2'b11: TS1 & TS2 Inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (Dual inputs from Digital and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) External Analog/Compressed sources) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) TS1_EXT_CLOCK = 0x6, /* 2'b11: TS1 & TS2 as selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) to external clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) TS1VIP_TS2_PORT = 0x2 /* 2'b01: TS1 used as 656/VIP Output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) TS2 Input (from Compressor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EAVP_MASK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) enum EAV_PRESENT{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) NO_EXTERNAL_AV = 0x0, /* 0: No External A/V inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) (no need for i2s block),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) Analog Tuner must be present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) EXTERNAL_AV = 0x8 /* 1: External A/V inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) present (requires i2s blk) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ATM_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum AT_MODE{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DIF_TUNER = 0x30, /* 2'b11: IF Tuner (requires use of DIF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) BASEBAND_SOUND = 0x20, /* 2'b10: Baseband Composite &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) Sound-IF Signals present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) NO_TUNER = 0x10 /* 2'b0x: No Analog Tuner present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PWR_SEL_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum POWE_TYPE{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SELF_POWER = 0x0, /* 0: self power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) BUS_POWER = 0x40 /* 1: bus power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) enum USB_POWE_TYPE{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) USB_SELF_POWER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) USB_BUS_POWER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BO_0_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum AVDEC_STATUS{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) AVDEC_DISABLE = 0x0, /* 0: A/V Decoder Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) AVDEC_ENABLE = 0x80 /* 1: A/V Decoder Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BO_1_MASK 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BUSPOWER_MASK 0xC4 /* for Polaris spec 0.8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SELFPOWER_MASK 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define NOT_DECIDE_YET 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define NOT_SUPPORTED 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * for mod field use *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MOD_DIGITAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MOD_ANALOG 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MOD_DIF 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MOD_EXTERNAL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CAP_ALL_MOD 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * source define *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SOURCE_DIGITAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SOURCE_ANALOG 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SOURCE_DIF 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SOURCE_EXTERNAL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SOURCE_TS_BDA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SOURCE_TS_ENCODE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SOURCE_TS_EXTERNAL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * interface information define *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct INTERFACE_INFO {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 interrupt_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 ts1_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 ts2_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 audio_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u8 video_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 vanc_index; /* VBI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 hanc_index; /* Sliced CC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 ir_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) enum INDEX_INTERFACE_INFO{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) INDEX_INTERRUPT = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) INDEX_TS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) INDEX_TS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) INDEX_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) INDEX_VIDEO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) INDEX_VANC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) INDEX_HANC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) INDEX_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * configuration information define *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct CONFIG_INFO {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 config_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct INTERFACE_INFO interface_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct pcb_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 type; /* bus power or self power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) self power--0, bus_power--1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 speed; /* usb speed, 2.0--1, 1.1--0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 mode; /* digital , anlog, dif or external A/V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 ts1_source; /* three source -- BDA,External,encode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 ts2_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 analog_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 digital_index; /* bus-power used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 analog_index; /* bus-power used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 dif_index; /* bus-power used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u8 external_index; /* bus-power used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u8 config_num; /* current config num, 0,1,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) for self-power, always 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct CONFIG_INFO hs_config_info[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct CONFIG_INFO fs_config_info[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum INDEX_PCB_CONFIG{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) INDEX_SELFPOWER_DIGITAL_ONLY = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) INDEX_SELFPOWER_DUAL_DIGITAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) INDEX_SELFPOWER_ANALOG_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) INDEX_SELFPOWER_DUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) INDEX_SELFPOWER_TRIPLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) INDEX_SELFPOWER_COMPRESSOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) INDEX_BUSPOWER_DIGITAL_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) INDEX_BUSPOWER_ANALOG_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) INDEX_BUSPOWER_DIF_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) INDEX_BUSPOWER_EXTERNAL_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) INDEX_BUSPOWER_EXTERNAL_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) INDEX_BUSPOWER_EXTERNAL_DIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) INDEX_BUSPOWER_EXTERNAL_DIGITAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) INDEX_BUSPOWER_DIGITAL_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) INDEX_BUSPOWER_DIGITAL_DIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) INDEX_BUSPOWER_DIGITAL_ANALOG_EXTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) INDEX_BUSPOWER_DIGITAL_DIF_EXTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct cx231xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int initialize_cx231xx(struct cx231xx *p_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags