^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) video capture devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _POLARIS_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _POLARIS_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BOARD_CFG_STAT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TS_MODE_REG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TS1_CFG_REG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TS1_LENGTH_REG 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TS2_CFG_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TS2_LENGTH_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EP_MODE_SET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CIR_PWR_PTN1 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CIR_PWR_PTN2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CIR_PWR_PTN3 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CIR_PWR_MASK0 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CIR_PWR_MASK1 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CIR_PWR_MASK2 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CIR_GAIN 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CIR_CAR_REG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CIR_OT_CFG1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CIR_OT_CFG2 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GBULK_BIT_EN 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PWR_CTL_EN 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Polaris Endpoints capture mask for register EP_MODE_SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ENABLE_EP1 0x01 /* Bit[0]=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ENABLE_EP2 0x02 /* Bit[1]=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ENABLE_EP3 0x04 /* Bit[2]=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ENABLE_EP4 0x08 /* Bit[3]=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ENABLE_EP5 0x10 /* Bit[4]=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ENABLE_EP6 0x20 /* Bit[5]=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Bit definition for register PWR_CTL_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PWR_MODE_MASK 0x17f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PWR_AV_EN 0x08 /* bit3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PWR_ISO_EN 0x40 /* bit6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PWR_AV_MODE 0x30 /* bit4,5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PWR_TUNER_EN 0x04 /* bit2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PWR_DEMOD_EN 0x02 /* bit1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2C_DEMOD_EN 0x01 /* bit0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PWR_RESETOUT_EN 0x100 /* bit8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum AV_MODE{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) POLARIS_AVMODE_DEFAULT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) POLARIS_AVMODE_DIGITAL = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) POLARIS_AVMODE_ANALOGT_TV = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) POLARIS_AVMODE_ENXTERNAL_AV = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Colibri Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SINGLE_ENDED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LOW_IF 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EU_IF 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define US_IF 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SUP_BLK_TUNE1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SUP_BLK_TUNE2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SUP_BLK_TUNE3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SUP_BLK_XTAL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SUP_BLK_PLL1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SUP_BLK_PLL2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SUP_BLK_PLL3 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SUP_BLK_REF 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SUP_BLK_PWRDN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SUP_BLK_TESTPAD 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ADC_COM_INT5_STAB_REF 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ADC_COM_QUANT 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ADC_COM_BIAS1 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADC_COM_BIAS2 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ADC_COM_BIAS3 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TESTBUS_CTRL 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FLD_PWRDN_TUNING_BIAS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define FLD_PWRDN_ENABLE_PLL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define FLD_PWRDN_PD_BANDGAP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define FLD_PWRDN_PD_BIAS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define FLD_PWRDN_PD_TUNECK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ADC_STATUS_CH1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ADC_STATUS_CH2 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ADC_STATUS_CH3 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ADC_STATUS2_CH1 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ADC_STATUS2_CH2 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ADC_STATUS2_CH3 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ADC_CAL_ATEST_CH1 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ADC_CAL_ATEST_CH2 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ADC_CAL_ATEST_CH3 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ADC_PWRDN_CLAMP_CH1 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ADC_PWRDN_CLAMP_CH2 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ADC_PWRDN_CLAMP_CH3 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ADC_CTRL_DAC23_CH1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ADC_CTRL_DAC23_CH2 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ADC_CTRL_DAC23_CH3 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ADC_CTRL_DAC1_CH1 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ADC_CTRL_DAC1_CH2 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ADC_CTRL_DAC1_CH3 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ADC_DCSERVO_DEM_CH1 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ADC_DCSERVO_DEM_CH2 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ADC_DCSERVO_DEM_CH3 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ADC_FB_FRCRST_CH1 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ADC_FB_FRCRST_CH2 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ADC_FB_FRCRST_CH3 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ADC_INPUT_CH1 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ADC_INPUT_CH2 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ADC_INPUT_CH3 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ADC_NTF_PRECLMP_EN_CH1 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ADC_NTF_PRECLMP_EN_CH2 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ADC_NTF_PRECLMP_EN_CH3 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ADC_QGAIN_RES_TRM_CH1 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ADC_QGAIN_RES_TRM_CH2 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ADC_QGAIN_RES_TRM_CH3 0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ADC_SOC_PRECLMP_TERM_CH1 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ADC_SOC_PRECLMP_TERM_CH2 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ADC_SOC_PRECLMP_TERM_CH3 0x6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TESTBUS_CTRL_CH1 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TESTBUS_CTRL_CH2 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TESTBUS_CTRL_CH3 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * DIF registers *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DIRECT_IF_REVB_BASE 0x00300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define FLD_DIF_PLL_LOCK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Reserved [30:29] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FLD_DIF_PLL_FREE_RUN 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define FLD_DIF_PLL_FREQ 0x0fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define FLD_DIF_KD_PD 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Reserved [23:20] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define FLD_DIF_KDS_PD 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FLD_DIF_KI_PD 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Reserved [7:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FLD_DIF_KIS_PD 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define FLD_DIF_KD_FD 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Reserved [23:20] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define FLD_DIF_KDS_FD 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define FLD_DIF_KI_FD 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FLD_DIF_SIG_PROP_SZ 0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FLD_DIF_KIS_FD 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define FLD_DIF_PLL_AGC_REF 0xfff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define FLD_DIF_PLL_AGC_KI 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Reserved [15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define FLD_DIF_FREQ_LIMIT 0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FLD_DIF_K_FD 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FLD_DIF_DOWNSMPL_FD 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Reserved [31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define FLD_DIF_PLL_AGC_EN 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Reserved [14:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define FLD_DIF_PLL_MAN_GAIN 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define FLD_DIF_K_AGC_RF 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define FLD_DIF_K_AGC_IF 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define FLD_DIF_K_AGC_INT 0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Reserved [19:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define FLD_DIF_IF_REF 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define FLD_DIF_IF_MAX 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define FLD_DIF_IF_MIN 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define FLD_DIF_IF_AGC 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define FLD_DIF_INT_MAX 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define FLD_DIF_INT_MIN 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define FLD_DIF_INT_AGC 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define FLD_DIF_RF_MAX 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define FLD_DIF_RF_MIN 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define FLD_DIF_RF_AGC 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define FLD_DIF_IF_AGC_IN 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define FLD_DIF_INT_AGC_IN 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Reserved [31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define FLD_DIF_RF_AGC_IN 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define FLD_DIF_AFD 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define FLD_DIF_K_VID_AGC 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define FLD_DIF_LINE_LENGTH 0x0fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define FLD_DIF_AGC_GAIN 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Reserved [30:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define FLD_DIF_AUDIO_MAN_GAIN 0x3f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Reserved [23:17] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define FLD_DIF_VID_AGC_OVERRIDE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define FLD_DIF_VID_MAN_GAIN 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define FLD_DIF_LPF_FREQ 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define FLD_DIF_AV_PHASE_INC 0x3f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define FLD_DIF_AUDIO_FREQ 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Reserved [31:24] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define FLD_DIF_IIR23_R2 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define FLD_DIF_IIR23_R1 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define FLD_DIF_IIR1_R1 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define FLD_DIF_DIF_BYPASS 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define FLD_DIF_FM_NYQ_GAIN 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define FLD_DIF_RF_AGC_ENA 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define FLD_DIF_INT_AGC_ENA 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define FLD_DIF_IF_AGC_ENA 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define FLD_DIF_FORCE_RF_IF_LOCK 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define FLD_DIF_VIDEO_AGC_ENA 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define FLD_DIF_RF_AGC_INV 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define FLD_DIF_INT_AGC_INV 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define FLD_DIF_IF_AGC_INV 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define FLD_DIF_SPEC_INV 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define FLD_DIF_AUD_FULL_BW 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define FLD_DIF_AUD_SRC_SEL 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Reserved [18] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define FLD_DIF_IF_FREQ 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Reserved [15:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define FLD_DIF_TIP_OFFSET 0x00003f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Reserved [7:5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define FLD_DIF_DITHER_ENA 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Reserved [3:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define FLD_DIF_RF_IF_LOCK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Reserved [31:29] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define FLD_DIF_PHASE_INC 0x1fffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Reserved [31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define FLD_DIF_SRC_KI 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define FLD_DIF_SRC_KD 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Reserved [31:19] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define FLD_DIF_BPF_COEFF_0 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Reserved [15:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define FLD_DIF_BPF_COEFF_1 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Reserved [31:22] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define FLD_DIF_BPF_COEFF_2 0x003f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Reserved [15:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define FLD_DIF_BPF_COEFF_3 0x0000007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Reserved [31:24] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define FLD_DIF_BPF_COEFF_4 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Reserved [15:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define FLD_DIF_BPF_COEFF_5 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Reserved [31:25] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define FLD_DIF_BPF_COEFF_6 0x01ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Reserved [15:9] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define FLD_DIF_BPF_COEFF_7 0x000001ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Reserved [31:26] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define FLD_DIF_BPF_COEFF_8 0x03ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Reserved [15:10] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define FLD_DIF_BPF_COEFF_9 0x000003ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Reserved [31:27] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define FLD_DIF_BPF_COEFF_10 0x07ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Reserved [15:11] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define FLD_DIF_BPF_COEFF_11 0x000007ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Reserved [31:27] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define FLD_DIF_BPF_COEFF_12 0x07ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Reserved [15:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define FLD_DIF_BPF_COEFF_13 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Reserved [31:28] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define FLD_DIF_BPF_COEFF_14 0x0fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Reserved [15:12] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define FLD_DIF_BPF_COEFF_15 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Reserved [31:29] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define FLD_DIF_BPF_COEFF_16 0x1fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Reserved [15:13] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define FLD_DIF_BPF_COEFF_17 0x00001fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Reserved [31:29] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define FLD_DIF_BPF_COEFF_18 0x1fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Reserved [15:13] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define FLD_DIF_BPF_COEFF_19 0x00001fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Reserved [31:29] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define FLD_DIF_BPF_COEFF_20 0x1fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Reserved [15:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define FLD_DIF_BPF_COEFF_21 0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Reserved [31:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define FLD_DIF_BPF_COEFF_22 0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Reserved [15:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define FLD_DIF_BPF_COEFF_23 0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Reserved [31:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define FLD_DIF_BPF_COEFF_24 0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Reserved [15:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define FLD_DIF_BPF_COEFF_25 0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Reserved [31:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define FLD_DIF_BPF_COEFF_26 0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Reserved [15:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define FLD_DIF_BPF_COEFF_27 0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Reserved [31:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define FLD_DIF_BPF_COEFF_28 0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Reserved [15:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define FLD_DIF_BPF_COEFF_29 0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Reserved [31:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define FLD_DIF_BPF_COEFF_30 0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Reserved [15:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define FLD_DIF_BPF_COEFF_31 0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Reserved [31:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define FLD_DIF_BPF_COEFF_32 0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Reserved [15:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define FLD_DIF_BPF_COEFF_33 0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Reserved [31:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define FLD_DIF_BPF_COEFF_34 0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Reserved [15:14] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define FLD_DIF_BPF_COEFF_35 0x00003fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Reserved [31:30] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define FLD_DIF_BPF_COEFF_36 0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Reserved [15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Reserved [31:20] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define FLD_DIF_RPT_VARIANCE 0x000fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Reserved [31:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define FLD_DIF_DIF_SOFT_RST 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define FLD_DIF_DIF_REG_RST_MSK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define FLD_DIF_AGC_RST_MSK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define FLD_DIF_CMP_RST_MSK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define FLD_DIF_AVS_RST_MSK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define FLD_DIF_NYQ_RST_MSK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define FLD_DIF_DIF_SRC_RST_MSK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define FLD_DIF_PLL_RST_MSK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Reserved [31:25] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define FLD_DIF_CTL_IP 0x01ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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