Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  Driver for the Auvitek USB bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (c) 2008 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) /* We'll start to rename these registers once we have a better
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * understanding of their meaning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define REG_000 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define REG_001 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define REG_002 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define REG_003 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AU0828_SENSORCTRL_100 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AU0828_SENSORCTRL_VBI_103 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* I2C registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AU0828_I2C_TRIGGER_200		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AU0828_I2C_STATUS_201		0x201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AU0828_I2C_CLK_DIVIDER_202	0x202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AU0828_I2C_DEST_ADDR_203	0x203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AU0828_I2C_WRITE_FIFO_205	0x205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AU0828_I2C_READ_FIFO_209	0x209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AU0828_I2C_MULTIBYTE_MODE_2FF	0x2ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Audio registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AU0828_AUDIOCTRL_50C 0x50C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_600 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Here are constants for values associated with the above registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* I2C Trigger (Reg 0x200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AU0828_I2C_TRIGGER_WRITE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AU0828_I2C_TRIGGER_READ		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AU0828_I2C_TRIGGER_HOLD		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* I2C Status (Reg 0x201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AU0828_I2C_STATUS_READ_DONE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AU0828_I2C_STATUS_NO_READ_ACK	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AU0828_I2C_STATUS_WRITE_DONE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AU0828_I2C_STATUS_NO_WRITE_ACK	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AU0828_I2C_STATUS_BUSY		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* I2C Clock Divider (Reg 0x202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AU0828_I2C_CLK_250KHZ 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AU0828_I2C_CLK_100KHZ 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AU0828_I2C_CLK_30KHZ  0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AU0828_I2C_CLK_20KHZ  0x60