Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Driver for the Auvitek AU0828 USB bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (c) 2008 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include "au0828.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "media/tuner.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static int i2c_scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) module_param(i2c_scan, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define I2C_WAIT_DELAY 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define I2C_WAIT_RETRY 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static inline int i2c_slave_did_write_ack(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct au0828_dev *dev = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	return au0828_read(dev, AU0828_I2C_STATUS_201) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		AU0828_I2C_STATUS_NO_WRITE_ACK ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static inline int i2c_slave_did_read_ack(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct au0828_dev *dev = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	return au0828_read(dev, AU0828_I2C_STATUS_201) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		AU0828_I2C_STATUS_NO_READ_ACK ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static int i2c_wait_read_ack(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	for (count = 0; count < I2C_WAIT_RETRY; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		if (!i2c_slave_did_read_ack(i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		udelay(I2C_WAIT_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (I2C_WAIT_RETRY == count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static inline int i2c_is_read_busy(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct au0828_dev *dev = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	return au0828_read(dev, AU0828_I2C_STATUS_201) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		AU0828_I2C_STATUS_READ_DONE ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static int i2c_wait_read_done(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	for (count = 0; count < I2C_WAIT_RETRY; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		if (!i2c_is_read_busy(i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		udelay(I2C_WAIT_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (I2C_WAIT_RETRY == count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static inline int i2c_is_write_done(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct au0828_dev *dev = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return au0828_read(dev, AU0828_I2C_STATUS_201) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		AU0828_I2C_STATUS_WRITE_DONE ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int i2c_wait_write_done(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	for (count = 0; count < I2C_WAIT_RETRY; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		if (i2c_is_write_done(i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		udelay(I2C_WAIT_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (I2C_WAIT_RETRY == count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline int i2c_is_busy(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct au0828_dev *dev = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return au0828_read(dev, AU0828_I2C_STATUS_201) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		AU0828_I2C_STATUS_BUSY ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int i2c_wait_done(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	for (count = 0; count < I2C_WAIT_RETRY; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		if (!i2c_is_busy(i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		udelay(I2C_WAIT_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (I2C_WAIT_RETRY == count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* FIXME: Implement join handling correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int i2c_sendbytes(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	const struct i2c_msg *msg, int joined_rlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int i, strobe = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct au0828_dev *dev = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u8 i2c_speed = dev->board.i2c_clk_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	dprintk(4, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	au0828_write(dev, AU0828_I2C_MULTIBYTE_MODE_2FF, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (((dev->board.tuner_type == TUNER_XC5000) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	     (dev->board.tuner_type == TUNER_XC5000C)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	    (dev->board.tuner_addr == msg->addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		 * Due to I2C clock stretch, we need to use a lower speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		 * on xc5000 for commands. However, firmware transfer can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		 * speed up to 400 KHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		if (msg->len == 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			i2c_speed = AU0828_I2C_CLK_250KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			i2c_speed = AU0828_I2C_CLK_20KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/* Set the I2C clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	au0828_write(dev, AU0828_I2C_CLK_DIVIDER_202, i2c_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* Hardware needs 8 bit addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	au0828_write(dev, AU0828_I2C_DEST_ADDR_203, msg->addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	dprintk(4, "SEND: %02x\n", msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* Deal with i2c_scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (msg->len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		/* The analog tuner detection code makes use of the SMBUS_QUICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		   message (which involves a zero length i2c write).  To avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		   checking the status register when we didn't strobe out any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		   actual bytes to the bus, just do a read check.  This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		   consistent with how I saw i2c device checking done in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		   USB trace of the Windows driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		au0828_write(dev, AU0828_I2C_TRIGGER_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			     AU0828_I2C_TRIGGER_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		if (!i2c_wait_done(i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		if (i2c_wait_read_ack(i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	for (i = 0; i < msg->len;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		dprintk(4, " %02x\n", msg->buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		au0828_write(dev, AU0828_I2C_WRITE_FIFO_205, msg->buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		strobe++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		if ((strobe >= 4) || (i >= msg->len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			/* Strobe the byte into the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			if (i < msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				au0828_write(dev, AU0828_I2C_TRIGGER_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 					     AU0828_I2C_TRIGGER_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 					     AU0828_I2C_TRIGGER_HOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				au0828_write(dev, AU0828_I2C_TRIGGER_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 					     AU0828_I2C_TRIGGER_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			/* Reset strobe trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			strobe = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			if (!i2c_wait_write_done(i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (!i2c_wait_done(i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	dprintk(4, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* FIXME: Implement join handling correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int i2c_readbytes(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	const struct i2c_msg *msg, int joined)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct au0828_dev *dev = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	u8 i2c_speed = dev->board.i2c_clk_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	dprintk(4, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	au0828_write(dev, AU0828_I2C_MULTIBYTE_MODE_2FF, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 * Due to xc5000c clock stretch, we cannot use full speed at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * readings from xc5000, as otherwise they'll fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (((dev->board.tuner_type == TUNER_XC5000) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	     (dev->board.tuner_type == TUNER_XC5000C)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	    (dev->board.tuner_addr == msg->addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		i2c_speed = AU0828_I2C_CLK_20KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* Set the I2C clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	au0828_write(dev, AU0828_I2C_CLK_DIVIDER_202, i2c_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* Hardware needs 8 bit addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	au0828_write(dev, AU0828_I2C_DEST_ADDR_203, msg->addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	dprintk(4, " RECV:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* Deal with i2c_scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (msg->len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		au0828_write(dev, AU0828_I2C_TRIGGER_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			     AU0828_I2C_TRIGGER_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		if (i2c_wait_read_ack(i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	for (i = 0; i < msg->len;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		if (i < msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			au0828_write(dev, AU0828_I2C_TRIGGER_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				     AU0828_I2C_TRIGGER_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				     AU0828_I2C_TRIGGER_HOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			au0828_write(dev, AU0828_I2C_TRIGGER_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				     AU0828_I2C_TRIGGER_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		if (!i2c_wait_read_done(i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		msg->buf[i-1] = au0828_read(dev, AU0828_I2C_READ_FIFO_209) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		dprintk(4, " %02x\n", msg->buf[i-1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (!i2c_wait_done(i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	dprintk(4, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int i2c_xfer(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		    struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	int i, retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	dprintk(4, "%s(num = %d)\n", __func__, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		dprintk(4, "%s(num = %d) addr = 0x%02x  len = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			__func__, num, msgs[i].addr, msgs[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		if (msgs[i].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			/* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			retval = i2c_readbytes(i2c_adap, &msgs[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		} else if (i + 1 < num && (msgs[i + 1].flags & I2C_M_RD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			   msgs[i].addr == msgs[i + 1].addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			/* write then read from same address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			retval = i2c_sendbytes(i2c_adap, &msgs[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 					       msgs[i + 1].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 				goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			retval = i2c_readbytes(i2c_adap, &msgs[i], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			/* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			retval = i2c_sendbytes(i2c_adap, &msgs[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static u32 au0828_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct i2c_algorithm au0828_i2c_algo_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.master_xfer	= i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.functionality	= au0828_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct i2c_adapter au0828_i2c_adap_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.name              = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.owner             = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.algo              = &au0828_i2c_algo_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct i2c_client au0828_i2c_client_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.name	= "au0828 internal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static char *i2c_devs[128] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	[0x8e >> 1] = "au8522",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	[0xa0 >> 1] = "eeprom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	[0xc2 >> 1] = "tuner/xc5000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static void do_i2c_scan(char *name, struct i2c_client *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	unsigned char buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	for (i = 0; i < 128; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		c->addr = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		rc = i2c_master_recv(c, &buf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		pr_info("%s: i2c scan: found device @ 0x%x  [%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		       name, i << 1, i2c_devs[i] ? i2c_devs[i] : "???");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* init + register i2c adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int au0828_i2c_register(struct au0828_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	dev->i2c_adap = au0828_i2c_adap_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	dev->i2c_algo = au0828_i2c_algo_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	dev->i2c_client = au0828_i2c_client_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	dev->i2c_adap.dev.parent = &dev->usbdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	strscpy(dev->i2c_adap.name, KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		sizeof(dev->i2c_adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	dev->i2c_adap.algo = &dev->i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	dev->i2c_adap.algo_data = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #ifdef CONFIG_VIDEO_AU0828_V4L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	i2c_set_adapdata(&dev->i2c_adap, &dev->v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	i2c_set_adapdata(&dev->i2c_adap, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	i2c_add_adapter(&dev->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	dev->i2c_client.adapter = &dev->i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	if (0 == dev->i2c_rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		pr_info("i2c bus registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		if (i2c_scan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			do_i2c_scan(KBUILD_MODNAME, &dev->i2c_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		pr_info("i2c bus register FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	return dev->i2c_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int au0828_i2c_unregister(struct au0828_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	i2c_del_adapter(&dev->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)