^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Xceive XC5000 "QAM/8VSB single chip tuner"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007 Xceive Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2007 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2009 Devin Heitmueller <dheitmueller@kernellabs.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "xc5000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "tuner-i2c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int no_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) module_param(no_poweroff, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_PARM_DESC(no_poweroff, "0 (default) powers device off when not used.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "\t\t1 keep device energized and with tuner ready all the times.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "\t\tFaster, but consumes more power and keeps the device hotter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static DEFINE_MUTEX(xc5000_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static LIST_HEAD(hybrid_tuner_instance_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define dprintk(level, fmt, arg...) if (debug >= level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) printk(KERN_INFO "%s: " fmt, "xc5000", ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct xc5000_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct tuner_i2c_props i2c_props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct list_head hybrid_tuner_instance_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 if_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u16 xtal_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 freq_hz, freq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 video_standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 rf_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 radio_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u16 output_amp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u16 pll_register_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 init_status_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 fw_checksum_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct delayed_work timer_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const struct firmware *firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Misc Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MAX_TV_STANDARD 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define XC_MAX_I2C_WRITE_LENGTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Time to suspend after the .sleep callback is called */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define XC5000_SLEEP_TIME 5000 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Signal Types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define XC_RF_MODE_AIR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define XC_RF_MODE_CABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Product id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define XC_PRODUCT_ID_FW_NOT_LOADED 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define XC_PRODUCT_ID_FW_LOADED 0x1388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define XREG_INIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define XREG_VIDEO_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define XREG_AUDIO_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define XREG_RF_FREQ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define XREG_D_CODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define XREG_IF_OUT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define XREG_SEEK_MODE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define XREG_POWER_DOWN 0x0A /* Obsolete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Set the output amplitude - SIF for analog, DTVP/DTVN for digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define XREG_OUTPUT_AMP 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define XREG_SIGNALSOURCE 0x0D /* 0=Air, 1=Cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define XREG_SMOOTHEDCVBS 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define XREG_XTALFREQ 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define XREG_FINERFREQ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define XREG_DDIMODE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define XREG_ADC_ENV 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define XREG_QUALITY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define XREG_FRAME_LINES 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define XREG_HSYNC_FREQ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define XREG_LOCK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define XREG_FREQ_ERROR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define XREG_SNR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define XREG_VERSION 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define XREG_PRODUCT_ID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define XREG_BUSY 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define XREG_BUILD 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define XREG_TOTALGAIN 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define XREG_FW_CHECKSUM 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define XREG_INIT_STATUS 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) Basic firmware description. This will remain with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) the driver for documentation purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) This represents an I2C firmware file encoded as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) string of unsigned char. Format is as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) char[0 ]=len0_MSB -> len = len_MSB * 256 + len_LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) char[1 ]=len0_LSB -> length of first write transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) char[2 ]=data0 -> first byte to be sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) char[3 ]=data1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) char[4 ]=data2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) char[ ]=...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) char[M ]=dataN -> last byte to be sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) char[M+1]=len1_MSB -> len = len_MSB * 256 + len_LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) char[M+2]=len1_LSB -> length of second write transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) char[M+3]=data0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) char[M+4]=data1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) The [len] value should be interpreted as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) len= len_MSB _ len_LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) len=1111_1111_1111_1111 : End of I2C_SEQUENCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) len=0000_0000_0000_0000 : Reset command: Do hardware reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) len=0NNN_NNNN_NNNN_NNNN : Normal transaction: number of bytes = {1:32767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) len=1WWW_WWWW_WWWW_WWWW : Wait command: wait for {1:32767} ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) For the RESET and WAIT commands, the two following bytes will contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) immediately the length of the following transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct XC_TV_STANDARD {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u16 audio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u16 video_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Tuner standards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MN_NTSC_PAL_BTSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MN_NTSC_PAL_A2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MN_NTSC_PAL_EIAJ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MN_NTSC_PAL_MONO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define BG_PAL_A2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define BG_PAL_NICAM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define BG_PAL_MONO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define I_PAL_NICAM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define I_PAL_NICAM_MONO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DK_PAL_A2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DK_PAL_NICAM 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DK_PAL_MONO 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DK_SECAM_A2DK1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DK_SECAM_A2LDK3 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DK_SECAM_A2MONO 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define L_SECAM_NICAM 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LC_SECAM_NICAM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DTV6 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DTV8 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DTV7_8 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DTV7 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define FM_RADIO_INPUT2 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FM_RADIO_INPUT1 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FM_RADIO_INPUT1_MONO 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct XC_TV_STANDARD xc5000_standard[MAX_TV_STANDARD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {"M/N-NTSC/PAL-BTSC", 0x0400, 0x8020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {"M/N-NTSC/PAL-A2", 0x0600, 0x8020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {"M/N-NTSC/PAL-EIAJ", 0x0440, 0x8020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {"M/N-NTSC/PAL-Mono", 0x0478, 0x8020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {"B/G-PAL-A2", 0x0A00, 0x8049},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {"B/G-PAL-NICAM", 0x0C04, 0x8049},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {"B/G-PAL-MONO", 0x0878, 0x8059},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {"I-PAL-NICAM", 0x1080, 0x8009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {"I-PAL-NICAM-MONO", 0x0E78, 0x8009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {"D/K-PAL-A2", 0x1600, 0x8009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {"D/K-PAL-NICAM", 0x0E80, 0x8009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {"D/K-PAL-MONO", 0x1478, 0x8009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {"D/K-SECAM-A2 DK1", 0x1200, 0x8009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {"D/K-SECAM-A2 L/DK3", 0x0E00, 0x8009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {"D/K-SECAM-A2 MONO", 0x1478, 0x8009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {"L-SECAM-NICAM", 0x8E82, 0x0009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {"L'-SECAM-NICAM", 0x8E82, 0x4009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {"DTV6", 0x00C0, 0x8002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {"DTV8", 0x00C0, 0x800B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {"DTV7/8", 0x00C0, 0x801B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {"DTV7", 0x00C0, 0x8007},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {"FM Radio-INPUT2", 0x9802, 0x9002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {"FM Radio-INPUT1", 0x0208, 0x9002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {"FM Radio-INPUT1_MONO", 0x0278, 0x9002}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct xc5000_fw_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u16 pll_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 init_status_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 fw_checksum_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define XC5000A_FIRMWARE "dvb-fe-xc5000-1.6.114.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct xc5000_fw_cfg xc5000a_1_6_114 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .name = XC5000A_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .size = 12401,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .pll_reg = 0x806c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define XC5000C_FIRMWARE "dvb-fe-xc5000c-4.1.30.7.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct xc5000_fw_cfg xc5000c_41_024_5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .name = XC5000C_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .size = 16497,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .pll_reg = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .init_status_supported = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .fw_checksum_supported = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static inline const struct xc5000_fw_cfg *xc5000_assign_firmware(int chip_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) switch (chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case XC5000A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return &xc5000a_1_6_114;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case XC5000C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return &xc5000c_41_024_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int xc_load_fw_and_init_tuner(struct dvb_frontend *fe, int force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int xc5000_is_firmware_loaded(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int xc5000_readreg(struct xc5000_priv *priv, u16 reg, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int xc5000_tuner_reset(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int xc_send_i2c_data(struct xc5000_priv *priv, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct i2c_msg msg = { .addr = priv->i2c_props.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .flags = 0, .buf = buf, .len = len };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (i2c_transfer(priv->i2c_props.adap, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) printk(KERN_ERR "xc5000: I2C write failed (len=%i)\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* This routine is never used because the only time we read data from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) i2c bus is when we read registers, and we want that to be an atomic i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) transaction in case we are on a multi-master bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int xc_read_i2c_data(struct xc5000_priv *priv, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct i2c_msg msg = { .addr = priv->i2c_props.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .flags = I2C_M_RD, .buf = buf, .len = len };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (i2c_transfer(priv->i2c_props.adap, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) printk(KERN_ERR "xc5000 I2C read failed (len=%i)\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int xc5000_readreg(struct xc5000_priv *priv, u16 reg, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 buf[2] = { reg >> 8, reg & 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 bval[2] = { 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { .addr = priv->i2c_props.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .flags = 0, .buf = &buf[0], .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { .addr = priv->i2c_props.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .flags = I2C_M_RD, .buf = &bval[0], .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (i2c_transfer(priv->i2c_props.adap, msg, 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) printk(KERN_WARNING "xc5000: I2C read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *val = (bval[0] << 8) | bval[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int xc5000_tuner_reset(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (fe->callback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = fe->callback(((fe->dvb) && (fe->dvb->priv)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) fe->dvb->priv :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) priv->i2c_props.adap->algo_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) DVB_FRONTEND_COMPONENT_TUNER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) XC5000_TUNER_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) printk(KERN_ERR "xc5000: reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) printk(KERN_ERR "xc5000: no tuner reset callback function, fatal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int xc_write_reg(struct xc5000_priv *priv, u16 reg_addr, u16 i2c_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int watch_dog_timer = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) buf[0] = (reg_addr >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) buf[1] = reg_addr & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) buf[2] = (i2c_data >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) buf[3] = i2c_data & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) result = xc_send_i2c_data(priv, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (result == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* wait for busy flag to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) while ((watch_dog_timer > 0) && (result == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) result = xc5000_readreg(priv, XREG_BUSY, (u16 *)buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (result == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if ((buf[0] == 0) && (buf[1] == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* busy flag cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) msleep(5); /* wait 5 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) watch_dog_timer--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (watch_dog_timer <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) result = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int xc_load_i2c_sequence(struct dvb_frontend *fe, const u8 *i2c_sequence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int i, nbytes_to_send, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int len, pos, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 buf[XC_MAX_I2C_WRITE_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) while ((i2c_sequence[index] != 0xFF) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) (i2c_sequence[index + 1] != 0xFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) len = i2c_sequence[index] * 256 + i2c_sequence[index+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (len == 0x0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* RESET command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) result = xc5000_tuner_reset(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) } else if (len & 0x8000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* WAIT command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) msleep(len & 0x7FFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Send i2c data whilst ensuring individual transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * do not exceed XC_MAX_I2C_WRITE_LENGTH bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) buf[0] = i2c_sequence[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) buf[1] = i2c_sequence[index + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pos = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) while (pos < len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if ((len - pos) > XC_MAX_I2C_WRITE_LENGTH - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) nbytes_to_send =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) XC_MAX_I2C_WRITE_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) nbytes_to_send = (len - pos + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) for (i = 2; i < nbytes_to_send; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) buf[i] = i2c_sequence[index + pos +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) i - 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) result = xc_send_i2c_data(priv, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) nbytes_to_send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pos += nbytes_to_send - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) index += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int xc_initialize(struct xc5000_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return xc_write_reg(priv, XREG_INIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int xc_set_tv_standard(struct xc5000_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u16 video_mode, u16 audio_mode, u8 radio_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dprintk(1, "%s(0x%04x,0x%04x)\n", __func__, video_mode, audio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (radio_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dprintk(1, "%s() Standard = %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) xc5000_standard[radio_mode].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dprintk(1, "%s() Standard = %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) xc5000_standard[priv->video_standard].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = xc_write_reg(priv, XREG_VIDEO_MODE, video_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = xc_write_reg(priv, XREG_AUDIO_MODE, audio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int xc_set_signal_source(struct xc5000_priv *priv, u16 rf_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dprintk(1, "%s(%d) Source = %s\n", __func__, rf_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) rf_mode == XC_RF_MODE_AIR ? "ANTENNA" : "CABLE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if ((rf_mode != XC_RF_MODE_AIR) && (rf_mode != XC_RF_MODE_CABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) rf_mode = XC_RF_MODE_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "%s(), Invalid mode, defaulting to CABLE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return xc_write_reg(priv, XREG_SIGNALSOURCE, rf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct dvb_tuner_ops xc5000_tuner_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int xc_set_rf_frequency(struct xc5000_priv *priv, u32 freq_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u16 freq_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dprintk(1, "%s(%u)\n", __func__, freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if ((freq_hz > xc5000_tuner_ops.info.frequency_max_hz) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) (freq_hz < xc5000_tuner_ops.info.frequency_min_hz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) freq_code = (u16)(freq_hz / 15625);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Starting in firmware version 1.1.44, Xceive recommends using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) FINERFREQ for all normal tuning (the doc indicates reg 0x03 should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) only be used for fast scanning for channel lock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return xc_write_reg(priv, XREG_FINERFREQ, freq_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int xc_set_IF_frequency(struct xc5000_priv *priv, u32 freq_khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 freq_code = (freq_khz * 1024)/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dprintk(1, "%s(freq_khz = %d) freq_code = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) __func__, freq_khz, freq_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return xc_write_reg(priv, XREG_IF_OUT, freq_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int xc_get_adc_envelope(struct xc5000_priv *priv, u16 *adc_envelope)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return xc5000_readreg(priv, XREG_ADC_ENV, adc_envelope);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int xc_get_frequency_error(struct xc5000_priv *priv, u32 *freq_error_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u16 reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) result = xc5000_readreg(priv, XREG_FREQ_ERROR, ®_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) tmp = (u32)reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) (*freq_error_hz) = (tmp * 15625) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int xc_get_lock_status(struct xc5000_priv *priv, u16 *lock_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return xc5000_readreg(priv, XREG_LOCK, lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int xc_get_version(struct xc5000_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 *hw_majorversion, u8 *hw_minorversion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 *fw_majorversion, u8 *fw_minorversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) result = xc5000_readreg(priv, XREG_VERSION, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) (*hw_majorversion) = (data >> 12) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) (*hw_minorversion) = (data >> 8) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) (*fw_majorversion) = (data >> 4) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) (*fw_minorversion) = data & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int xc_get_buildversion(struct xc5000_priv *priv, u16 *buildrev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return xc5000_readreg(priv, XREG_BUILD, buildrev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int xc_get_hsync_freq(struct xc5000_priv *priv, u32 *hsync_freq_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u16 reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) result = xc5000_readreg(priv, XREG_HSYNC_FREQ, ®_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) (*hsync_freq_hz) = ((reg_data & 0x0fff) * 763)/100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int xc_get_frame_lines(struct xc5000_priv *priv, u16 *frame_lines)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return xc5000_readreg(priv, XREG_FRAME_LINES, frame_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int xc_get_quality(struct xc5000_priv *priv, u16 *quality)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return xc5000_readreg(priv, XREG_QUALITY, quality);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int xc_get_analogsnr(struct xc5000_priv *priv, u16 *snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return xc5000_readreg(priv, XREG_SNR, snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int xc_get_totalgain(struct xc5000_priv *priv, u16 *totalgain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return xc5000_readreg(priv, XREG_TOTALGAIN, totalgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define XC_TUNE_ANALOG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define XC_TUNE_DIGITAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int xc_tune_channel(struct xc5000_priv *priv, u32 freq_hz, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dprintk(1, "%s(%u)\n", __func__, freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (xc_set_rf_frequency(priv, freq_hz) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int xc_set_xtal(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) switch (priv->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case XC5000A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* 32.000 MHz xtal is default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case XC5000C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) switch (priv->xtal_khz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* 32.000 MHz xtal is default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case 31875:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* 31.875 MHz xtal configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = xc_write_reg(priv, 0x000f, 0x8081);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int xc5000_fwupload(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) const struct xc5000_fw_cfg *desired_fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* request the firmware, this will block and timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dprintk(1, "waiting for firmware upload (%s)...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) desired_fw->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) priv->pll_register_no = desired_fw->pll_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) priv->init_status_supported = desired_fw->init_status_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) priv->fw_checksum_supported = desired_fw->fw_checksum_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dprintk(1, "firmware uploading...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = xc_load_i2c_sequence(fe, fw->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = xc_set_xtal(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dprintk(1, "Firmware upload complete...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) printk(KERN_ERR "xc5000: firmware upload failed...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void xc_debug_dump(struct xc5000_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u16 adc_envelope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 freq_error_hz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u16 lock_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 hsync_freq_hz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u16 frame_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u16 quality;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u16 snr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u16 totalgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u8 hw_majorversion = 0, hw_minorversion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u8 fw_majorversion = 0, fw_minorversion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u16 fw_buildversion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u16 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Wait for stats to stabilize.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * Frame Lines needs two frame times after initial lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * before it is valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) xc_get_adc_envelope(priv, &adc_envelope);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dprintk(1, "*** ADC envelope (0-1023) = %d\n", adc_envelope);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) xc_get_frequency_error(priv, &freq_error_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dprintk(1, "*** Frequency error = %d Hz\n", freq_error_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) xc_get_lock_status(priv, &lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dprintk(1, "*** Lock status (0-Wait, 1-Locked, 2-No-signal) = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) xc_get_version(priv, &hw_majorversion, &hw_minorversion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) &fw_majorversion, &fw_minorversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) xc_get_buildversion(priv, &fw_buildversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dprintk(1, "*** HW: V%d.%d, FW: V %d.%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) hw_majorversion, hw_minorversion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) fw_majorversion, fw_minorversion, fw_buildversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) xc_get_hsync_freq(priv, &hsync_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dprintk(1, "*** Horizontal sync frequency = %d Hz\n", hsync_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) xc_get_frame_lines(priv, &frame_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dprintk(1, "*** Frame lines = %d\n", frame_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) xc_get_quality(priv, &quality);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dprintk(1, "*** Quality (0:<8dB, 7:>56dB) = %d\n", quality & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) xc_get_analogsnr(priv, &snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dprintk(1, "*** Unweighted analog SNR = %d dB\n", snr & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) xc_get_totalgain(priv, &totalgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dprintk(1, "*** Total gain = %d.%d dB\n", totalgain / 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) (totalgain % 256) * 100 / 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (priv->pll_register_no) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!xc5000_readreg(priv, priv->pll_register_no, ®val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dprintk(1, "*** PLL lock status = 0x%04x\n", regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static int xc5000_tune_digital(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u32 bw = fe->dtv_property_cache.bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret = xc_set_signal_source(priv, priv->rf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) "xc5000: xc_set_signal_source(%d) failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) priv->rf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = xc_set_tv_standard(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) xc5000_standard[priv->video_standard].video_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) xc5000_standard[priv->video_standard].audio_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) printk(KERN_ERR "xc5000: xc_set_tv_standard failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = xc_set_IF_frequency(priv, priv->if_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) printk(KERN_ERR "xc5000: xc_Set_IF_frequency(%d) failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) priv->if_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dprintk(1, "%s() setting OUTPUT_AMP to 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) __func__, priv->output_amp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) xc_write_reg(priv, XREG_OUTPUT_AMP, priv->output_amp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) xc_tune_channel(priv, priv->freq_hz, XC_TUNE_DIGITAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) xc_debug_dump(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) priv->bandwidth = bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int xc5000_set_digital_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u32 bw = fe->dtv_property_cache.bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 freq = fe->dtv_property_cache.frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 delsys = fe->dtv_property_cache.delivery_system;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (xc_load_fw_and_init_tuner(fe, 0) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dprintk(1, "Unable to load firmware and init tuner\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dprintk(1, "%s() frequency=%d (Hz)\n", __func__, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) switch (delsys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) case SYS_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dprintk(1, "%s() VSB modulation\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) priv->rf_mode = XC_RF_MODE_AIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) priv->freq_offset = 1750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) priv->video_standard = DTV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) case SYS_DVBC_ANNEX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dprintk(1, "%s() QAM modulation\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) priv->rf_mode = XC_RF_MODE_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) priv->freq_offset = 1750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) priv->video_standard = DTV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case SYS_ISDBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* All ISDB-T are currently for 6 MHz bw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) bw = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* fall to OFDM handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case SYS_DMBTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) case SYS_DVBT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dprintk(1, "%s() OFDM\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) switch (bw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) priv->video_standard = DTV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) priv->freq_offset = 1750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) priv->video_standard = DTV7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) priv->freq_offset = 2250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) priv->video_standard = DTV8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) priv->freq_offset = 2750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) printk(KERN_ERR "xc5000 bandwidth not set!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) priv->rf_mode = XC_RF_MODE_AIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case SYS_DVBC_ANNEX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dprintk(1, "%s() QAM modulation\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) priv->rf_mode = XC_RF_MODE_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (bw <= 6000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) priv->video_standard = DTV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) priv->freq_offset = 1750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) b = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) } else if (bw <= 7000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) priv->video_standard = DTV7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) priv->freq_offset = 2250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) b = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) priv->video_standard = DTV7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) priv->freq_offset = 2750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) b = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dprintk(1, "%s() Bandwidth %dMHz (%d)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) b, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) printk(KERN_ERR "xc5000: delivery system is not supported!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) priv->freq_hz = freq - priv->freq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) priv->mode = V4L2_TUNER_DIGITAL_TV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dprintk(1, "%s() frequency=%d (compensated to %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) __func__, freq, priv->freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return xc5000_tune_digital(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int xc5000_is_firmware_loaded(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret = xc5000_readreg(priv, XREG_PRODUCT_ID, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (id == XC_PRODUCT_ID_FW_NOT_LOADED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dprintk(1, "%s() returns id = 0x%x\n", __func__, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dprintk(1, "%s() returns error %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static void xc5000_config_tv(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct analog_parameters *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dprintk(1, "%s() frequency=%d (in units of 62.5khz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) __func__, params->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Fix me: it could be air. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) priv->rf_mode = params->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (params->mode > XC_RF_MODE_CABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) priv->rf_mode = XC_RF_MODE_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* params->frequency is in units of 62.5khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) priv->freq_hz = params->frequency * 62500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* FIX ME: Some video standards may have several possible audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) standards. We simply default to one of them here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (params->std & V4L2_STD_MN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* default to BTSC audio standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) priv->video_standard = MN_NTSC_PAL_BTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (params->std & V4L2_STD_PAL_BG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* default to NICAM audio standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) priv->video_standard = BG_PAL_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (params->std & V4L2_STD_PAL_I) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* default to NICAM audio standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) priv->video_standard = I_PAL_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (params->std & V4L2_STD_PAL_DK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* default to NICAM audio standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) priv->video_standard = DK_PAL_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (params->std & V4L2_STD_SECAM_DK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* default to A2 DK1 audio standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) priv->video_standard = DK_SECAM_A2DK1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (params->std & V4L2_STD_SECAM_L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) priv->video_standard = L_SECAM_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (params->std & V4L2_STD_SECAM_LC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) priv->video_standard = LC_SECAM_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int xc5000_set_tv_freq(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u16 pll_lock_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) tune_channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ret = xc_set_signal_source(priv, priv->rf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "xc5000: xc_set_signal_source(%d) failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) priv->rf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = xc_set_tv_standard(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) xc5000_standard[priv->video_standard].video_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) xc5000_standard[priv->video_standard].audio_mode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) printk(KERN_ERR "xc5000: xc_set_tv_standard failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) xc_write_reg(priv, XREG_OUTPUT_AMP, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) xc_tune_channel(priv, priv->freq_hz, XC_TUNE_ANALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) xc_debug_dump(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (priv->pll_register_no != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret = xc5000_readreg(priv, priv->pll_register_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) &pll_lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (pll_lock_status > 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* PLL is unlocked, force reload of the firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dprintk(1, "xc5000: PLL not locked (0x%x). Reloading...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) pll_lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (xc_load_fw_and_init_tuner(fe, 1) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) printk(KERN_ERR "xc5000: Unable to reload fw\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) goto tune_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int xc5000_config_radio(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct analog_parameters *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dprintk(1, "%s() frequency=%d (in units of khz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) __func__, params->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (priv->radio_input == XC5000_RADIO_NOT_CONFIGURED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dprintk(1, "%s() radio input not configured\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) priv->freq_hz = params->frequency * 125 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) priv->rf_mode = XC_RF_MODE_AIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int xc5000_set_radio_freq(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) u8 radio_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (priv->radio_input == XC5000_RADIO_FM1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) radio_input = FM_RADIO_INPUT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) else if (priv->radio_input == XC5000_RADIO_FM2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) radio_input = FM_RADIO_INPUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) else if (priv->radio_input == XC5000_RADIO_FM1_MONO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) radio_input = FM_RADIO_INPUT1_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) dprintk(1, "%s() unknown radio input %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) priv->radio_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ret = xc_set_tv_standard(priv, xc5000_standard[radio_input].video_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) xc5000_standard[radio_input].audio_mode, radio_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) printk(KERN_ERR "xc5000: xc_set_tv_standard failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ret = xc_set_signal_source(priv, priv->rf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) "xc5000: xc_set_signal_source(%d) failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) priv->rf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if ((priv->radio_input == XC5000_RADIO_FM1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) (priv->radio_input == XC5000_RADIO_FM2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) xc_write_reg(priv, XREG_OUTPUT_AMP, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) else if (priv->radio_input == XC5000_RADIO_FM1_MONO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) xc_write_reg(priv, XREG_OUTPUT_AMP, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) xc_tune_channel(priv, priv->freq_hz, XC_TUNE_ANALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static int xc5000_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (xc_load_fw_and_init_tuner(fe, 0) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) dprintk(1, "Unable to load firmware and init tuner\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) switch (priv->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) case V4L2_TUNER_RADIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return xc5000_set_radio_freq(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case V4L2_TUNER_ANALOG_TV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return xc5000_set_tv_freq(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) case V4L2_TUNER_DIGITAL_TV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return xc5000_tune_digital(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static int xc5000_set_analog_params(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct analog_parameters *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (priv->i2c_props.adap == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) switch (params->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) case V4L2_TUNER_RADIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ret = xc5000_config_radio(fe, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) case V4L2_TUNER_ANALOG_TV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) xc5000_config_tv(fe, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) priv->mode = params->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return xc5000_set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int xc5000_get_frequency(struct dvb_frontend *fe, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) *freq = priv->freq_hz + priv->freq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int xc5000_get_if_frequency(struct dvb_frontend *fe, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) *freq = priv->if_khz * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static int xc5000_get_bandwidth(struct dvb_frontend *fe, u32 *bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) *bw = priv->bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static int xc5000_get_status(struct dvb_frontend *fe, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) u16 lock_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) xc_get_lock_status(priv, &lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) dprintk(1, "%s() lock_status = 0x%08x\n", __func__, lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) *status = lock_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static int xc_load_fw_and_init_tuner(struct dvb_frontend *fe, int force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) const struct xc5000_fw_cfg *desired_fw = xc5000_assign_firmware(priv->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) u16 pll_lock_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) u16 fw_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) cancel_delayed_work(&priv->timer_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (!force && xc5000_is_firmware_loaded(fe) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (!priv->firmware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ret = request_firmware(&fw, desired_fw->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) priv->i2c_props.adap->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) pr_err("xc5000: Upload failed. rc %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) dprintk(1, "firmware read %zu bytes.\n", fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (fw->size != desired_fw->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) pr_err("xc5000: Firmware file with incorrect size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) priv->firmware = fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) fw = priv->firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* Try up to 5 times to load firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) printk(KERN_CONT " - retrying to upload firmware.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ret = xc5000_fwupload(fe, desired_fw, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (priv->fw_checksum_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (xc5000_readreg(priv, XREG_FW_CHECKSUM, &fw_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) "xc5000: FW checksum reading failed.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (!fw_ck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) "xc5000: FW checksum failed = 0x%04x.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) fw_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Start the tuner self-calibration process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ret = xc_initialize(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) printk(KERN_ERR "xc5000: Can't request self-calibration.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* Wait for calibration to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * We could continue but XC5000 will clock stretch subsequent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * I2C transactions until calibration is complete. This way we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * don't have to rely on clock stretching working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (priv->init_status_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (xc5000_readreg(priv, XREG_INIT_STATUS, &fw_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) "xc5000: FW failed reading init status.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (!fw_ck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) "xc5000: FW init status failed = 0x%04x.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) fw_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (priv->pll_register_no) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ret = xc5000_readreg(priv, priv->pll_register_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) &pll_lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (pll_lock_status > 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /* PLL is unlocked, force reload of the firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) "xc5000: PLL not running after fwload.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* Default to "CABLE" mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ret = xc_write_reg(priv, XREG_SIGNALSOURCE, XC_RF_MODE_CABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) printk(KERN_ERR "xc5000: can't set to cable mode.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) printk(KERN_INFO "xc5000: Firmware %s loaded and running.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) desired_fw->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) printk(KERN_CONT " - too many retries. Giving up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static void xc5000_do_timer_sleep(struct work_struct *timer_sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct xc5000_priv *priv =container_of(timer_sleep, struct xc5000_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) timer_sleep.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct dvb_frontend *fe = priv->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* According to Xceive technical support, the "powerdown" register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) was removed in newer versions of the firmware. The "supported"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) way to sleep the tuner is to pull the reset pin low for 10ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ret = xc5000_tuner_reset(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) "xc5000: %s() unable to shutdown tuner\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static int xc5000_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Avoid firmware reload on slow devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (no_poweroff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) schedule_delayed_work(&priv->timer_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) msecs_to_jiffies(XC5000_SLEEP_TIME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static int xc5000_suspend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) cancel_delayed_work(&priv->timer_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) ret = xc5000_tuner_reset(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) "xc5000: %s() unable to shutdown tuner\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static int xc5000_resume(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* suspended before firmware is loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) Avoid firmware load in resume path. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (!priv->firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return xc5000_set_params(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static int xc5000_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (xc_load_fw_and_init_tuner(fe, 0) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) printk(KERN_ERR "xc5000: Unable to initialise tuner\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) xc_debug_dump(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static void xc5000_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) mutex_lock(&xc5000_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) cancel_delayed_work(&priv->timer_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (priv->firmware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) release_firmware(priv->firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) priv->firmware = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) hybrid_tuner_release_state(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) mutex_unlock(&xc5000_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static int xc5000_set_config(struct dvb_frontend *fe, void *priv_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct xc5000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) struct xc5000_config *p = priv_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (p->if_khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) priv->if_khz = p->if_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (p->radio_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) priv->radio_input = p->radio_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (p->output_amp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) priv->output_amp = p->output_amp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static const struct dvb_tuner_ops xc5000_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .name = "Xceive XC5000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .frequency_min_hz = 1 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .frequency_max_hz = 1023 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .frequency_step_hz = 50 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .release = xc5000_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .init = xc5000_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .sleep = xc5000_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .suspend = xc5000_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .resume = xc5000_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .set_config = xc5000_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .set_params = xc5000_set_digital_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .set_analog_params = xc5000_set_analog_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .get_frequency = xc5000_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .get_if_frequency = xc5000_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .get_bandwidth = xc5000_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .get_status = xc5000_get_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) const struct xc5000_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct xc5000_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) int instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) u16 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dprintk(1, "%s(%d-%04x)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) i2c ? i2c_adapter_id(i2c) : -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) cfg ? cfg->i2c_address : -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) mutex_lock(&xc5000_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) instance = hybrid_tuner_request_state(struct xc5000_priv, priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) hybrid_tuner_instance_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) i2c, cfg->i2c_address, "xc5000");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) switch (instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* new tuner instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) priv->bandwidth = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) priv->fe = fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) INIT_DELAYED_WORK(&priv->timer_sleep, xc5000_do_timer_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* existing tuner instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (priv->if_khz == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /* If the IF hasn't been set yet, use the value provided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) the caller (occurs in hybrid devices where the analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) call to xc5000_attach occurs before the digital side) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) priv->if_khz = cfg->if_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (priv->xtal_khz == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) priv->xtal_khz = cfg->xtal_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (priv->radio_input == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) priv->radio_input = cfg->radio_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* don't override chip id if it's already been set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) unless explicitly specified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if ((priv->chip_id == 0) || (cfg->chip_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* use default chip id if none specified, set to 0 so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) it can be overridden if this is a hybrid driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) priv->chip_id = (cfg->chip_id) ? cfg->chip_id : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* don't override output_amp if it's already been set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) unless explicitly specified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if ((priv->output_amp == 0) || (cfg->output_amp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* use default output_amp value if none specified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) priv->output_amp = (cfg->output_amp) ? cfg->output_amp : 0x8a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* Check if firmware has been loaded. It is possible that another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) instance of the driver has loaded the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (xc5000_readreg(priv, XREG_PRODUCT_ID, &id) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) case XC_PRODUCT_ID_FW_LOADED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) "xc5000: Successfully identified at address 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) cfg->i2c_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) "xc5000: Firmware has been loaded previously\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) case XC_PRODUCT_ID_FW_NOT_LOADED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) "xc5000: Successfully identified at address 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) cfg->i2c_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) "xc5000: Firmware has not been loaded previously\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) "xc5000: Device not found at addr 0x%02x (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) cfg->i2c_address, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) mutex_unlock(&xc5000_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) memcpy(&fe->ops.tuner_ops, &xc5000_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) mutex_unlock(&xc5000_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) xc5000_release(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) EXPORT_SYMBOL(xc5000_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) MODULE_AUTHOR("Steven Toth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) MODULE_DESCRIPTION("Xceive xc5000 silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) MODULE_FIRMWARE(XC5000A_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) MODULE_FIRMWARE(XC5000C_FIRMWARE);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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