^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Xceive XC4000 "QAM/8VSB single chip tuner"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007 Xceive Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2007 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2009 Devin Heitmueller <dheitmueller@kernellabs.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2009 Davide Ferri <d.ferri@zero11.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2010 Istvan Varga <istvan_v@mailbox.hu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "xc4000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "tuner-i2c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "tuner-xc2028-types.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_PARM_DESC(debug, "Debugging level (0 to 2, default: 0 (off)).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int no_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) module_param(no_poweroff, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_PARM_DESC(no_poweroff, "Power management (1: disabled, 2: enabled, 0 (default): use device-specific default mode).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int audio_std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) module_param(audio_std, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MODULE_PARM_DESC(audio_std, "Audio standard. XC4000 audio decoder explicitly needs to know what audio standard is needed for some video standards with audio A2 or NICAM. The valid settings are a sum of:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) " 1: use NICAM/B or A2/B instead of NICAM/A or A2/A\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) " 2: use A2 instead of NICAM or BTSC\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) " 4: use SECAM/K3 instead of K1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) " 8: use PAL-D/K audio for SECAM-D/K\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "16: use FM radio input 1 instead of input 2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "32: use mono audio (the lower three bits are ignored)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static char firmware_name[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the default firmware name.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static DEFINE_MUTEX(xc4000_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static LIST_HEAD(hybrid_tuner_instance_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define dprintk(level, fmt, arg...) if (debug >= level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) printk(KERN_INFO "%s: " fmt, "xc4000", ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* struct for storing firmware table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct firmware_description {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) v4l2_std_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __u16 int_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned char *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct firmware_properties {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) v4l2_std_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) v4l2_std_id std_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __u16 int_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int scode_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int scode_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct xc4000_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct tuner_i2c_props i2c_props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct list_head hybrid_tuner_instance_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct firmware_description *firm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int firm_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 if_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 freq_hz, freq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 video_standard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 rf_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 default_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 dvb_amplitude;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 set_smoothedcvbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 ignore_i2c_write_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __u16 firm_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct firmware_properties cur_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __u16 hwmodel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __u16 hwvers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define XC4000_AUDIO_STD_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define XC4000_AUDIO_STD_A2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define XC4000_AUDIO_STD_K3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define XC4000_AUDIO_STD_L 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define XC4000_AUDIO_STD_INPUT1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define XC4000_AUDIO_STD_MONO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define XC4000_DEFAULT_FIRMWARE "dvb-fe-xc4000-1.4.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define XC4000_DEFAULT_FIRMWARE_NEW "dvb-fe-xc4000-1.4.1.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Misc Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MAX_TV_STANDARD 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define XC_MAX_I2C_WRITE_LENGTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define XC_POWERED_DOWN 0x80000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Signal Types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define XC_RF_MODE_AIR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define XC_RF_MODE_CABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Product id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define XC_PRODUCT_ID_FW_NOT_LOADED 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define XC_PRODUCT_ID_XC4000 0x0FA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define XC_PRODUCT_ID_XC4100 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Registers (Write-only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define XREG_INIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define XREG_VIDEO_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define XREG_AUDIO_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define XREG_RF_FREQ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define XREG_D_CODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define XREG_DIRECTSITTING_MODE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define XREG_SEEK_MODE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define XREG_POWER_DOWN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define XREG_SIGNALSOURCE 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define XREG_SMOOTHEDCVBS 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define XREG_AMPLITUDE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Registers (Read-only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define XREG_ADC_ENV 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define XREG_QUALITY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define XREG_FRAME_LINES 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define XREG_HSYNC_FREQ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define XREG_LOCK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define XREG_FREQ_ERROR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define XREG_SNR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define XREG_VERSION 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define XREG_PRODUCT_ID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define XREG_SIGNAL_LEVEL 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define XREG_NOISE_LEVEL 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) Basic firmware description. This will remain with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) the driver for documentation purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) This represents an I2C firmware file encoded as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) string of unsigned char. Format is as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) char[0 ]=len0_MSB -> len = len_MSB * 256 + len_LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) char[1 ]=len0_LSB -> length of first write transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) char[2 ]=data0 -> first byte to be sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) char[3 ]=data1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) char[4 ]=data2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) char[ ]=...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) char[M ]=dataN -> last byte to be sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) char[M+1]=len1_MSB -> len = len_MSB * 256 + len_LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) char[M+2]=len1_LSB -> length of second write transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) char[M+3]=data0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) char[M+4]=data1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) The [len] value should be interpreted as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) len= len_MSB _ len_LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) len=1111_1111_1111_1111 : End of I2C_SEQUENCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) len=0000_0000_0000_0000 : Reset command: Do hardware reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) len=0NNN_NNNN_NNNN_NNNN : Normal transaction: number of bytes = {1:32767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) len=1WWW_WWWW_WWWW_WWWW : Wait command: wait for {1:32767} ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) For the RESET and WAIT commands, the two following bytes will contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) immediately the length of the following transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct XC_TV_STANDARD {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const char *Name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u16 audio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u16 video_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u16 int_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Tuner standards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define XC4000_MN_NTSC_PAL_BTSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define XC4000_MN_NTSC_PAL_A2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define XC4000_MN_NTSC_PAL_EIAJ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define XC4000_MN_NTSC_PAL_Mono 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define XC4000_BG_PAL_A2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define XC4000_BG_PAL_NICAM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define XC4000_BG_PAL_MONO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define XC4000_I_PAL_NICAM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define XC4000_I_PAL_NICAM_MONO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define XC4000_DK_PAL_A2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define XC4000_DK_PAL_NICAM 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define XC4000_DK_PAL_MONO 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define XC4000_DK_SECAM_A2DK1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define XC4000_DK_SECAM_A2LDK3 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define XC4000_DK_SECAM_A2MONO 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define XC4000_DK_SECAM_NICAM 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define XC4000_L_SECAM_NICAM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define XC4000_LC_SECAM_NICAM 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define XC4000_DTV6 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define XC4000_DTV8 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define XC4000_DTV7_8 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define XC4000_DTV7 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define XC4000_FM_Radio_INPUT2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define XC4000_FM_Radio_INPUT1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct XC_TV_STANDARD xc4000_standard[MAX_TV_STANDARD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {"M/N-NTSC/PAL-BTSC", 0x0000, 0x80A0, 4500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {"M/N-NTSC/PAL-A2", 0x0000, 0x80A0, 4600},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {"M/N-NTSC/PAL-EIAJ", 0x0040, 0x80A0, 4500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {"M/N-NTSC/PAL-Mono", 0x0078, 0x80A0, 4500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {"B/G-PAL-A2", 0x0000, 0x8159, 5640},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {"B/G-PAL-NICAM", 0x0004, 0x8159, 5740},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {"B/G-PAL-MONO", 0x0078, 0x8159, 5500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {"I-PAL-NICAM", 0x0080, 0x8049, 6240},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {"I-PAL-NICAM-MONO", 0x0078, 0x8049, 6000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {"D/K-PAL-A2", 0x0000, 0x8049, 6380},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {"D/K-PAL-NICAM", 0x0080, 0x8049, 6200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {"D/K-PAL-MONO", 0x0078, 0x8049, 6500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {"D/K-SECAM-A2 DK1", 0x0000, 0x8049, 6340},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {"D/K-SECAM-A2 L/DK3", 0x0000, 0x8049, 6000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {"D/K-SECAM-A2 MONO", 0x0078, 0x8049, 6500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {"D/K-SECAM-NICAM", 0x0080, 0x8049, 6200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {"L-SECAM-NICAM", 0x8080, 0x0009, 6200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {"L'-SECAM-NICAM", 0x8080, 0x4009, 6200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {"DTV6", 0x00C0, 0x8002, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {"DTV8", 0x00C0, 0x800B, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {"DTV7/8", 0x00C0, 0x801B, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {"DTV7", 0x00C0, 0x8007, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {"FM Radio-INPUT2", 0x0008, 0x9800, 10700},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {"FM Radio-INPUT1", 0x0008, 0x9000, 10700}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int xc4000_readreg(struct xc4000_priv *priv, u16 reg, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int xc4000_tuner_reset(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void xc_debug_dump(struct xc4000_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int xc_send_i2c_data(struct xc4000_priv *priv, u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct i2c_msg msg = { .addr = priv->i2c_props.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .flags = 0, .buf = buf, .len = len };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (i2c_transfer(priv->i2c_props.adap, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (priv->ignore_i2c_write_errors == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) printk(KERN_ERR "xc4000: I2C write failed (len=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (len == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) printk(KERN_ERR "bytes %*ph\n", 4, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int xc4000_tuner_reset(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (fe->callback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = fe->callback(((fe->dvb) && (fe->dvb->priv)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) fe->dvb->priv :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) priv->i2c_props.adap->algo_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DVB_FRONTEND_COMPONENT_TUNER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) XC4000_TUNER_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) printk(KERN_ERR "xc4000: reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) printk(KERN_ERR "xc4000: no tuner reset callback function, fatal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int xc_write_reg(struct xc4000_priv *priv, u16 regAddr, u16 i2cData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) buf[0] = (regAddr >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) buf[1] = regAddr & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) buf[2] = (i2cData >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) buf[3] = i2cData & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) result = xc_send_i2c_data(priv, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int xc_load_i2c_sequence(struct dvb_frontend *fe, const u8 *i2c_sequence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int i, nbytes_to_send, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int len, pos, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 buf[XC_MAX_I2C_WRITE_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) while ((i2c_sequence[index] != 0xFF) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) (i2c_sequence[index + 1] != 0xFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) len = i2c_sequence[index] * 256 + i2c_sequence[index+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (len == 0x0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* RESET command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* NOTE: this is ignored, as the reset callback was */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* already called by check_firmware() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } else if (len & 0x8000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* WAIT command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) msleep(len & 0x7FFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Send i2c data whilst ensuring individual transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * do not exceed XC_MAX_I2C_WRITE_LENGTH bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) buf[0] = i2c_sequence[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) buf[1] = i2c_sequence[index + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pos = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) while (pos < len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if ((len - pos) > XC_MAX_I2C_WRITE_LENGTH - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) nbytes_to_send =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) XC_MAX_I2C_WRITE_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) nbytes_to_send = (len - pos + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) for (i = 2; i < nbytes_to_send; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) buf[i] = i2c_sequence[index + pos +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) i - 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) result = xc_send_i2c_data(priv, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) nbytes_to_send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pos += nbytes_to_send - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) index += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int xc_set_tv_standard(struct xc4000_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u16 video_mode, u16 audio_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dprintk(1, "%s(0x%04x,0x%04x)\n", __func__, video_mode, audio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dprintk(1, "%s() Standard = %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) xc4000_standard[priv->video_standard].Name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Don't complain when the request fails because of i2c stretching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) priv->ignore_i2c_write_errors = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret = xc_write_reg(priv, XREG_VIDEO_MODE, video_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ret = xc_write_reg(priv, XREG_AUDIO_MODE, audio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) priv->ignore_i2c_write_errors = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int xc_set_signal_source(struct xc4000_priv *priv, u16 rf_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dprintk(1, "%s(%d) Source = %s\n", __func__, rf_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) rf_mode == XC_RF_MODE_AIR ? "ANTENNA" : "CABLE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if ((rf_mode != XC_RF_MODE_AIR) && (rf_mode != XC_RF_MODE_CABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) rf_mode = XC_RF_MODE_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "%s(), Invalid mode, defaulting to CABLE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return xc_write_reg(priv, XREG_SIGNALSOURCE, rf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct dvb_tuner_ops xc4000_tuner_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int xc_set_rf_frequency(struct xc4000_priv *priv, u32 freq_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u16 freq_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dprintk(1, "%s(%u)\n", __func__, freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if ((freq_hz > xc4000_tuner_ops.info.frequency_max_hz) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) (freq_hz < xc4000_tuner_ops.info.frequency_min_hz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) freq_code = (u16)(freq_hz / 15625);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* WAS: Starting in firmware version 1.1.44, Xceive recommends using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) FINERFREQ for all normal tuning (the doc indicates reg 0x03 should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) only be used for fast scanning for channel lock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* WAS: XREG_FINERFREQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return xc_write_reg(priv, XREG_RF_FREQ, freq_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int xc_get_adc_envelope(struct xc4000_priv *priv, u16 *adc_envelope)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return xc4000_readreg(priv, XREG_ADC_ENV, adc_envelope);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int xc_get_frequency_error(struct xc4000_priv *priv, u32 *freq_error_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u16 regData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) result = xc4000_readreg(priv, XREG_FREQ_ERROR, ®Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) tmp = (u32)regData & 0xFFFFU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tmp = (tmp < 0x8000U ? tmp : 0x10000U - tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) (*freq_error_hz) = tmp * 15625;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int xc_get_lock_status(struct xc4000_priv *priv, u16 *lock_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return xc4000_readreg(priv, XREG_LOCK, lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int xc_get_version(struct xc4000_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u8 *hw_majorversion, u8 *hw_minorversion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u8 *fw_majorversion, u8 *fw_minorversion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) result = xc4000_readreg(priv, XREG_VERSION, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) (*hw_majorversion) = (data >> 12) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) (*hw_minorversion) = (data >> 8) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) (*fw_majorversion) = (data >> 4) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) (*fw_minorversion) = data & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int xc_get_hsync_freq(struct xc4000_priv *priv, u32 *hsync_freq_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u16 regData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) result = xc4000_readreg(priv, XREG_HSYNC_FREQ, ®Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) (*hsync_freq_hz) = ((regData & 0x0fff) * 763)/100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int xc_get_frame_lines(struct xc4000_priv *priv, u16 *frame_lines)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return xc4000_readreg(priv, XREG_FRAME_LINES, frame_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int xc_get_quality(struct xc4000_priv *priv, u16 *quality)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return xc4000_readreg(priv, XREG_QUALITY, quality);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int xc_get_signal_level(struct xc4000_priv *priv, u16 *signal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return xc4000_readreg(priv, XREG_SIGNAL_LEVEL, signal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int xc_get_noise_level(struct xc4000_priv *priv, u16 *noise)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return xc4000_readreg(priv, XREG_NOISE_LEVEL, noise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static u16 xc_wait_for_lock(struct xc4000_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u16 lock_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int watchdog_count = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) while ((lock_state == 0) && (watchdog_count > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) xc_get_lock_status(priv, &lock_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (lock_state != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) watchdog_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return lock_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int xc_tune_channel(struct xc4000_priv *priv, u32 freq_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dprintk(1, "%s(%u)\n", __func__, freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Don't complain when the request fails because of i2c stretching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) priv->ignore_i2c_write_errors = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) result = xc_set_rf_frequency(priv, freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) priv->ignore_i2c_write_errors = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* wait for lock only in analog TV mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if ((priv->cur_fw.type & (FM | DTV6 | DTV7 | DTV78 | DTV8)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (xc_wait_for_lock(priv) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Wait for stats to stabilize.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * Frame Lines needs two frame times after initial lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * before it is valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) msleep(debug ? 100 : 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) xc_debug_dump(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int xc4000_readreg(struct xc4000_priv *priv, u16 reg, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u8 buf[2] = { reg >> 8, reg & 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u8 bval[2] = { 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { .addr = priv->i2c_props.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .flags = 0, .buf = &buf[0], .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { .addr = priv->i2c_props.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .flags = I2C_M_RD, .buf = &bval[0], .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (i2c_transfer(priv->i2c_props.adap, msg, 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) printk(KERN_ERR "xc4000: I2C read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) *val = (bval[0] << 8) | bval[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define dump_firm_type(t) dump_firm_type_and_int_freq(t, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void dump_firm_type_and_int_freq(unsigned int type, u16 int_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (type & BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) printk(KERN_CONT "BASE ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (type & INIT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) printk(KERN_CONT "INIT1 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (type & F8MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) printk(KERN_CONT "F8MHZ ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (type & MTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) printk(KERN_CONT "MTS ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (type & D2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) printk(KERN_CONT "D2620 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (type & D2633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) printk(KERN_CONT "D2633 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (type & DTV6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) printk(KERN_CONT "DTV6 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (type & QAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) printk(KERN_CONT "QAM ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (type & DTV7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) printk(KERN_CONT "DTV7 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (type & DTV78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) printk(KERN_CONT "DTV78 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (type & DTV8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) printk(KERN_CONT "DTV8 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (type & FM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) printk(KERN_CONT "FM ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (type & INPUT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) printk(KERN_CONT "INPUT1 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (type & LCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) printk(KERN_CONT "LCD ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (type & NOGD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) printk(KERN_CONT "NOGD ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (type & MONO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) printk(KERN_CONT "MONO ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (type & ATSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) printk(KERN_CONT "ATSC ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (type & IF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) printk(KERN_CONT "IF ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (type & LG60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) printk(KERN_CONT "LG60 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (type & ATI638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) printk(KERN_CONT "ATI638 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (type & OREN538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) printk(KERN_CONT "OREN538 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (type & OREN36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) printk(KERN_CONT "OREN36 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (type & TOYOTA388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) printk(KERN_CONT "TOYOTA388 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (type & TOYOTA794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) printk(KERN_CONT "TOYOTA794 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (type & DIBCOM52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) printk(KERN_CONT "DIBCOM52 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (type & ZARLINK456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) printk(KERN_CONT "ZARLINK456 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (type & CHINA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) printk(KERN_CONT "CHINA ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (type & F6MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) printk(KERN_CONT "F6MHZ ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (type & INPUT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) printk(KERN_CONT "INPUT2 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (type & SCODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) printk(KERN_CONT "SCODE ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (type & HAS_IF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) printk(KERN_CONT "HAS_IF_%d ", int_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int seek_firmware(struct dvb_frontend *fe, unsigned int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) v4l2_std_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int i, best_i = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unsigned int best_nr_diffs = 255U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!priv->firm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) printk(KERN_ERR "Error! firmware not loaded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (((type & ~SCODE) == 0) && (*id == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) *id = V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Seek for generic video standard match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) for (i = 0; i < priv->firm_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) v4l2_std_id id_diff_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) (priv->firm[i].id ^ (*id)) & (*id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned int type_diff_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) (priv->firm[i].type ^ type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) & (BASE_TYPES | DTV_TYPES | LCD | NOGD | MONO | SCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned int nr_diffs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (type_diff_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) & (BASE | INIT1 | FM | DTV6 | DTV7 | DTV78 | DTV8 | SCODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) nr_diffs = hweight64(id_diff_mask) + hweight32(type_diff_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (!nr_diffs) /* Supports all the requested standards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (nr_diffs < best_nr_diffs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) best_nr_diffs = nr_diffs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) best_i = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* FIXME: Would make sense to seek for type "hint" match ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (best_i < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) i = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) goto ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (best_nr_diffs > 0U) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) "Selecting best matching firmware (%u bits differ) for type=(%x), id %016llx:\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) best_nr_diffs, type, (unsigned long long)*id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) i = best_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) *id = priv->firm[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (debug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) printk(KERN_DEBUG "%s firmware for type=",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) (i < 0) ? "Can't find" : "Found");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dump_firm_type(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) printk(KERN_DEBUG "(%x), id %016llx.\n", type, (unsigned long long)*id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int load_firmware(struct dvb_frontend *fe, unsigned int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) v4l2_std_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int pos, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) unsigned char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) pos = seek_firmware(fe, type, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (pos < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) p = priv->firm[pos].ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Don't complain when the request fails because of i2c stretching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) priv->ignore_i2c_write_errors = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) rc = xc_load_i2c_sequence(fe, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) priv->ignore_i2c_write_errors = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int xc4000_fwupload(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) const struct firmware *fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) const unsigned char *p, *endp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int n, n_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) char name[33];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) const char *fname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (firmware_name[0] != '\0') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) fname = firmware_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dprintk(1, "Reading custom firmware %s\n", fname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) rc = request_firmware(&fw, fname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) priv->i2c_props.adap->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) fname = XC4000_DEFAULT_FIRMWARE_NEW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dprintk(1, "Trying to read firmware %s\n", fname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) rc = request_firmware(&fw, fname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) priv->i2c_props.adap->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (rc == -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) fname = XC4000_DEFAULT_FIRMWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dprintk(1, "Trying to read firmware %s\n", fname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) rc = request_firmware(&fw, fname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) priv->i2c_props.adap->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (rc == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) printk(KERN_ERR "Error: firmware %s not found.\n", fname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) printk(KERN_ERR "Error %d while requesting firmware %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) rc, fname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dprintk(1, "Loading Firmware: %s\n", fname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) p = fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) endp = p + fw->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (fw->size < sizeof(name) - 1 + 2 + 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) printk(KERN_ERR "Error: firmware file %s has invalid size!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) fname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) goto corrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) memcpy(name, p, sizeof(name) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) name[sizeof(name) - 1] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) p += sizeof(name) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) priv->firm_version = get_unaligned_le16(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) p += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) n_array = get_unaligned_le16(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) p += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dprintk(1, "Loading %d firmware images from %s, type: %s, ver %d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) n_array, fname, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) priv->firm_version >> 8, priv->firm_version & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) priv->firm = kcalloc(n_array, sizeof(*priv->firm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (priv->firm == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) printk(KERN_ERR "Not enough memory to load firmware file.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) priv->firm_size = n_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) n = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) while (p < endp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) __u32 type, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) v4l2_std_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) __u16 int_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (n >= n_array) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) printk(KERN_ERR "More firmware images in file than were expected!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) goto corrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Checks if there's enough bytes to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (endp - p < sizeof(type) + sizeof(id) + sizeof(size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) goto header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) type = get_unaligned_le32(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) p += sizeof(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) id = get_unaligned_le64(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) p += sizeof(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (type & HAS_IF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int_freq = get_unaligned_le16(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) p += sizeof(int_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (endp - p < sizeof(size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) goto header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) size = get_unaligned_le32(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) p += sizeof(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (!size || size > endp - p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) printk(KERN_ERR "Firmware type (%x), id %llx is corrupted (size=%zd, expected %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) type, (unsigned long long)id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) endp - p, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) goto corrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) priv->firm[n].ptr = kmemdup(p, size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (priv->firm[n].ptr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) printk(KERN_ERR "Not enough memory to load firmware file.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (debug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) printk(KERN_DEBUG "Reading firmware type ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dump_firm_type_and_int_freq(type, int_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) printk(KERN_DEBUG "(%x), id %llx, size=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) type, (unsigned long long)id, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) priv->firm[n].type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) priv->firm[n].id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) priv->firm[n].size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) priv->firm[n].int_freq = int_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) p += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (n + 1 != priv->firm_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) printk(KERN_ERR "Firmware file is incomplete!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) goto corrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) header:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) printk(KERN_ERR "Firmware header is incomplete!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) corrupt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) printk(KERN_ERR "Error: firmware file is corrupted!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dprintk(1, "Firmware files loaded.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static int load_scode(struct dvb_frontend *fe, unsigned int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) v4l2_std_id *id, __u16 int_freq, int scode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int pos, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) unsigned char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u8 scode_buf[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u8 indirect_mode[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dprintk(1, "%s called int_freq=%d\n", __func__, int_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (!int_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) pos = seek_firmware(fe, type, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (pos < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) for (pos = 0; pos < priv->firm_size; pos++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if ((priv->firm[pos].int_freq == int_freq) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) (priv->firm[pos].type & HAS_IF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (pos == priv->firm_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) p = priv->firm[pos].ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (priv->firm[pos].size != 12 * 16 || scode >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) p += 12 * scode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (debug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) tuner_info("Loading SCODE for type=");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dump_firm_type_and_int_freq(priv->firm[pos].type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) priv->firm[pos].int_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) printk(KERN_CONT "(%x), id %016llx.\n", priv->firm[pos].type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) (unsigned long long)*id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) scode_buf[0] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) memcpy(&scode_buf[1], p, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Enter direct-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) rc = xc_write_reg(priv, XREG_DIRECTSITTING_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) printk(KERN_ERR "failed to put device into direct mode!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) rc = xc_send_i2c_data(priv, scode_buf, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Even if the send failed, make sure we set back to indirect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) printk(KERN_ERR "Failed to set scode %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Switch back to indirect-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) memset(indirect_mode, 0, sizeof(indirect_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) indirect_mode[4] = 0x88;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) xc_send_i2c_data(priv, indirect_mode, sizeof(indirect_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static int check_firmware(struct dvb_frontend *fe, unsigned int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) v4l2_std_id std, __u16 int_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct firmware_properties new_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) int rc = 0, is_retry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) u16 hwmodel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) v4l2_std_id std0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) u8 hw_major = 0, hw_minor = 0, fw_major = 0, fw_minor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dprintk(1, "%s called\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (!priv->firm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) rc = xc4000_fwupload(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) new_fw.type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) new_fw.id = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) new_fw.std_req = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) new_fw.scode_table = SCODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) new_fw.scode_nr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) new_fw.int_freq = int_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dprintk(1, "checking firmware, user requested type=");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (debug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dump_firm_type(new_fw.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) printk(KERN_CONT "(%x), id %016llx, ", new_fw.type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) (unsigned long long)new_fw.std_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (!int_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) printk(KERN_CONT "scode_tbl ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) printk(KERN_CONT "int_freq %d, ", new_fw.int_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) printk(KERN_CONT "scode_nr %d\n", new_fw.scode_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* No need to reload base firmware if it matches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (priv->cur_fw.type & BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dprintk(1, "BASE firmware not changed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) goto skip_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* Updating BASE - forget about all currently loaded firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) memset(&priv->cur_fw, 0, sizeof(priv->cur_fw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* Reset is needed before loading firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) rc = xc4000_tuner_reset(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* BASE firmwares are all std0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) std0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) rc = load_firmware(fe, BASE, &std0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) printk(KERN_ERR "Error %d while loading base firmware\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* Load INIT1, if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dprintk(1, "Load init1 firmware, if exists\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) rc = load_firmware(fe, BASE | INIT1, &std0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (rc == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) rc = load_firmware(fe, BASE | INIT1, &std0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (rc < 0 && rc != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) tuner_err("Error %d while loading init1 firmware\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) skip_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * No need to reload standard specific firmware if base firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * was not reloaded and requested video standards have not changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (priv->cur_fw.type == (BASE | new_fw.type) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) priv->cur_fw.std_req == std) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dprintk(1, "Std-specific firmware already loaded.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) goto skip_std_specific;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* Reloading std-specific firmware forces a SCODE update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) priv->cur_fw.scode_table = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* Load the standard firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) rc = load_firmware(fe, new_fw.type, &new_fw.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) skip_std_specific:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (priv->cur_fw.scode_table == new_fw.scode_table &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) priv->cur_fw.scode_nr == new_fw.scode_nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) dprintk(1, "SCODE firmware already loaded.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) goto check_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* Load SCODE firmware, if exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) rc = load_scode(fe, new_fw.type | new_fw.scode_table, &new_fw.id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) new_fw.int_freq, new_fw.scode_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (rc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dprintk(1, "load scode failed %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) check_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (xc4000_readreg(priv, XREG_PRODUCT_ID, &hwmodel) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) printk(KERN_ERR "Unable to read tuner registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (xc_get_version(priv, &hw_major, &hw_minor, &fw_major,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) &fw_minor) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) printk(KERN_ERR "Unable to read tuner registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) dprintk(1, "Device is Xceive %d version %d.%d, firmware version %d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) hwmodel, hw_major, hw_minor, fw_major, fw_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* Check firmware version against what we downloaded. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (priv->firm_version != ((fw_major << 8) | fw_minor)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) "Incorrect readback of firmware version %d.%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) fw_major, fw_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Check that the tuner hardware model remains consistent over time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (priv->hwmodel == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) (hwmodel == XC_PRODUCT_ID_XC4000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) hwmodel == XC_PRODUCT_ID_XC4100)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) priv->hwmodel = hwmodel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) priv->hwvers = (hw_major << 8) | hw_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) } else if (priv->hwmodel == 0 || priv->hwmodel != hwmodel ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) priv->hwvers != ((hw_major << 8) | hw_minor)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "Read invalid device hardware information - tuner hung?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) priv->cur_fw = new_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * By setting BASE in cur_fw.type only after successfully loading all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * firmwares, we can:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * 1. Identify that BASE firmware with type=0 has been loaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * 2. Tell whether BASE firmware was just changed the next time through.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) priv->cur_fw.type |= BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) memset(&priv->cur_fw, 0, sizeof(priv->cur_fw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (!is_retry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) is_retry = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dprintk(1, "Retrying firmware load\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (rc == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static void xc_debug_dump(struct xc4000_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) u16 adc_envelope;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) u32 freq_error_hz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) u16 lock_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) u32 hsync_freq_hz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) u16 frame_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) u16 quality;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) u16 signal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) u16 noise = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) u8 hw_majorversion = 0, hw_minorversion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) u8 fw_majorversion = 0, fw_minorversion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) xc_get_adc_envelope(priv, &adc_envelope);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) dprintk(1, "*** ADC envelope (0-1023) = %d\n", adc_envelope);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) xc_get_frequency_error(priv, &freq_error_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) dprintk(1, "*** Frequency error = %d Hz\n", freq_error_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) xc_get_lock_status(priv, &lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) dprintk(1, "*** Lock status (0-Wait, 1-Locked, 2-No-signal) = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) xc_get_version(priv, &hw_majorversion, &hw_minorversion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) &fw_majorversion, &fw_minorversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) dprintk(1, "*** HW: V%02x.%02x, FW: V%02x.%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) hw_majorversion, hw_minorversion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) fw_majorversion, fw_minorversion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (priv->video_standard < XC4000_DTV6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) xc_get_hsync_freq(priv, &hsync_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dprintk(1, "*** Horizontal sync frequency = %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) hsync_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) xc_get_frame_lines(priv, &frame_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dprintk(1, "*** Frame lines = %d\n", frame_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) xc_get_quality(priv, &quality);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dprintk(1, "*** Quality (0:<8dB, 7:>56dB) = %d\n", quality);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) xc_get_signal_level(priv, &signal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dprintk(1, "*** Signal level = -%ddB (%d)\n", signal >> 8, signal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) xc_get_noise_level(priv, &noise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dprintk(1, "*** Noise level = %ddB (%d)\n", noise >> 8, noise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static int xc4000_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) u32 delsys = c->delivery_system;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) u32 bw = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) int ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) dprintk(1, "%s() frequency=%d (Hz)\n", __func__, c->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) switch (delsys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) case SYS_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dprintk(1, "%s() VSB modulation\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) priv->rf_mode = XC_RF_MODE_AIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) priv->freq_offset = 1750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) priv->video_standard = XC4000_DTV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) type = DTV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) case SYS_DVBC_ANNEX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) dprintk(1, "%s() QAM modulation\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) priv->rf_mode = XC_RF_MODE_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) priv->freq_offset = 1750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) priv->video_standard = XC4000_DTV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) type = DTV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) case SYS_DVBT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) dprintk(1, "%s() OFDM\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (bw == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (c->frequency < 400000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) priv->freq_offset = 2250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) priv->freq_offset = 2750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) priv->video_standard = XC4000_DTV7_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) type = DTV78;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) } else if (bw <= 6000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) priv->video_standard = XC4000_DTV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) priv->freq_offset = 1750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) type = DTV6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) } else if (bw <= 7000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) priv->video_standard = XC4000_DTV7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) priv->freq_offset = 2250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) type = DTV7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) priv->video_standard = XC4000_DTV8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) priv->freq_offset = 2750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) type = DTV8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) priv->rf_mode = XC_RF_MODE_AIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) printk(KERN_ERR "xc4000 delivery system not supported!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) priv->freq_hz = c->frequency - priv->freq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dprintk(1, "%s() frequency=%d (compensated)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) __func__, priv->freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* Make sure the correct firmware type is loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (check_firmware(fe, type, 0, priv->if_khz) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) priv->bandwidth = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret = xc_set_signal_source(priv, priv->rf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) printk(KERN_ERR "xc4000: xc_set_signal_source(%d) failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) priv->rf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u16 video_mode, audio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) video_mode = xc4000_standard[priv->video_standard].video_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) audio_mode = xc4000_standard[priv->video_standard].audio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (type == DTV6 && priv->firm_version != 0x0102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) video_mode |= 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) ret = xc_set_tv_standard(priv, video_mode, audio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) printk(KERN_ERR "xc4000: xc_set_tv_standard failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* DJH - do not return when it fails... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /* goto fail; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (xc_write_reg(priv, XREG_D_CODE, 0) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (priv->dvb_amplitude != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (xc_write_reg(priv, XREG_AMPLITUDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) (priv->firm_version != 0x0102 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) priv->dvb_amplitude != 134 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) priv->dvb_amplitude : 132)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (priv->set_smoothedcvbs != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (xc_write_reg(priv, XREG_SMOOTHEDCVBS, 1) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) printk(KERN_ERR "xc4000: setting registers failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* goto fail; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) xc_tune_channel(priv, priv->freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static int xc4000_set_analog_params(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct analog_parameters *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) unsigned int type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) int ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (params->mode == V4L2_TUNER_RADIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dprintk(1, "%s() frequency=%d (in units of 62.5Hz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) __func__, params->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) params->std = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) priv->freq_hz = params->frequency * 125L / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (audio_std & XC4000_AUDIO_STD_INPUT1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) priv->video_standard = XC4000_FM_Radio_INPUT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) type = FM | INPUT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) priv->video_standard = XC4000_FM_Radio_INPUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) type = FM | INPUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) goto tune_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dprintk(1, "%s() frequency=%d (in units of 62.5khz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) __func__, params->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /* params->frequency is in units of 62.5khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) priv->freq_hz = params->frequency * 62500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) params->std &= V4L2_STD_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /* if std is not defined, choose one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (!params->std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) params->std = V4L2_STD_PAL_BG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (audio_std & XC4000_AUDIO_STD_MONO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) type = MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (params->std & V4L2_STD_MN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) params->std = V4L2_STD_MN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (audio_std & XC4000_AUDIO_STD_MONO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) priv->video_standard = XC4000_MN_NTSC_PAL_Mono;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) } else if (audio_std & XC4000_AUDIO_STD_A2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) params->std |= V4L2_STD_A2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) priv->video_standard = XC4000_MN_NTSC_PAL_A2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) params->std |= V4L2_STD_BTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) priv->video_standard = XC4000_MN_NTSC_PAL_BTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) goto tune_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (params->std & V4L2_STD_PAL_BG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) params->std = V4L2_STD_PAL_BG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (audio_std & XC4000_AUDIO_STD_MONO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) priv->video_standard = XC4000_BG_PAL_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) } else if (!(audio_std & XC4000_AUDIO_STD_A2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (!(audio_std & XC4000_AUDIO_STD_B)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) params->std |= V4L2_STD_NICAM_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) priv->video_standard = XC4000_BG_PAL_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) params->std |= V4L2_STD_NICAM_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) priv->video_standard = XC4000_BG_PAL_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (!(audio_std & XC4000_AUDIO_STD_B)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) params->std |= V4L2_STD_A2_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) priv->video_standard = XC4000_BG_PAL_A2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) params->std |= V4L2_STD_A2_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) priv->video_standard = XC4000_BG_PAL_A2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) goto tune_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (params->std & V4L2_STD_PAL_I) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* default to NICAM audio standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) params->std = V4L2_STD_PAL_I | V4L2_STD_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (audio_std & XC4000_AUDIO_STD_MONO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) priv->video_standard = XC4000_I_PAL_NICAM_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) priv->video_standard = XC4000_I_PAL_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) goto tune_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (params->std & V4L2_STD_PAL_DK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) params->std = V4L2_STD_PAL_DK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (audio_std & XC4000_AUDIO_STD_MONO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) priv->video_standard = XC4000_DK_PAL_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) } else if (audio_std & XC4000_AUDIO_STD_A2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) params->std |= V4L2_STD_A2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) priv->video_standard = XC4000_DK_PAL_A2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) params->std |= V4L2_STD_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) priv->video_standard = XC4000_DK_PAL_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) goto tune_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (params->std & V4L2_STD_SECAM_DK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /* default to A2 audio standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) params->std = V4L2_STD_SECAM_DK | V4L2_STD_A2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (audio_std & XC4000_AUDIO_STD_L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) priv->video_standard = XC4000_DK_SECAM_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) } else if (audio_std & XC4000_AUDIO_STD_MONO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) priv->video_standard = XC4000_DK_SECAM_A2MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) } else if (audio_std & XC4000_AUDIO_STD_K3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) params->std |= V4L2_STD_SECAM_K3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) priv->video_standard = XC4000_DK_SECAM_A2LDK3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) priv->video_standard = XC4000_DK_SECAM_A2DK1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) goto tune_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (params->std & V4L2_STD_SECAM_L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* default to NICAM audio standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) params->std = V4L2_STD_SECAM_L | V4L2_STD_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) priv->video_standard = XC4000_L_SECAM_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) goto tune_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (params->std & V4L2_STD_SECAM_LC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* default to NICAM audio standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) params->std = V4L2_STD_SECAM_LC | V4L2_STD_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) priv->video_standard = XC4000_LC_SECAM_NICAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) goto tune_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) tune_channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) /* FIXME: it could be air. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) priv->rf_mode = XC_RF_MODE_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (check_firmware(fe, type, params->std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) xc4000_standard[priv->video_standard].int_freq) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ret = xc_set_signal_source(priv, priv->rf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) "xc4000: xc_set_signal_source(%d) failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) priv->rf_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) u16 video_mode, audio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) video_mode = xc4000_standard[priv->video_standard].video_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) audio_mode = xc4000_standard[priv->video_standard].audio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (priv->video_standard < XC4000_BG_PAL_A2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (type & NOGD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) video_mode &= 0xFF7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) } else if (priv->video_standard < XC4000_I_PAL_NICAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (priv->firm_version == 0x0102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) video_mode &= 0xFEFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (audio_std & XC4000_AUDIO_STD_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) video_mode |= 0x0080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ret = xc_set_tv_standard(priv, video_mode, audio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) printk(KERN_ERR "xc4000: xc_set_tv_standard failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (xc_write_reg(priv, XREG_D_CODE, 0) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (xc_write_reg(priv, XREG_AMPLITUDE, 1) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (priv->set_smoothedcvbs != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (xc_write_reg(priv, XREG_SMOOTHEDCVBS, 1) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) printk(KERN_ERR "xc4000: setting registers failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) xc_tune_channel(priv, priv->freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static int xc4000_get_signal(struct dvb_frontend *fe, u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) u16 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) rc = xc4000_readreg(priv, XREG_SIGNAL_LEVEL, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) goto ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* Information from real testing of DVB-T and radio part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) coefficient for one dB is 0xff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) tuner_dbg("Signal strength: -%ddB (%05d)\n", value >> 8, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /* all known digital modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if ((priv->video_standard == XC4000_DTV6) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) (priv->video_standard == XC4000_DTV7) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) (priv->video_standard == XC4000_DTV7_8) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) (priv->video_standard == XC4000_DTV8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) goto digital;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* Analog mode has NOISE LEVEL important, signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) depends only on gain of antenna and amplifiers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) but it doesn't tell anything about real quality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) of reception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) rc = xc4000_readreg(priv, XREG_NOISE_LEVEL, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) tuner_dbg("Noise level: %ddB (%05d)\n", value >> 8, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* highest noise level: 32dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (value >= 0x2000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) value = (~value << 3) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) goto ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* Digital mode has SIGNAL LEVEL important and real
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) noise level is stored in demodulator registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) digital:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* best signal: -50dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (value <= 0x3200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) value = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /* minimum: -114dB - should be 0x7200 but real zero is 0x713A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) } else if (value >= 0x713A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) value = ~(value - 0x3200) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) *strength = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static int xc4000_get_frequency(struct dvb_frontend *fe, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) *freq = priv->freq_hz + priv->freq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (debug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if ((priv->cur_fw.type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) & (BASE | FM | DTV6 | DTV7 | DTV78 | DTV8)) == BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) u16 snr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (xc4000_readreg(priv, XREG_SNR, &snr) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) dprintk(1, "%s() freq = %u, SNR = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) __func__, *freq, snr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static int xc4000_get_bandwidth(struct dvb_frontend *fe, u32 *bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) *bw = priv->bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static int xc4000_get_status(struct dvb_frontend *fe, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) u16 lock_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (priv->cur_fw.type & BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) xc_get_lock_status(priv, &lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) *status = (lock_status == 1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) TUNER_STATUS_LOCKED | TUNER_STATUS_STEREO : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (priv->cur_fw.type & (DTV6 | DTV7 | DTV78 | DTV8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) *status &= (~TUNER_STATUS_STEREO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) dprintk(2, "%s() lock_status = %d\n", __func__, lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) static int xc4000_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) /* Avoid firmware reload on slow devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if ((no_poweroff == 2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) (no_poweroff == 0 && priv->default_pm != 0)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) (priv->cur_fw.type & BASE) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* force reset and firmware reload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) priv->cur_fw.type = XC_POWERED_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (xc_write_reg(priv, XREG_POWER_DOWN, 0) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) "xc4000: %s() unable to shutdown tuner\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static int xc4000_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static void xc4000_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) struct xc4000_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) mutex_lock(&xc4000_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) hybrid_tuner_release_state(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) mutex_unlock(&xc4000_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) static const struct dvb_tuner_ops xc4000_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .name = "Xceive XC4000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .frequency_min_hz = 1 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .frequency_max_hz = 1023 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .frequency_step_hz = 50 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .release = xc4000_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .init = xc4000_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .sleep = xc4000_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .set_params = xc4000_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .set_analog_params = xc4000_set_analog_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .get_frequency = xc4000_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .get_rf_strength = xc4000_get_signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .get_bandwidth = xc4000_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .get_status = xc4000_get_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) struct dvb_frontend *xc4000_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct xc4000_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct xc4000_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) int instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) u16 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) dprintk(1, "%s(%d-%04x)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) i2c ? i2c_adapter_id(i2c) : -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) cfg ? cfg->i2c_address : -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) mutex_lock(&xc4000_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) instance = hybrid_tuner_request_state(struct xc4000_priv, priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) hybrid_tuner_instance_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) i2c, cfg->i2c_address, "xc4000");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) switch (instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* new tuner instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) priv->bandwidth = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /* set default configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) priv->if_khz = 4560;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) priv->default_pm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) priv->dvb_amplitude = 134;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) priv->set_smoothedcvbs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) /* existing tuner instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (cfg->if_khz != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) /* copy configuration if provided by the caller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) priv->if_khz = cfg->if_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) priv->default_pm = cfg->default_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) priv->dvb_amplitude = cfg->dvb_amplitude;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) priv->set_smoothedcvbs = cfg->set_smoothedcvbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* Check if firmware has been loaded. It is possible that another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) instance of the driver has loaded the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (instance == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (xc4000_readreg(priv, XREG_PRODUCT_ID, &id) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) id = ((priv->cur_fw.type & BASE) != 0 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) priv->hwmodel : XC_PRODUCT_ID_FW_NOT_LOADED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) case XC_PRODUCT_ID_XC4000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) case XC_PRODUCT_ID_XC4100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) "xc4000: Successfully identified at address 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) cfg->i2c_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) "xc4000: Firmware has been loaded previously\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) case XC_PRODUCT_ID_FW_NOT_LOADED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) "xc4000: Successfully identified at address 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) cfg->i2c_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) "xc4000: Firmware has not been loaded previously\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) "xc4000: Device not found at addr 0x%02x (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) cfg->i2c_address, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) mutex_unlock(&xc4000_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) memcpy(&fe->ops.tuner_ops, &xc4000_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (instance == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) ret = xc4000_fwupload(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) goto fail2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) mutex_unlock(&xc4000_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) fail2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) xc4000_release(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) EXPORT_SYMBOL(xc4000_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) MODULE_AUTHOR("Steven Toth, Davide Ferri");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) MODULE_DESCRIPTION("Xceive xc4000 silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) MODULE_FIRMWARE(XC4000_DEFAULT_FIRMWARE_NEW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) MODULE_FIRMWARE(XC4000_DEFAULT_FIRMWARE);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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