^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (c) 2005 Hartmut Hackmann
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) 2007 Michael Krufky
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "tda827x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) if (debug) printk(KERN_DEBUG "tda827x: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct tda827x_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct i2c_adapter *i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct tda827x_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int sgIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned char lpsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void tda827x_set_std(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct analog_parameters *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) char *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) priv->lpsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (params->std & V4L2_STD_MN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) priv->sgIF = 92;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) priv->lpsel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) mode = "MN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) } else if (params->std & V4L2_STD_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) priv->sgIF = 108;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mode = "B";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) } else if (params->std & V4L2_STD_GH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) priv->sgIF = 124;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mode = "GH";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) } else if (params->std & V4L2_STD_PAL_I) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) priv->sgIF = 124;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mode = "I";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } else if (params->std & V4L2_STD_DK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) priv->sgIF = 124;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mode = "DK";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) } else if (params->std & V4L2_STD_SECAM_L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) priv->sgIF = 124;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mode = "L";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } else if (params->std & V4L2_STD_SECAM_LC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) priv->sgIF = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) mode = "LC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) priv->sgIF = 124;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mode = "xx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (params->mode == V4L2_TUNER_RADIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) priv->sgIF = 88; /* if frequency is 5.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) dprintk("setting tda827x to radio FM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dprintk("setting tda827x to system %s\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct tda827x_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 lomax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 spd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 bs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 gc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 div1p5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct tda827x_data tda827x_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { .lomax = 62000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { .lomax = 66000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { .lomax = 76000000, .spd = 3, .bs = 1, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { .lomax = 84000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { .lomax = 93000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .lomax = 98000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { .lomax = 109000000, .spd = 3, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { .lomax = 123000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { .lomax = 133000000, .spd = 2, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { .lomax = 151000000, .spd = 2, .bs = 1, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { .lomax = 154000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { .lomax = 181000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 0, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { .lomax = 185000000, .spd = 2, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { .lomax = 217000000, .spd = 2, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { .lomax = 244000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { .lomax = 265000000, .spd = 1, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { .lomax = 302000000, .spd = 1, .bs = 1, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { .lomax = 324000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { .lomax = 370000000, .spd = 1, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { .lomax = 454000000, .spd = 1, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { .lomax = 493000000, .spd = 0, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { .lomax = 530000000, .spd = 0, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { .lomax = 554000000, .spd = 0, .bs = 1, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { .lomax = 604000000, .spd = 0, .bs = 1, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .lomax = 696000000, .spd = 0, .bs = 2, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { .lomax = 740000000, .spd = 0, .bs = 2, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .lomax = 820000000, .spd = 0, .bs = 3, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { .lomax = 865000000, .spd = 0, .bs = 3, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { .lomax = 0, .spd = 0, .bs = 0, .bp = 0, .cp = 0, .gc3 = 0, .div1p5 = 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int tuner_transfer(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) rc = i2c_transfer(priv->i2c_adap, msg, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (rc >= 0 && rc != size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int tda827xo_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 buf[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .buf = buf, .len = sizeof(buf) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int i, tuner_freq, if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (c->bandwidth_hz == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if_freq = 5000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } else if (c->bandwidth_hz <= 6000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if_freq = 4000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) } else if (c->bandwidth_hz <= 7000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if_freq = 4500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) } else { /* 8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if_freq = 5000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) tuner_freq = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) while (tda827x_table[i].lomax < tuner_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (tda827x_table[i + 1].lomax == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tuner_freq += if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) N = ((tuner_freq + 125000) / 250000) << (tda827x_table[i].spd + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) buf[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) buf[1] = (N>>8) | 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) buf[2] = N & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) buf[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) buf[4] = 0x52;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) buf[5] = (tda827x_table[i].spd << 6) + (tda827x_table[i].div1p5 << 5) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) (tda827x_table[i].bs << 3) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) tda827x_table[i].bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) buf[6] = (tda827x_table[i].gc3 << 4) + 0x8f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) buf[7] = 0xbf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) buf[8] = 0x2a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) buf[9] = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) buf[10] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) buf[11] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) buf[12] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) buf[13] = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) msg.len = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* correct CP value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) buf[0] = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) buf[1] = 0x50 + tda827x_table[i].cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) msg.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) priv->frequency = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) priv->bandwidth = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) printk(KERN_ERR "%s: could not write to tuner at addr: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __func__, priv->i2c_addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int tda827xo_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static u8 buf[] = { 0x30, 0xd0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .buf = buf, .len = sizeof(buf) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (priv->cfg && priv->cfg->sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) priv->cfg->sleep(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int tda827xo_set_analog_params(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct analog_parameters *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned char tuner_reg[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned char reg2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned int freq = params->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) tda827x_set_std(fe, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (params->mode == V4L2_TUNER_RADIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) freq = freq / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) N = freq + priv->sgIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) while (tda827x_table[i].lomax < N * 62500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (tda827x_table[i + 1].lomax == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) N = N << tda827x_table[i].spd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) tuner_reg[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) tuner_reg[1] = (unsigned char)(N>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) tuner_reg[2] = (unsigned char) N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) tuner_reg[3] = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) tuner_reg[4] = 0x52 + (priv->lpsel << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) tuner_reg[5] = (tda827x_table[i].spd << 6) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) (tda827x_table[i].div1p5 << 5) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) (tda827x_table[i].bs << 3) + tda827x_table[i].bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) tuner_reg[6] = 0x8f + (tda827x_table[i].gc3 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) tuner_reg[7] = 0x8f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) msg.buf = tuner_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) msg.len = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) msg.buf = reg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) msg.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) reg2[0] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) reg2[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) reg2[0] = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) reg2[1] = 0xbf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) reg2[0] = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) reg2[1] = tuner_reg[4] + 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) reg2[0] = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) reg2[1] = tuner_reg[4] + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) reg2[0] = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) reg2[1] = tuner_reg[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) msleep(550);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) reg2[0] = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) reg2[1] = (tuner_reg[4] & 0xfc) + tda827x_table[i].cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) reg2[0] = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) reg2[1] = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) reg2[0] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) reg2[1] = 0x08; /* Vsync en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) priv->frequency = params->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void tda827xo_agcf(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned char data[] = { 0x80, 0x0c };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .buf = data, .len = 2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct tda827xa_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 lomax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 svco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u8 spd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 sbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 gc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct tda827xa_data tda827xa_dvbt[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { .lomax = 56875000, .svco = 3, .spd = 4, .scr = 0, .sbs = 0, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { .lomax = 67250000, .svco = 0, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { .lomax = 81250000, .svco = 1, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { .lomax = 97500000, .svco = 2, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { .lomax = 113750000, .svco = 3, .spd = 3, .scr = 0, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { .lomax = 134500000, .svco = 0, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { .lomax = 154000000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { .lomax = 162500000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { .lomax = 183000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { .lomax = 195000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { .lomax = 227500000, .svco = 3, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { .lomax = 269000000, .svco = 0, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { .lomax = 290000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { .lomax = 325000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { .lomax = 390000000, .svco = 2, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { .lomax = 455000000, .svco = 3, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { .lomax = 520000000, .svco = 0, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { .lomax = 538000000, .svco = 0, .spd = 0, .scr = 1, .sbs = 3, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { .lomax = 550000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { .lomax = 620000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { .lomax = 650000000, .svco = 1, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { .lomax = 700000000, .svco = 2, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { .lomax = 780000000, .svco = 2, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { .lomax = 820000000, .svco = 3, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { .lomax = 870000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { .lomax = 911000000, .svco = 3, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { .lomax = 0, .svco = 0, .spd = 0, .scr = 0, .sbs = 0, .gc3 = 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct tda827xa_data tda827xa_dvbc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { .lomax = 50125000, .svco = 2, .spd = 4, .scr = 2, .sbs = 0, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { .lomax = 58500000, .svco = 3, .spd = 4, .scr = 2, .sbs = 0, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { .lomax = 69250000, .svco = 0, .spd = 3, .scr = 2, .sbs = 0, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { .lomax = 83625000, .svco = 1, .spd = 3, .scr = 2, .sbs = 0, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { .lomax = 97500000, .svco = 2, .spd = 3, .scr = 2, .sbs = 0, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { .lomax = 100250000, .svco = 2, .spd = 3, .scr = 2, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { .lomax = 117000000, .svco = 3, .spd = 3, .scr = 2, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { .lomax = 138500000, .svco = 0, .spd = 2, .scr = 2, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { .lomax = 167250000, .svco = 1, .spd = 2, .scr = 2, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { .lomax = 187000000, .svco = 2, .spd = 2, .scr = 2, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { .lomax = 200500000, .svco = 2, .spd = 2, .scr = 2, .sbs = 2, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { .lomax = 234000000, .svco = 3, .spd = 2, .scr = 2, .sbs = 2, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { .lomax = 277000000, .svco = 0, .spd = 1, .scr = 2, .sbs = 2, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { .lomax = 325000000, .svco = 1, .spd = 1, .scr = 2, .sbs = 2, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { .lomax = 334500000, .svco = 1, .spd = 1, .scr = 2, .sbs = 3, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { .lomax = 401000000, .svco = 2, .spd = 1, .scr = 2, .sbs = 3, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { .lomax = 468000000, .svco = 3, .spd = 1, .scr = 2, .sbs = 3, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { .lomax = 535000000, .svco = 0, .spd = 0, .scr = 1, .sbs = 3, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { .lomax = 554000000, .svco = 0, .spd = 0, .scr = 2, .sbs = 3, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { .lomax = 638000000, .svco = 1, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { .lomax = 669000000, .svco = 1, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { .lomax = 720000000, .svco = 2, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { .lomax = 802000000, .svco = 2, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { .lomax = 835000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { .lomax = 885000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { .lomax = 911000000, .svco = 3, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { .lomax = 0, .svco = 0, .spd = 0, .scr = 0, .sbs = 0, .gc3 = 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static struct tda827xa_data tda827xa_analog[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { .lomax = 56875000, .svco = 3, .spd = 4, .scr = 0, .sbs = 0, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { .lomax = 67250000, .svco = 0, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { .lomax = 81250000, .svco = 1, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { .lomax = 97500000, .svco = 2, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { .lomax = 113750000, .svco = 3, .spd = 3, .scr = 0, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { .lomax = 134500000, .svco = 0, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { .lomax = 154000000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { .lomax = 162500000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { .lomax = 183000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { .lomax = 195000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { .lomax = 227500000, .svco = 3, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { .lomax = 269000000, .svco = 0, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { .lomax = 325000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { .lomax = 390000000, .svco = 2, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { .lomax = 455000000, .svco = 3, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { .lomax = 520000000, .svco = 0, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { .lomax = 538000000, .svco = 0, .spd = 0, .scr = 1, .sbs = 3, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { .lomax = 554000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { .lomax = 620000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { .lomax = 650000000, .svco = 1, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { .lomax = 700000000, .svco = 2, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { .lomax = 780000000, .svco = 2, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { .lomax = 820000000, .svco = 3, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { .lomax = 870000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { .lomax = 911000000, .svco = 3, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { .lomax = 0, .svco = 0, .spd = 0, .scr = 0, .sbs = 0, .gc3 = 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int tda827xa_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static u8 buf[] = { 0x30, 0x90 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .buf = buf, .len = sizeof(buf) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (priv->cfg && priv->cfg->sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) priv->cfg->sleep(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void tda827xa_lna_gain(struct dvb_frontend *fe, int high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct analog_parameters *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned char buf[] = {0x22, 0x01};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int gp_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct i2c_msg msg = { .flags = 0, .buf = buf, .len = sizeof(buf) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (NULL == priv->cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dprintk("tda827x_config not defined, cannot set LNA gain!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) msg.addr = priv->cfg->switch_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (priv->cfg->config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dprintk("setting LNA to high gain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dprintk("setting LNA to low gain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) switch (priv->cfg->config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case TDA8290_LNA_OFF: /* no LNA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case TDA8290_LNA_GP0_HIGH_ON: /* switch is GPIO 0 of tda8290 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case TDA8290_LNA_GP0_HIGH_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (params == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) gp_func = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* turn Vsync on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) gp_func = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (params->std & V4L2_STD_MN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (fe->callback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) fe->callback(priv->i2c_adap->algo_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) DVB_FRONTEND_COMPONENT_TUNER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) gp_func, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) buf[1] = high ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (priv->cfg->config == TDA8290_LNA_GP0_HIGH_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) buf[1] = high ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case TDA8290_LNA_ON_BRIDGE: /* switch with GPIO of saa713x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (fe->callback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) fe->callback(priv->i2c_adap->algo_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) DVB_FRONTEND_COMPONENT_TUNER, 0, high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int tda827xa_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct tda827xa_data *frequency_map = tda827xa_dvbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u8 buf[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .buf = buf, .len = sizeof(buf) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int i, tuner_freq, if_freq, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) tda827xa_lna_gain(fe, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (c->bandwidth_hz == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if_freq = 5000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) } else if (c->bandwidth_hz <= 6000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if_freq = 4000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) } else if (c->bandwidth_hz <= 7000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if_freq = 4500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) } else { /* 8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if_freq = 5000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) tuner_freq = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) switch (c->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case SYS_DVBC_ANNEX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dprintk("%s select tda827xa_dvbc\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) frequency_map = tda827xa_dvbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) while (frequency_map[i].lomax < tuner_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (frequency_map[i + 1].lomax == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) tuner_freq += if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) N = ((tuner_freq + 31250) / 62500) << frequency_map[i].spd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) buf[0] = 0; // subaddress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) buf[1] = N >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) buf[2] = N & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) buf[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) buf[4] = 0x16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) buf[5] = (frequency_map[i].spd << 5) + (frequency_map[i].svco << 3) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) frequency_map[i].sbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) buf[6] = 0x4b + (frequency_map[i].gc3 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) buf[7] = 0x1c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) buf[8] = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) buf[9] = 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) buf[10] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) msg.len = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) buf[0] = 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) buf[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) buf[2] = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) buf[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) buf[4] = 0x59; // lpsel, for 6MHz + 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) msg.len = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) buf[0] = 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) buf[1] = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) msg.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) msleep(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) msg.flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) buf[1] >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dprintk("tda8275a AGC2 gain is: %d\n", buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if ((buf[1]) < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) tda827xa_lna_gain(fe, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) buf[0] = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) buf[1] = 0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) buf[0] = 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) buf[1] = 0x99; // lpsel, for 6MHz + 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) buf[0] = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) buf[1] = 0x3c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* correct CP value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) buf[0] = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) buf[1] = 0x10 + frequency_map[i].scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) msleep(163);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) buf[0] = 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) buf[1] = 0x39; // lpsel, for 6MHz + 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) msleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* freeze AGC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) buf[0] = 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) buf[1] = 0x4f + (frequency_map[i].gc3 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) priv->frequency = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) priv->bandwidth = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) printk(KERN_ERR "%s: could not write to tuner at addr: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) __func__, priv->i2c_addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int tda827xa_set_analog_params(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct analog_parameters *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned char tuner_reg[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u32 N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .buf = tuner_reg, .len = sizeof(tuner_reg) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) unsigned int freq = params->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) tda827x_set_std(fe, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) tda827xa_lna_gain(fe, 1, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (params->mode == V4L2_TUNER_RADIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) freq = freq / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) N = freq + priv->sgIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) while (tda827xa_analog[i].lomax < N * 62500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (tda827xa_analog[i + 1].lomax == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) N = N << tda827xa_analog[i].spd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) tuner_reg[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) tuner_reg[1] = (unsigned char)(N>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) tuner_reg[2] = (unsigned char) N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) tuner_reg[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) tuner_reg[4] = 0x16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) tuner_reg[5] = (tda827xa_analog[i].spd << 5) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) (tda827xa_analog[i].svco << 3) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) tda827xa_analog[i].sbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) tuner_reg[6] = 0x8b + (tda827xa_analog[i].gc3 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) tuner_reg[7] = 0x1c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) tuner_reg[8] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) tuner_reg[9] = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) tuner_reg[10] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) msg.len = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) tuner_reg[0] = 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) tuner_reg[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) tuner_reg[2] = 0xe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) tuner_reg[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) tuner_reg[4] = 0x99 + (priv->lpsel << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) msg.len = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) tuner_reg[0] = 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) tuner_reg[1] = 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) msg.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) tuner_reg[0] = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) tuner_reg[1] = 0x10 + tda827xa_analog[i].scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) msg.flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) tuner_reg[1] >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dprintk("AGC2 gain is: %d\n", tuner_reg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (tuner_reg[1] < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) tda827xa_lna_gain(fe, 0, params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) tuner_reg[0] = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) tuner_reg[1] = 0x3c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) msleep(163);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) tuner_reg[0] = 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) tuner_reg[1] = 0x8f + (tda827xa_analog[i].gc3 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) tuner_reg[0] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) tuner_reg[1] = 0x28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) tuner_reg[0] = 0xb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) tuner_reg[1] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) tuner_reg[0] = 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) tuner_reg[1] = 0x19 + (priv->lpsel << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) priv->frequency = params->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static void tda827xa_agcf(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) unsigned char data[] = {0x80, 0x2c};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct i2c_msg msg = {.addr = priv->i2c_addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .buf = data, .len = 2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static void tda827x_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) kfree(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static int tda827x_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) *frequency = priv->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int tda827x_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) *bandwidth = priv->bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static int tda827x_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (priv->cfg && priv->cfg->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) priv->cfg->init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int tda827x_probe_version(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int tda827x_initial_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = tda827x_probe_version(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return fe->ops.tuner_ops.init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int tda827x_initial_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = tda827x_probe_version(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return fe->ops.tuner_ops.sleep(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const struct dvb_tuner_ops tda827xo_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .name = "Philips TDA827X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .frequency_min_hz = 55 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .frequency_max_hz = 860 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .frequency_step_hz = 250 * kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .release = tda827x_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .init = tda827x_initial_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .sleep = tda827x_initial_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .set_params = tda827xo_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .set_analog_params = tda827xo_set_analog_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .get_frequency = tda827x_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .get_bandwidth = tda827x_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static const struct dvb_tuner_ops tda827xa_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .name = "Philips TDA827XA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .frequency_min_hz = 44 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .frequency_max_hz = 906 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .frequency_step_hz = 62500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .release = tda827x_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .init = tda827x_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .sleep = tda827xa_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .set_params = tda827xa_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .set_analog_params = tda827xa_set_analog_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .get_frequency = tda827x_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .get_bandwidth = tda827x_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int tda827x_probe_version(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct tda827x_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .buf = &data, .len = 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) rc = tuner_transfer(fe, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) printk("%s: could not read from tuner at addr: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) __func__, msg.addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if ((data & 0x3c) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dprintk("tda827x tuner found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) fe->ops.tuner_ops.init = tda827x_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) fe->ops.tuner_ops.sleep = tda827xo_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (priv->cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) priv->cfg->agcf = tda827xo_agcf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dprintk("tda827xa tuner found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) memcpy(&fe->ops.tuner_ops, &tda827xa_tuner_ops, sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (priv->cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) priv->cfg->agcf = tda827xa_agcf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct dvb_frontend *tda827x_attach(struct dvb_frontend *fe, int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct tda827x_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct tda827x_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dprintk("%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) priv = kzalloc(sizeof(struct tda827x_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) priv->i2c_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) priv->i2c_adap = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) priv->cfg = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) memcpy(&fe->ops.tuner_ops, &tda827xo_tuner_ops, sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dprintk("type set to %s\n", fe->ops.tuner_ops.info.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) EXPORT_SYMBOL_GPL(tda827x_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) MODULE_DESCRIPTION("DVB TDA827x driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) MODULE_AUTHOR("Hartmut Hackmann <hartmut.hackmann@t-online.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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