^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "tda18271-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "tda8290.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) int tda18271_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) module_param_named(debug, tda18271_debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) MODULE_PARM_DESC(debug, "set debug level (info=1, map=2, reg=4, adv=8, cal=16 (or-able))");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static int tda18271_cal_on_startup = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) module_param_named(cal, tda18271_cal_on_startup, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MODULE_PARM_DESC(cal, "perform RF tracking filter calibration on startup");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static DEFINE_MUTEX(tda18271_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static LIST_HEAD(hybrid_tuner_instance_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*---------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int tda18271_toggle_output(struct dvb_frontend *fe, int standby)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int ret = tda18271_set_standby_mode(fe, standby ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) priv->output_opt & TDA18271_OUTPUT_LT_OFF ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) priv->output_opt & TDA18271_OUTPUT_XT_OFF ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) tda_dbg("%s mode: xtal oscillator %s, slave tuner loop through %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) standby ? "standby" : "active",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) priv->output_opt & TDA18271_OUTPUT_XT_OFF ? "off" : "on",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) priv->output_opt & TDA18271_OUTPUT_LT_OFF ? "off" : "on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*---------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static inline int charge_pump_source(struct dvb_frontend *fe, int force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return tda18271_charge_pump_source(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) (priv->role == TDA18271_SLAVE) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) TDA18271_CAL_PLL :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) TDA18271_MAIN_PLL, force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline void tda18271_set_if_notch(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) switch (priv->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case TDA18271_ANALOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) regs[R_MPD] &= ~0x80; /* IF notch = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case TDA18271_DIGITAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) regs[R_MPD] |= 0x80; /* IF notch = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int tda18271_channel_configuration(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct tda18271_std_map_item *map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 freq, u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* update TV broadcast parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* set standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) regs[R_EP3] &= ~0x1f; /* clear std bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) regs[R_EP3] |= (map->agc_mode << 3) | map->std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (priv->id == TDA18271HDC2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* set rfagc to high speed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) regs[R_EP3] &= ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* set cal mode to normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) regs[R_EP4] &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* update IF output level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regs[R_EP4] &= ~0x1c; /* clear if level bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) regs[R_EP4] |= (map->if_lvl << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* update FM_RFn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) regs[R_EP4] &= ~0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) regs[R_EP4] |= map->fm_rfn << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* update rf top / if top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) regs[R_EB22] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) regs[R_EB22] |= map->rfagc_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = tda18271_write_regs(fe, R_EB22, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* disable Power Level Indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) regs[R_EP1] |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* make sure thermometer is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regs[R_TM] &= ~0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* frequency dependent parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tda18271_calc_ir_measure(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) tda18271_calc_bp_filter(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) tda18271_calc_rf_band(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) tda18271_calc_gain_taper(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* dual tuner and agc1 extra configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) switch (priv->role) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case TDA18271_MASTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regs[R_EB1] |= 0x04; /* main vco */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case TDA18271_SLAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) regs[R_EB1] &= ~0x04; /* cal vco */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* agc1 always active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) regs[R_EB1] &= ~0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* agc1 has priority on agc2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) regs[R_EB1] &= ~0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = tda18271_write_regs(fe, R_EB1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) N = map->if_freq * 1000 + freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) switch (priv->role) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case TDA18271_MASTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tda18271_calc_main_pll(fe, N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) tda18271_set_if_notch(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) tda18271_write_regs(fe, R_MPD, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case TDA18271_SLAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tda18271_calc_cal_pll(fe, N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) tda18271_write_regs(fe, R_CPD, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) regs[R_MPD] = regs[R_CPD] & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) tda18271_set_if_notch(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) tda18271_write_regs(fe, R_MPD, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = tda18271_write_regs(fe, R_TM, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* force charge pump source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) charge_pump_source(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* return pll to normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) charge_pump_source(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (priv->id == TDA18271HDC2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* set rfagc to normal speed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (map->fm_rfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) regs[R_EP3] &= ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) regs[R_EP3] |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = tda18271_write_regs(fe, R_EP3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int tda18271_read_thermometer(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* switch thermometer on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) regs[R_TM] |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) tda18271_write_regs(fe, R_TM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* read thermometer info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tda18271_read_regs(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if ((((regs[R_TM] & 0x0f) == 0x00) && ((regs[R_TM] & 0x20) == 0x20)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) (((regs[R_TM] & 0x0f) == 0x08) && ((regs[R_TM] & 0x20) == 0x00))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if ((regs[R_TM] & 0x20) == 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) regs[R_TM] &= ~0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) regs[R_TM] |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tda18271_write_regs(fe, R_TM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) msleep(10); /* temperature sensing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* read thermometer info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) tda18271_read_regs(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tm = tda18271_lookup_thermometer(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* switch thermometer off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) regs[R_TM] &= ~0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) tda18271_write_regs(fe, R_TM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* set CAL mode to normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) regs[R_EP4] &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tda18271_write_regs(fe, R_EP4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u8 tm_current, dc_over_dt, rf_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) s32 rfcal_comp, approx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = tda18271_set_standby_mode(fe, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* read die current temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) tm_current = tda18271_read_thermometer(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* frequency dependent parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) tda18271_calc_rf_cal(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) rf_tab = regs[R_EB14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) i = tda18271_lookup_rf_band(fe, &freq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (tda_fail(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if ((0 == map[i].rf3) || (freq / 1000 < map[i].rf2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) approx = map[i].rf_a1 * (s32)(freq / 1000 - map[i].rf1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) map[i].rf_b1 + rf_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) approx = map[i].rf_a2 * (s32)(freq / 1000 - map[i].rf2) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) map[i].rf_b2 + rf_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (approx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) approx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (approx > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) approx = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tda18271_lookup_map(fe, RF_CAL_DC_OVER_DT, &freq, &dc_over_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* calculate temperature compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rfcal_comp = dc_over_dt * (s32)(tm_current - priv->tm_rfcal) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) regs[R_EB14] = (unsigned char)(approx + rfcal_comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = tda18271_write_regs(fe, R_EB14, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int tda18271_por(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* power up detector 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) regs[R_EB12] &= ~0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = tda18271_write_regs(fe, R_EB12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) regs[R_EB18] &= ~0x80; /* turn agc1 loop on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = tda18271_write_regs(fe, R_EB18, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) regs[R_EB21] |= 0x03; /* set agc2_gain to -6 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* POR mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = tda18271_set_standby_mode(fe, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* disable 1.5 MHz low pass filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) regs[R_EB23] &= ~0x04; /* forcelp_fc2_en = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) regs[R_EB23] &= ~0x02; /* XXX: lp_fc[2] = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = tda18271_write_regs(fe, R_EB21, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int tda18271_calibrate_rf(struct dvb_frontend *fe, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* set CAL mode to normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) regs[R_EP4] &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) tda18271_write_regs(fe, R_EP4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* switch off agc1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) regs[R_EP3] |= 0x40; /* sm_lt = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) regs[R_EB18] |= 0x03; /* set agc1_gain to 15 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) tda18271_write_regs(fe, R_EB18, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* frequency dependent parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) tda18271_calc_bp_filter(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) tda18271_calc_gain_taper(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) tda18271_calc_rf_band(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tda18271_calc_km(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) tda18271_write_regs(fe, R_EP1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) tda18271_write_regs(fe, R_EB13, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* main pll charge pump source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* cal pll charge pump source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) tda18271_charge_pump_source(fe, TDA18271_CAL_PLL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* force dcdc converter to 0 V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) regs[R_EB14] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) tda18271_write_regs(fe, R_EB14, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* disable plls lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) regs[R_EB20] &= ~0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) tda18271_write_regs(fe, R_EB20, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* set CAL mode to RF tracking filter calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) regs[R_EP4] |= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) tda18271_write_regs(fe, R_EP4, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* set the internal calibration signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) N = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) tda18271_calc_cal_pll(fe, N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) tda18271_write_regs(fe, R_CPD, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* downconvert internal calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) N += 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) tda18271_calc_main_pll(fe, N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) tda18271_write_regs(fe, R_MPD, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) tda18271_write_regs(fe, R_EP2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) tda18271_write_regs(fe, R_EP1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) tda18271_write_regs(fe, R_EP2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) tda18271_write_regs(fe, R_EP1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* normal operation for the main pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* normal operation for the cal pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) tda18271_charge_pump_source(fe, TDA18271_CAL_PLL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) msleep(10); /* plls locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* launch the rf tracking filters calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) regs[R_EB20] |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) tda18271_write_regs(fe, R_EB20, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) msleep(60); /* calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* set CAL mode to normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) regs[R_EP4] &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* switch on agc1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) regs[R_EP3] &= ~0x40; /* sm_lt = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) tda18271_write_regs(fe, R_EB18, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) tda18271_write_regs(fe, R_EP3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tda18271_write_regs(fe, R_EP1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* get calibration result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) tda18271_read_extended(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return regs[R_EB14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int tda18271_powerscan(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u32 *freq_in, u32 *freq_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int sgn, bcal, count, wait, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u8 cid_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u16 count_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) freq = *freq_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tda18271_calc_rf_band(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) tda18271_calc_rf_cal(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) tda18271_calc_gain_taper(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) tda18271_lookup_cid_target(fe, &freq, &cid_target, &count_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) tda18271_write_regs(fe, R_EP2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) tda18271_write_regs(fe, R_EB14, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* downconvert frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) freq += 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tda18271_calc_main_pll(fe, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) tda18271_write_regs(fe, R_MPD, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) msleep(5); /* pll locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* detection mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) regs[R_EP4] &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regs[R_EP4] |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) tda18271_write_regs(fe, R_EP4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* launch power detection measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tda18271_write_regs(fe, R_EP2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* read power detection info, stored in EB10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = tda18271_read_extended(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* algorithm initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sgn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) *freq_out = *freq_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) bcal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) wait = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) while ((regs[R_EB10] & 0x3f) < cid_target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* downconvert updated freq to 1 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) freq = *freq_in + (sgn * count) + 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) tda18271_calc_main_pll(fe, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tda18271_write_regs(fe, R_MPD, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (wait) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) msleep(5); /* pll locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) wait = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) udelay(100); /* pll locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* launch power detection measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) tda18271_write_regs(fe, R_EP2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* read power detection info, stored in EB10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = tda18271_read_extended(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) count += 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (count <= count_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (sgn <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) sgn = -1 * sgn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) count = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) wait = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if ((regs[R_EB10] & 0x3f) >= cid_target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) bcal = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) *freq_out = freq - 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) bcal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) tda_cal("bcal = %d, freq_in = %d, freq_out = %d (freq = %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) bcal, *freq_in, *freq_out, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return bcal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int tda18271_powerscan_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* set standard to digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) regs[R_EP3] &= ~0x1f; /* clear std bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) regs[R_EP3] |= 0x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* set cal mode to normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) regs[R_EP4] &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* update IF output level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) regs[R_EP4] &= ~0x1c; /* clear if level bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = tda18271_write_regs(fe, R_EP3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = tda18271_write_regs(fe, R_EB18, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) regs[R_EB21] &= ~0x03; /* set agc2_gain to -15 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* 1.5 MHz low pass filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) regs[R_EB23] |= 0x04; /* forcelp_fc2_en = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) regs[R_EB23] |= 0x02; /* lp_fc[2] = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ret = tda18271_write_regs(fe, R_EB21, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int bcal, rf, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) s32 divisor, dividend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define RF1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define RF2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define RF3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 rf_default[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u32 rf_freq[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) s32 prog_cal[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) s32 prog_tab[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) i = tda18271_lookup_rf_band(fe, &freq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (tda_fail(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) rf_default[RF1] = 1000 * map[i].rf1_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) rf_default[RF2] = 1000 * map[i].rf2_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) rf_default[RF3] = 1000 * map[i].rf3_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) for (rf = RF1; rf <= RF3; rf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (0 == rf_default[rf])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) tda_cal("freq = %d, rf = %d\n", freq, rf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* look for optimized calibration frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) bcal = tda18271_powerscan(fe, &rf_default[rf], &rf_freq[rf]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (tda_fail(bcal))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return bcal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) tda18271_calc_rf_cal(fe, &rf_freq[rf]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) prog_tab[rf] = (s32)regs[R_EB14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (1 == bcal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) prog_cal[rf] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) (s32)tda18271_calibrate_rf(fe, rf_freq[rf]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) prog_cal[rf] = prog_tab[rf];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) switch (rf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case RF1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) map[i].rf_a1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) map[i].rf_b1 = (prog_cal[RF1] - prog_tab[RF1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) map[i].rf1 = rf_freq[RF1] / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case RF2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dividend = (prog_cal[RF2] - prog_tab[RF2] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) prog_cal[RF1] + prog_tab[RF1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) divisor = (s32)(rf_freq[RF2] - rf_freq[RF1]) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) map[i].rf_a1 = (dividend / divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) map[i].rf2 = rf_freq[RF2] / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case RF3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dividend = (prog_cal[RF3] - prog_tab[RF3] -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) prog_cal[RF2] + prog_tab[RF2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) divisor = (s32)(rf_freq[RF3] - rf_freq[RF2]) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) map[i].rf_a2 = (dividend / divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) map[i].rf_b2 = (prog_cal[RF2] - prog_tab[RF2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) map[i].rf3 = rf_freq[RF3] / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) tda_info("performing RF tracking filter calibration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* wait for die temperature stabilization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret = tda18271_powerscan_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* rf band calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) for (i = 0; priv->rf_cal_state[i].rfmax != 0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) tda18271_rf_tracking_filters_init(fe, 1000 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) priv->rf_cal_state[i].rfmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) priv->tm_rfcal = tda18271_read_thermometer(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int tda18271c2_rf_cal_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* test RF_CAL_OK to see if we need init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if ((regs[R_EP1] & 0x10) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) priv->cal_initialized = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (priv->cal_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ret = tda18271_calc_rf_filter_curve(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret = tda18271_por(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) tda_info("RF tracking filter calibration complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) priv->cal_initialized = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) tda_info("RF tracking filter calibration failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 freq, u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u32 N = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* calculate bp filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) tda18271_calc_bp_filter(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) tda18271_write_regs(fe, R_EP1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) regs[R_EB4] &= 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) regs[R_EB4] |= 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) tda18271_write_regs(fe, R_EB4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) regs[R_EB7] = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) tda18271_write_regs(fe, R_EB7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) regs[R_EB14] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) tda18271_write_regs(fe, R_EB14, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) regs[R_EB20] = 0xcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) tda18271_write_regs(fe, R_EB20, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* set cal mode to RF tracking filter calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) regs[R_EP4] |= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* calculate cal pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) switch (priv->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case TDA18271_ANALOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) N = freq - 1250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) case TDA18271_DIGITAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) N = freq + bw / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) tda18271_calc_cal_pll(fe, N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* calculate main pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) switch (priv->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case TDA18271_ANALOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) N = freq - 250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case TDA18271_DIGITAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) N = freq + bw / 2 + 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) tda18271_calc_main_pll(fe, N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = tda18271_write_regs(fe, R_EP3, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) msleep(5); /* RF tracking filter calibration initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* search for K,M,CO for RF calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) tda18271_calc_km(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) tda18271_write_regs(fe, R_EB13, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* search for rf band */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) tda18271_calc_rf_band(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* search for gain taper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) tda18271_calc_gain_taper(fe, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) tda18271_write_regs(fe, R_EP2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) tda18271_write_regs(fe, R_EP1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) tda18271_write_regs(fe, R_EP2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) tda18271_write_regs(fe, R_EP1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) regs[R_EB4] &= 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) regs[R_EB4] |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) tda18271_write_regs(fe, R_EB4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) regs[R_EB7] = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) tda18271_write_regs(fe, R_EB7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) msleep(10); /* pll locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) regs[R_EB20] = 0xec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) tda18271_write_regs(fe, R_EB20, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) msleep(60); /* RF tracking filter calibration completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) regs[R_EP4] &= ~0x03; /* set cal mode to normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) tda18271_write_regs(fe, R_EP4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) tda18271_write_regs(fe, R_EP1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* RF tracking filter correction for VHF_Low band */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (0 == tda18271_calc_rf_cal(fe, &freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) tda18271_write_regs(fe, R_EB14, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int tda18271_ir_cal_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = tda18271_read_regs(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* test IR_CAL_OK to see if we need init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if ((regs[R_EP1] & 0x08) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = tda18271_init_regs(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int tda18271_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* full power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret = tda18271_set_standby_mode(fe, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = tda18271_ir_cal_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (priv->id == TDA18271HDC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) tda18271c2_rf_cal_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static int tda18271_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* enter standby mode, with required output features enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = tda18271_toggle_output(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static int tda18271_agc(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) switch (priv->config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) case TDA8290_LNA_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* no external agc configuration required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (tda18271_debug & DBG_ADV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) tda_dbg("no agc configuration provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) case TDA8290_LNA_ON_BRIDGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* switch with GPIO of saa713x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) tda_dbg("invoking callback\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (fe->callback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = fe->callback(priv->i2c_props.adap->algo_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) DVB_FRONTEND_COMPONENT_TUNER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) TDA18271_CALLBACK_CMD_AGC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) priv->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case TDA8290_LNA_GP0_HIGH_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) case TDA8290_LNA_GP0_HIGH_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* n/a - currently not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) tda_err("unsupported configuration: %d\n", priv->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int tda18271_tune(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct tda18271_std_map_item *map, u32 freq, u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) tda_dbg("freq = %d, ifc = %d, bw = %d, agc_mode = %d, std = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) freq, map->if_freq, bw, map->agc_mode, map->std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ret = tda18271_agc(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) tda_warn("failed to configure agc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ret = tda18271_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) switch (priv->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case TDA18271HDC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) tda18271c1_rf_tracking_filter_calibration(fe, freq, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case TDA18271HDC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) tda18271c2_rf_tracking_filters_correction(fe, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ret = tda18271_channel_configuration(fe, map, freq, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static int tda18271_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) u32 delsys = c->delivery_system;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) u32 bw = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) u32 freq = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct tda18271_std_map *std_map = &priv->std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct tda18271_std_map_item *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) priv->mode = TDA18271_DIGITAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) switch (delsys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) case SYS_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) map = &std_map->atsc_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) bw = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) case SYS_ISDBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) case SYS_DVBT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (bw <= 6000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) map = &std_map->dvbt_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) } else if (bw <= 7000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) map = &std_map->dvbt_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) map = &std_map->dvbt_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) case SYS_DVBC_ANNEX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) bw = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) case SYS_DVBC_ANNEX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (bw <= 6000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) map = &std_map->qam_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) } else if (bw <= 7000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) map = &std_map->qam_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) map = &std_map->qam_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) tda_warn("modulation type not supported!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* When tuning digital, the analog demod must be tri-stated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (fe->ops.analog_ops.standby)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) fe->ops.analog_ops.standby(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ret = tda18271_tune(fe, map, freq, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) priv->if_freq = map->if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) priv->frequency = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) priv->bandwidth = bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static int tda18271_set_analog_params(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct analog_parameters *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct tda18271_std_map *std_map = &priv->std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct tda18271_std_map_item *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) char *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u32 freq = params->frequency * 125 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ((params->mode == V4L2_TUNER_RADIO) ? 1 : 1000) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) priv->mode = TDA18271_ANALOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (params->mode == V4L2_TUNER_RADIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) map = &std_map->fm_radio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) mode = "fm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) } else if (params->std & V4L2_STD_MN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) map = &std_map->atv_mn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) mode = "MN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) } else if (params->std & V4L2_STD_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) map = &std_map->atv_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) mode = "B";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) } else if (params->std & V4L2_STD_GH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) map = &std_map->atv_gh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) mode = "GH";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) } else if (params->std & V4L2_STD_PAL_I) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) map = &std_map->atv_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) mode = "I";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) } else if (params->std & V4L2_STD_DK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) map = &std_map->atv_dk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) mode = "DK";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) } else if (params->std & V4L2_STD_SECAM_L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) map = &std_map->atv_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) mode = "L";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) } else if (params->std & V4L2_STD_SECAM_LC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) map = &std_map->atv_lc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) mode = "L'";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) map = &std_map->atv_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) mode = "xx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) tda_dbg("setting tda18271 to system %s\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ret = tda18271_tune(fe, map, freq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) priv->if_freq = map->if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) priv->frequency = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) priv->bandwidth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static void tda18271_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) mutex_lock(&tda18271_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) hybrid_tuner_release_state(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) mutex_unlock(&tda18271_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static int tda18271_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) *frequency = priv->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int tda18271_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) *bandwidth = priv->bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static int tda18271_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) *frequency = (u32)priv->if_freq * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define tda18271_update_std(std_cfg, name) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (map->std_cfg.if_freq + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) map->std_cfg.agc_mode + map->std_cfg.std + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) map->std_cfg.if_lvl + map->std_cfg.rfagc_top > 0) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) tda_dbg("Using custom std config for %s\n", name); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) memcpy(&std->std_cfg, &map->std_cfg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) sizeof(struct tda18271_std_map_item)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) } } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define tda18271_dump_std_item(std_cfg, name) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) tda_dbg("(%s) if_freq = %d, agc_mode = %d, std = %d, " \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) "if_lvl = %d, rfagc_top = 0x%02x\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) name, std->std_cfg.if_freq, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) std->std_cfg.agc_mode, std->std_cfg.std, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) std->std_cfg.if_lvl, std->std_cfg.rfagc_top); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int tda18271_dump_std_map(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct tda18271_std_map *std = &priv->std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) tda_dbg("========== STANDARD MAP SETTINGS ==========\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) tda18271_dump_std_item(fm_radio, " fm ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) tda18271_dump_std_item(atv_b, "atv b ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) tda18271_dump_std_item(atv_dk, "atv dk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) tda18271_dump_std_item(atv_gh, "atv gh");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) tda18271_dump_std_item(atv_i, "atv i ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) tda18271_dump_std_item(atv_l, "atv l ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) tda18271_dump_std_item(atv_lc, "atv l'");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) tda18271_dump_std_item(atv_mn, "atv mn");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) tda18271_dump_std_item(atsc_6, "atsc 6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) tda18271_dump_std_item(dvbt_6, "dvbt 6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) tda18271_dump_std_item(dvbt_7, "dvbt 7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) tda18271_dump_std_item(dvbt_8, "dvbt 8");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) tda18271_dump_std_item(qam_6, "qam 6 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) tda18271_dump_std_item(qam_7, "qam 7 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) tda18271_dump_std_item(qam_8, "qam 8 ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static int tda18271_update_std_map(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct tda18271_std_map *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct tda18271_std_map *std = &priv->std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (!map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) tda18271_update_std(fm_radio, "fm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) tda18271_update_std(atv_b, "atv b");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) tda18271_update_std(atv_dk, "atv dk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) tda18271_update_std(atv_gh, "atv gh");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) tda18271_update_std(atv_i, "atv i");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) tda18271_update_std(atv_l, "atv l");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) tda18271_update_std(atv_lc, "atv l'");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) tda18271_update_std(atv_mn, "atv mn");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) tda18271_update_std(atsc_6, "atsc 6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) tda18271_update_std(dvbt_6, "dvbt 6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) tda18271_update_std(dvbt_7, "dvbt 7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) tda18271_update_std(dvbt_8, "dvbt 8");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) tda18271_update_std(qam_6, "qam 6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) tda18271_update_std(qam_7, "qam 7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) tda18271_update_std(qam_8, "qam 8");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static int tda18271_get_id(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ret = tda18271_read_regs(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) tda_info("Error reading device ID @ %d-%04x, bailing out.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) i2c_adapter_id(priv->i2c_props.adap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) priv->i2c_props.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) switch (regs[R_ID] & 0x7f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) name = "TDA18271HD/C1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) priv->id = TDA18271HDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) name = "TDA18271HD/C2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) priv->id = TDA18271HDC2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) tda_info("Unknown device (%i) detected @ %d-%04x, device not supported.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) regs[R_ID], i2c_adapter_id(priv->i2c_props.adap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) priv->i2c_props.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) tda_info("%s detected @ %d-%04x\n", name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) i2c_adapter_id(priv->i2c_props.adap), priv->i2c_props.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static int tda18271_setup_configuration(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) struct tda18271_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) priv->gate = (cfg) ? cfg->gate : TDA18271_GATE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) priv->role = (cfg) ? cfg->role : TDA18271_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) priv->config = (cfg) ? cfg->config : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) priv->small_i2c = (cfg) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) cfg->small_i2c : TDA18271_39_BYTE_CHUNK_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) priv->output_opt = (cfg) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) cfg->output_opt : TDA18271_OUTPUT_LT_XT_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static inline int tda18271_need_cal_on_startup(struct tda18271_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* tda18271_cal_on_startup == -1 when cal module option is unset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return ((tda18271_cal_on_startup == -1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* honor configuration setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ((cfg) && (cfg->rf_cal_on_startup)) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* module option overrides configuration setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) (tda18271_cal_on_startup)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static int tda18271_set_config(struct dvb_frontend *fe, void *priv_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct tda18271_config *cfg = (struct tda18271_config *) priv_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) tda18271_setup_configuration(fe, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (tda18271_need_cal_on_startup(cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) tda18271_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* override default std map with values in config struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if ((cfg) && (cfg->std_map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) tda18271_update_std_map(fe, cfg->std_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static const struct dvb_tuner_ops tda18271_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .name = "NXP TDA18271HD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .frequency_min_hz = 45 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .frequency_max_hz = 864 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .frequency_step_hz = 62500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .init = tda18271_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .sleep = tda18271_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .set_params = tda18271_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .set_analog_params = tda18271_set_analog_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .release = tda18271_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .set_config = tda18271_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .get_frequency = tda18271_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .get_bandwidth = tda18271_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .get_if_frequency = tda18271_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct tda18271_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct tda18271_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) int instance, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) mutex_lock(&tda18271_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) instance = hybrid_tuner_request_state(struct tda18271_priv, priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) hybrid_tuner_instance_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) i2c, addr, "tda18271");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) switch (instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* new tuner instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) tda18271_setup_configuration(fe, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) priv->cal_initialized = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ret = tda18271_get_id(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ret = tda18271_assign_map_layout(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /* if delay_cal is set, delay IR & RF calibration until init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * module option 'cal' overrides this delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if ((cfg->delay_cal) && (!tda18271_need_cal_on_startup(cfg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) tda18271_init_regs(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if ((tda18271_need_cal_on_startup(cfg)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) (priv->id == TDA18271HDC2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) tda18271c2_rf_cal_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* enter standby mode, with required output features enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ret = tda18271_toggle_output(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) tda_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* existing tuner instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* allow dvb driver to override configuration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (cfg->gate != TDA18271_GATE_ANALOG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) priv->gate = cfg->gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (cfg->role)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) priv->role = cfg->role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (cfg->config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) priv->config = cfg->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (cfg->small_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) priv->small_i2c = cfg->small_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (cfg->output_opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) priv->output_opt = cfg->output_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (cfg->std_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) tda18271_update_std_map(fe, cfg->std_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (tda18271_need_cal_on_startup(cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) tda18271_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* override default std map with values in config struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if ((cfg) && (cfg->std_map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) tda18271_update_std_map(fe, cfg->std_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) mutex_unlock(&tda18271_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (tda18271_debug & (DBG_MAP | DBG_ADV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) tda18271_dump_std_map(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) mutex_unlock(&tda18271_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) tda18271_release(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) EXPORT_SYMBOL_GPL(tda18271_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) MODULE_VERSION("0.4");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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