^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) tda18271-common.c - driver for the Philips / NXP TDA18271 silicon tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "tda18271-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum tda18271_i2c_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) switch (priv->gate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) case TDA18271_GATE_DIGITAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) case TDA18271_GATE_ANALOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) gate = priv->gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) case TDA18271_GATE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) switch (priv->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) case TDA18271_DIGITAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) gate = TDA18271_GATE_DIGITAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) case TDA18271_ANALOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) gate = TDA18271_GATE_ANALOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) switch (gate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) case TDA18271_GATE_ANALOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (fe->ops.analog_ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) case TDA18271_GATE_DIGITAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ret = fe->ops.i2c_gate_ctrl(fe, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*---------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void tda18271_dump_regs(struct dvb_frontend *fe, int extended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) tda_reg("=== TDA18271 REG DUMP ===\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) tda_reg("ID_BYTE = 0x%02x\n", 0xff & regs[R_ID]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) tda_reg("THERMO_BYTE = 0x%02x\n", 0xff & regs[R_TM]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) tda_reg("POWER_LEVEL_BYTE = 0x%02x\n", 0xff & regs[R_PL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) tda_reg("EASY_PROG_BYTE_1 = 0x%02x\n", 0xff & regs[R_EP1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) tda_reg("EASY_PROG_BYTE_2 = 0x%02x\n", 0xff & regs[R_EP2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) tda_reg("EASY_PROG_BYTE_3 = 0x%02x\n", 0xff & regs[R_EP3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) tda_reg("EASY_PROG_BYTE_4 = 0x%02x\n", 0xff & regs[R_EP4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) tda_reg("EASY_PROG_BYTE_5 = 0x%02x\n", 0xff & regs[R_EP5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) tda_reg("CAL_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_CPD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) tda_reg("CAL_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_CD1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) tda_reg("CAL_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_CD2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) tda_reg("CAL_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_CD3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) tda_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* only dump extended regs if DBG_ADV is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!(tda18271_debug & DBG_ADV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* W indicates write-only registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Register dump for write-only registers shows last value written. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) tda_reg("EXTENDED_BYTE_1 = 0x%02x\n", 0xff & regs[R_EB1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) tda_reg("EXTENDED_BYTE_2 = 0x%02x\n", 0xff & regs[R_EB2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) tda_reg("EXTENDED_BYTE_3 = 0x%02x\n", 0xff & regs[R_EB3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) tda_reg("EXTENDED_BYTE_4 = 0x%02x\n", 0xff & regs[R_EB4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) tda_reg("EXTENDED_BYTE_5 = 0x%02x\n", 0xff & regs[R_EB5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) tda_reg("EXTENDED_BYTE_6 = 0x%02x\n", 0xff & regs[R_EB6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) tda_reg("EXTENDED_BYTE_7 = 0x%02x\n", 0xff & regs[R_EB7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) tda_reg("EXTENDED_BYTE_8 = 0x%02x\n", 0xff & regs[R_EB8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tda_reg("EXTENDED_BYTE_9 W = 0x%02x\n", 0xff & regs[R_EB9]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tda_reg("EXTENDED_BYTE_10 = 0x%02x\n", 0xff & regs[R_EB10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) tda_reg("EXTENDED_BYTE_11 = 0x%02x\n", 0xff & regs[R_EB11]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tda_reg("EXTENDED_BYTE_12 = 0x%02x\n", 0xff & regs[R_EB12]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) tda_reg("EXTENDED_BYTE_13 = 0x%02x\n", 0xff & regs[R_EB13]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tda_reg("EXTENDED_BYTE_14 = 0x%02x\n", 0xff & regs[R_EB14]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) tda_reg("EXTENDED_BYTE_15 = 0x%02x\n", 0xff & regs[R_EB15]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) tda_reg("EXTENDED_BYTE_16 W = 0x%02x\n", 0xff & regs[R_EB16]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tda_reg("EXTENDED_BYTE_17 W = 0x%02x\n", 0xff & regs[R_EB17]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) tda_reg("EXTENDED_BYTE_18 = 0x%02x\n", 0xff & regs[R_EB18]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) tda_reg("EXTENDED_BYTE_19 W = 0x%02x\n", 0xff & regs[R_EB19]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tda_reg("EXTENDED_BYTE_20 W = 0x%02x\n", 0xff & regs[R_EB20]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) tda_reg("EXTENDED_BYTE_21 = 0x%02x\n", 0xff & regs[R_EB21]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) tda_reg("EXTENDED_BYTE_22 = 0x%02x\n", 0xff & regs[R_EB22]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) tda_reg("EXTENDED_BYTE_23 = 0x%02x\n", 0xff & regs[R_EB23]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int tda18271_read_regs(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned char buf = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .addr = priv->i2c_props.addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .buf = &buf, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .addr = priv->i2c_props.addr, .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .buf = regs, .len = 16 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) tda18271_i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* read all registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = i2c_transfer(priv->i2c_props.adap, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) tda18271_i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) tda_err("ERROR: i2c_transfer returned: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (tda18271_debug & DBG_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tda18271_dump_regs(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return (ret == 2 ? 0 : ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int tda18271_read_extended(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned char regdump[TDA18271_NUM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned char buf = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { .addr = priv->i2c_props.addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .buf = &buf, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { .addr = priv->i2c_props.addr, .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .buf = regdump, .len = TDA18271_NUM_REGS }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tda18271_i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* read all registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = i2c_transfer(priv->i2c_props.adap, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tda18271_i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) tda_err("ERROR: i2c_transfer returned: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) for (i = 0; i < TDA18271_NUM_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* don't update write-only registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if ((i != R_EB9) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) (i != R_EB16) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) (i != R_EB17) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) (i != R_EB19) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) (i != R_EB20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) regs[i] = regdump[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (tda18271_debug & DBG_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tda18271_dump_regs(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return (ret == 2 ? 0 : ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int __tda18271_write_regs(struct dvb_frontend *fe, int idx, int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) bool lock_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned char buf[TDA18271_NUM_REGS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct i2c_msg msg = { .addr = priv->i2c_props.addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .buf = buf };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int i, ret = 1, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) BUG_ON((len == 0) || (idx + len > sizeof(buf)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) switch (priv->small_i2c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case TDA18271_03_BYTE_CHUNK_INIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) max = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case TDA18271_08_BYTE_CHUNK_INIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) max = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case TDA18271_16_BYTE_CHUNK_INIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) max = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case TDA18271_39_BYTE_CHUNK_INIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) max = 39;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * If lock_i2c is true, it will take the I2C bus for tda18271 private
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * usage during the entire write ops, as otherwise, bad things could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * During device init, several write operations will happen. So,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * tda18271_init_regs controls the I2C lock directly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * disabling lock_i2c here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (lock_i2c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tda18271_i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) i2c_lock_bus(priv->i2c_props.adap, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (max > len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) max = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) buf[0] = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) for (i = 1; i <= max; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) buf[i] = regs[idx - 1 + i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) msg.len = max + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* write registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = __i2c_transfer(priv->i2c_props.adap, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) idx += max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) len -= max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (lock_i2c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) i2c_unlock_bus(priv->i2c_props.adap, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) tda18271_i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) tda_err("ERROR: idx = 0x%x, len = %d, i2c_transfer returned: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) idx, max, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return (ret == 1 ? 0 : ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return __tda18271_write_regs(fe, idx, len, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*---------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int __tda18271_charge_pump_source(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) enum tda18271_pll pll, int force,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) bool lock_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int r_cp = (pll == TDA18271_CAL_PLL) ? R_EB7 : R_EB4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) regs[r_cp] &= ~0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) regs[r_cp] |= ((force & 1) << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return __tda18271_write_regs(fe, r_cp, 1, lock_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int tda18271_charge_pump_source(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) enum tda18271_pll pll, int force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return __tda18271_charge_pump_source(fe, pll, force, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int tda18271_init_regs(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tda_dbg("initializing registers for device @ %d-%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) i2c_adapter_id(priv->i2c_props.adap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) priv->i2c_props.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Don't let any other I2C transfer to happen at adapter during init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * as those could cause bad things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) tda18271_i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) i2c_lock_bus(priv->i2c_props.adap, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* initialize registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) switch (priv->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case TDA18271HDC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) regs[R_ID] = 0x83;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case TDA18271HDC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) regs[R_ID] = 0x84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) regs[R_TM] = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) regs[R_PL] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) regs[R_EP1] = 0xc6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) regs[R_EP2] = 0xdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) regs[R_EP3] = 0x16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) regs[R_EP4] = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) regs[R_EP5] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) regs[R_CPD] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) regs[R_CD1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) regs[R_CD2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) regs[R_CD3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) regs[R_MPD] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) regs[R_MD1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) regs[R_MD2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) regs[R_MD3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) switch (priv->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case TDA18271HDC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) regs[R_EB1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case TDA18271HDC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) regs[R_EB1] = 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) regs[R_EB2] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) regs[R_EB3] = 0x84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) regs[R_EB4] = 0x41;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) regs[R_EB5] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) regs[R_EB6] = 0x84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) regs[R_EB7] = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) regs[R_EB8] = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) regs[R_EB9] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) regs[R_EB10] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) regs[R_EB11] = 0x96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) switch (priv->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case TDA18271HDC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) regs[R_EB12] = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case TDA18271HDC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) regs[R_EB12] = 0x33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) regs[R_EB13] = 0xc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) regs[R_EB14] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) regs[R_EB15] = 0x8f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) regs[R_EB16] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) regs[R_EB17] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) switch (priv->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case TDA18271HDC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) regs[R_EB18] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case TDA18271HDC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) regs[R_EB18] = 0x8c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) regs[R_EB19] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) regs[R_EB20] = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) switch (priv->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case TDA18271HDC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) regs[R_EB21] = 0x33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case TDA18271HDC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) regs[R_EB21] = 0xb3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) regs[R_EB22] = 0x48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) regs[R_EB23] = 0xb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) __tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* setup agc1 gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) regs[R_EB17] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) __tda18271_write_regs(fe, R_EB17, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) regs[R_EB17] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) __tda18271_write_regs(fe, R_EB17, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) regs[R_EB17] = 0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) __tda18271_write_regs(fe, R_EB17, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) regs[R_EB17] = 0x4c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) __tda18271_write_regs(fe, R_EB17, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* setup agc2 gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if ((priv->id) == TDA18271HDC1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) regs[R_EB20] = 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) __tda18271_write_regs(fe, R_EB20, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) regs[R_EB20] = 0xa7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) __tda18271_write_regs(fe, R_EB20, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) regs[R_EB20] = 0xe7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __tda18271_write_regs(fe, R_EB20, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) regs[R_EB20] = 0xec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) __tda18271_write_regs(fe, R_EB20, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* image rejection calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* low-band */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) regs[R_EP3] = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) regs[R_EP4] = 0x66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) regs[R_EP5] = 0x81;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) regs[R_CPD] = 0xcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) regs[R_CD1] = 0x6c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) regs[R_CD2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) regs[R_CD3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) regs[R_MPD] = 0xcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) regs[R_MD1] = 0x77;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) regs[R_MD2] = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) regs[R_MD3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) __tda18271_write_regs(fe, R_EP3, 11, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if ((priv->id) == TDA18271HDC2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* main pll cp source on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) __tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* main pll cp source off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) __tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) msleep(5); /* pll locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* launch detector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) __tda18271_write_regs(fe, R_EP1, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) msleep(5); /* wanted low measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) regs[R_EP5] = 0x85;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) regs[R_CPD] = 0xcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) regs[R_CD1] = 0x66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) regs[R_CD2] = 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) __tda18271_write_regs(fe, R_EP3, 7, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) msleep(5); /* pll locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* launch optimization algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) __tda18271_write_regs(fe, R_EP2, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) msleep(30); /* image low optimization completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* mid-band */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) regs[R_EP5] = 0x82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) regs[R_CPD] = 0xa8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) regs[R_CD2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) regs[R_MPD] = 0xa9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) regs[R_MD1] = 0x73;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) regs[R_MD2] = 0x1a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) __tda18271_write_regs(fe, R_EP3, 11, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) msleep(5); /* pll locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* launch detector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __tda18271_write_regs(fe, R_EP1, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) msleep(5); /* wanted mid measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) regs[R_EP5] = 0x86;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) regs[R_CPD] = 0xa8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) regs[R_CD1] = 0x66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) regs[R_CD2] = 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) __tda18271_write_regs(fe, R_EP3, 7, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) msleep(5); /* pll locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* launch optimization algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) __tda18271_write_regs(fe, R_EP2, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) msleep(30); /* image mid optimization completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* high-band */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) regs[R_EP5] = 0x83;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) regs[R_CPD] = 0x98;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) regs[R_CD1] = 0x65;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) regs[R_CD2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) regs[R_MPD] = 0x99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) regs[R_MD1] = 0x71;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) regs[R_MD2] = 0xcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) __tda18271_write_regs(fe, R_EP3, 11, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) msleep(5); /* pll locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* launch detector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) __tda18271_write_regs(fe, R_EP1, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) msleep(5); /* wanted high measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) regs[R_EP5] = 0x87;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) regs[R_CD1] = 0x65;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) regs[R_CD2] = 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) __tda18271_write_regs(fe, R_EP3, 7, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) msleep(5); /* pll locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* launch optimization algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __tda18271_write_regs(fe, R_EP2, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) msleep(30); /* image high optimization completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* return to normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) regs[R_EP4] = 0x64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) __tda18271_write_regs(fe, R_EP4, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* synchronize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) __tda18271_write_regs(fe, R_EP1, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) i2c_unlock_bus(priv->i2c_props.adap, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) tda18271_i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*---------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * Standby modes, EP3 [7:5]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * | SM || SM_LT || SM_XT || mode description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * |=====\\=======\\=======\\====================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * | 0 || 0 || 0 || normal mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * |-----||-------||-------||------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * | || || || standby mode w/ slave tuner output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * | 1 || 0 || 0 || & loop through & xtal oscillator on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * |-----||-------||-------||------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * | 1 || 1 || 0 || standby mode w/ xtal oscillator on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * |-----||-------||-------||------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * | 1 || 1 || 1 || power off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int tda18271_set_standby_mode(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int sm, int sm_lt, int sm_xt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (tda18271_debug & DBG_ADV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) regs[R_EP3] &= ~0xe0; /* clear sm, sm_lt, sm_xt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) regs[R_EP3] |= (sm ? (1 << 7) : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) (sm_lt ? (1 << 6) : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) (sm_xt ? (1 << 5) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return tda18271_write_regs(fe, R_EP3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*---------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* sets main post divider & divider bytes, but does not write them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u8 d, pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) regs[R_MPD] = (0x7f & pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) div = ((d * (freq / 1000)) << 7) / 125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) regs[R_MD1] = 0x7f & (div >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) regs[R_MD2] = 0xff & (div >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) regs[R_MD3] = 0xff & div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* sets cal post divider & divider bytes, but does not write them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u8 d, pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) regs[R_CPD] = pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) div = ((d * (freq / 1000)) << 7) / 125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) regs[R_CD1] = 0x7f & (div >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) regs[R_CD2] = 0xff & (div >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) regs[R_CD3] = 0xff & div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /*---------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* sets bp filter bits, but does not write them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) regs[R_EP1] &= ~0x07; /* clear bp filter bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) regs[R_EP1] |= (0x07 & val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* sets K & M bits, but does not write them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) regs[R_EB13] &= ~0x7c; /* clear k & m bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) regs[R_EB13] |= (0x7c & val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* sets rf band bits, but does not write them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) regs[R_EP2] &= ~0xe0; /* clear rf band bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) regs[R_EP2] |= (0xe0 & (val << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* sets gain taper bits, but does not write them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) regs[R_EP2] |= (0x1f & val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* sets IR Meas bits, but does not write them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (tda_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) regs[R_EP5] &= ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) regs[R_EP5] |= (0x07 & val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* sets rf cal byte (RFC_Cprog), but does not write it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct tda18271_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) unsigned char *regs = priv->tda18271_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int ret = tda18271_lookup_map(fe, RF_CAL, freq, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* The TDA18271HD/C1 rf_cal map lookup is expected to go out of range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * for frequencies above 61.1 MHz. In these cases, the internal RF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * tracking filters calibration mechanism is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * There is no need to warn the user about this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) regs[R_EB14] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) void _tda_printk(struct tda18271_priv *state, const char *level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) const char *func, const char *fmt, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct va_format vaf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) va_list args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) va_start(args, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) vaf.fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) vaf.va = &args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) printk("%s%s: [%d-%04x|%c] %pV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) level, func, i2c_adapter_id(state->i2c_props.adap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) state->i2c_props.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) (state->role == TDA18271_MASTER) ? 'M' : 'S',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) printk("%s%s: %pV", level, func, &vaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) va_end(args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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