^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NXP TDA18250BHN silicon tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Olli Salonen <olli.salonen@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef TDA18250_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define TDA18250_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "tda18250.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R00_ID1 0x00 /* ID byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R01_ID2 0x01 /* ID byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R02_ID3 0x02 /* ID byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define R03_THERMO1 0x03 /* Thermo byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R04_THERMO2 0x04 /* Thermo byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R05_POWER1 0x05 /* Power byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R06_POWER2 0x06 /* Power byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R07_GPIO 0x07 /* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R08_IRQ1 0x08 /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R09_IRQ2 0x09 /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R0A_IRQ3 0x0a /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R0B_IRQ4 0x0b /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R0C_AGC11 0x0c /* AGC1 byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R0D_AGC12 0x0d /* AGC1 byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R0E_AGC13 0x0e /* AGC1 byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R0F_AGC14 0x0f /* AGC1 byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R10_LT1 0x10 /* LT byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R11_LT2 0x11 /* LT byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R12_AGC21 0x12 /* AGC2 byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R13_AGC22 0x13 /* AGC2 byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R14_AGC23 0x14 /* AGC2 byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R15_AGC24 0x15 /* AGC2 byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R16_AGC25 0x16 /* AGC2 byte 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R17_AGC31 0x17 /* AGC3 byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R18_AGC32 0x18 /* AGC3 byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R19_AGC33 0x19 /* AGC3 byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R1A_AGCK 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R1B_GAIN1 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R1C_GAIN2 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R1D_GAIN3 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R1E_WI_FI 0x1e /* Wireless Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R1F_RF_BPF 0x1f /* RF Band Pass Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R20_IR_MIX 0x20 /* IR Mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R21_IF_AGC 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define R22_IF1 0x22 /* IF byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R23_IF2 0x23 /* IF byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define R24_IF3 0x24 /* IF byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R25_REF 0x25 /* reference byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R26_IF 0x26 /* IF frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R27_RF1 0x27 /* RF frequency byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define R28_RF2 0x28 /* RF frequency byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R29_RF3 0x29 /* RF frequency byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define R2A_MSM1 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define R2B_MSM2 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define R2C_PS1 0x2c /* power saving mode byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define R2D_PS2 0x2d /* power saving mode byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define R2E_PS3 0x2e /* power saving mode byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define R2F_RSSI1 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define R30_RSSI2 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define R31_IRQ_CTRL 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define R32_DUMMY 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define R33_TEST 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define R34_MD1 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define R35_SD1 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R36_SD2 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define R37_SD3 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define R38_SD4 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define R39_SD5 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define R3A_SD_TEST 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define R3B_REGU 0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define R3C_RCCAL1 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define R3D_RCCAL2 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define R3E_IRCAL1 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define R3F_IRCAL2 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define R40_IRCAL3 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define R41_IRCAL4 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define R42_IRCAL5 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define R43_PD1 0x43 /* power down byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define R44_PD2 0x44 /* power down byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define R45_PD 0x45 /* power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define R46_CPUMP 0x46 /* charge pump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define R47_LNAPOL 0x47 /* LNA polar casc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define R48_SMOOTH1 0x48 /* smooth test byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define R49_SMOOTH2 0x49 /* smooth test byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define R4A_SMOOTH3 0x4a /* smooth test byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define R4B_XTALOSC1 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define R4C_XTALOSC2 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define R4D_XTALFLX1 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define R4E_XTALFLX2 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define R4F_XTALFLX3 0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define R50_XTALFLX4 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define R51_XTALFLX5 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define R52_IRLOOP0 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define R53_IRLOOP1 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define R54_IRLOOP2 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define R55_IRLOOP3 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define R56_IRLOOP4 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define R57_PLL_LOG 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define R58_AGC2_UP1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define R59_AGC2_UP2 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define R5A_H3H5 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define R5B_AGC_AUTO 0x5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define R5C_AGC_DEBUG 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TDA18250_NUM_REGS 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TDA18250_POWER_STANDBY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TDA18250_POWER_NORMAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TDA18250_IRQ_CAL 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TDA18250_IRQ_HW_INIT 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TDA18250_IRQ_TUNE 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct tda18250_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct mutex i2c_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 xtal_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* IF in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u16 if_dvbt_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u16 if_dvbt_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u16 if_dvbt_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u16 if_dvbc_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u16 if_dvbc_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u16 if_atsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u16 if_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) bool slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bool loopthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bool warm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 regs[TDA18250_NUM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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