Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * NXP TDA18212HN silicon tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include "tda18212.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) struct tda18212_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	struct tda18212_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	u32 if_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static int tda18212_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	struct tda18212_dev *dev = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u32 if_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u8 buf[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	#define DVBT_6   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	#define DVBT_7   1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	#define DVBT_8   2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	#define DVBT2_6  3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	#define DVBT2_7  4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	#define DVBT2_8  5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	#define DVBC_6   6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	#define DVBC_8   7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	#define ATSC_VSB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	#define ATSC_QAM 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	static const u8 bw_params[][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		     /* reg:   0f    13    23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		[DVBT_6]  = { 0xb3, 0x20, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		[DVBT_7]  = { 0xb3, 0x31, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		[DVBT_8]  = { 0xb3, 0x22, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		[DVBT2_6] = { 0xbc, 0x20, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		[DVBT2_7] = { 0xbc, 0x72, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		[DVBT2_8] = { 0xbc, 0x22, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		[DVBC_6]  = { 0x92, 0x50, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		[DVBC_8]  = { 0x92, 0x53, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		[ATSC_VSB] = { 0x7d, 0x20, 0x63 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		[ATSC_QAM] = { 0x7d, 0x20, 0x63 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	dev_dbg(&dev->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			"delivery_system=%d frequency=%d bandwidth_hz=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			c->delivery_system, c->frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			c->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	switch (c->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	case SYS_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		if_khz = dev->cfg.if_atsc_vsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		i = ATSC_VSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	case SYS_DVBC_ANNEX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		if_khz = dev->cfg.if_atsc_qam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		i = ATSC_QAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		switch (c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			if_khz = dev->cfg.if_dvbt_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			i = DVBT_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			if_khz = dev->cfg.if_dvbt_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			i = DVBT_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			if_khz = dev->cfg.if_dvbt_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			i = DVBT_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	case SYS_DVBT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		switch (c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			if_khz = dev->cfg.if_dvbt2_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			i = DVBT2_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			if_khz = dev->cfg.if_dvbt2_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			i = DVBT2_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			if_khz = dev->cfg.if_dvbt2_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			i = DVBT2_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	case SYS_DVBC_ANNEX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		if_khz = dev->cfg.if_dvbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		i = DVBC_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ret = regmap_write(dev->regmap, 0x23, bw_params[i][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ret = regmap_write(dev->regmap, 0x06, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ret = regmap_write(dev->regmap, 0x0f, bw_params[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	buf[0] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	buf[1] = bw_params[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	buf[2] = 0x03; /* default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	buf[3] = DIV_ROUND_CLOSEST(if_khz, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	buf[4] = ((c->frequency / 1000) >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	buf[5] = ((c->frequency / 1000) >>  8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	buf[6] = ((c->frequency / 1000) >>  0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	buf[7] = 0xc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	buf[8] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	ret = regmap_bulk_write(dev->regmap, 0x12, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/* actual IF rounded as it is on register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	dev->if_frequency = buf[3] * 50 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	dev_dbg(&dev->client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int tda18212_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct tda18212_dev *dev = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	*frequency = dev->if_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct dvb_tuner_ops tda18212_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.name              = "NXP TDA18212",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.frequency_min_hz  =  48 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.frequency_max_hz  = 864 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.frequency_step_hz =   1 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.set_params    = tda18212_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.get_if_frequency = tda18212_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int tda18212_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct tda18212_config *cfg = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct dvb_frontend *fe = cfg->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct tda18212_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	char *version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	static const struct regmap_config regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		dev_err(&client->dev, "kzalloc() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	memcpy(&dev->cfg, cfg, sizeof(struct tda18212_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	dev->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	dev->regmap = devm_regmap_init_i2c(client, &regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (IS_ERR(dev->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		ret = PTR_ERR(dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* check if the tuner is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	ret = regmap_read(dev->regmap, 0x00, &chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	dev_dbg(&dev->client->dev, "chip_id=%02x\n", chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	switch (chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case 0xc7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		version = "M"; /* master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	case 0x47:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		version = "S"; /* slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	dev_info(&dev->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			"NXP TDA18212HN/%s successfully identified\n", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	fe->tuner_priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	memcpy(&fe->ops.tuner_ops, &tda18212_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	i2c_set_clientdata(client, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int tda18212_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct tda18212_dev *dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct dvb_frontend *fe = dev->cfg.fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const struct i2c_device_id tda18212_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	{"tda18212", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MODULE_DEVICE_TABLE(i2c, tda18212_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct i2c_driver tda18212_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.name	= "tda18212",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.probe		= tda18212_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.remove		= tda18212_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.id_table	= tda18212_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) module_i2c_driver(tda18212_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MODULE_DESCRIPTION("NXP TDA18212HN silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_LICENSE("GPL");