Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Sharp QM1D1C0042 8PSK tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * NOTICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * As the disclosed information on the chip is very limited,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * this driver lacks some features, including chip config like IF freq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * It assumes that users of this driver (such as a PCI bridge of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * DTV receiver cards) know the relevant info and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * configure the chip via I2C if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Currently, PT3 driver is the only one that uses this driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * and contains init/config code in its firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Thus some part of the code might be dependent on PT3 specific config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "qm1d1c0042.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define QM1D1C0042_NUM_REGS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define QM1D1C0042_NUM_REG_ROWS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static const u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) reg_initval[QM1D1C0042_NUM_REG_ROWS][QM1D1C0042_NUM_REGS] = { {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		0x48, 0x1c, 0xa0, 0x10, 0xbc, 0xc5, 0x20, 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		0x00, 0xff, 0xf3, 0x00, 0x2a, 0x64, 0xa6, 0x86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		0x8c, 0xcf, 0xb8, 0xf1, 0xa8, 0xf2, 0x89, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		0x68, 0x1c, 0xc0, 0x10, 0xbc, 0xc1, 0x11, 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		0x00, 0xff, 0xf3, 0x00, 0x3f, 0x25, 0x5c, 0xd6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		0x55, 0xcf, 0x95, 0xf6, 0x36, 0xf2, 0x09, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static int reg_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static const struct qm1d1c0042_config default_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	.xtal_freq = 16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.lpf = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.fast_srch = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.lpf_wait = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.fast_srch_wait = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	.normal_srch_wait = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) struct qm1d1c0042_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct qm1d1c0042_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u8 regs[QM1D1C0042_NUM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static struct qm1d1c0042_state *cfg_to_state(struct qm1d1c0042_config *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return container_of(c, struct qm1d1c0042_state, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u8 wbuf[2] = { reg, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ret = i2c_master_send(state->i2c, wbuf, sizeof(wbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (ret >= 0 && ret < sizeof(wbuf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return (ret == sizeof(wbuf)) ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static int reg_read(struct qm1d1c0042_state *state, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct i2c_msg msgs[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			.addr = state->i2c->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			.flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			.buf = &reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			.len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			.addr = state->i2c->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			.flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			.buf = val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			.len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	ret = i2c_transfer(state->i2c->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (ret >= 0 && ret < ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return (ret == ARRAY_SIZE(msgs)) ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int qm1d1c0042_set_srch_mode(struct qm1d1c0042_state *state, bool fast)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (fast)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		state->regs[0x03] |= 0x01; /* set fast search mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		state->regs[0x03] &= ~0x01 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return reg_write(state, 0x03, state->regs[0x03]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int qm1d1c0042_wakeup(struct qm1d1c0042_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	state->regs[0x01] |= 1 << 3;             /* BB_Reg_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	state->regs[0x01] &= (~(1 << 0)) & 0xff; /* NORMAL (wake-up) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	state->regs[0x05] &= (~(1 << 3)) & 0xff; /* pfd_rst NORMAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	ret = reg_write(state, 0x01, state->regs[0x01]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		ret = reg_write(state, 0x05, state->regs[0x05]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			__func__, state->cfg.fe->dvb->num, state->cfg.fe->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* tuner_ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int qm1d1c0042_set_config(struct dvb_frontend *fe, void *priv_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct qm1d1c0042_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct qm1d1c0042_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	cfg = priv_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (cfg->fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		state->cfg.fe = cfg->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (cfg->xtal_freq != QM1D1C0042_CFG_XTAL_DFLT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		dev_warn(&state->i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			"(%s) changing xtal_freq not supported. ", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	state->cfg.xtal_freq = default_cfg.xtal_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	state->cfg.lpf = cfg->lpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	state->cfg.fast_srch = cfg->fast_srch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (cfg->lpf_wait != QM1D1C0042_CFG_WAIT_DFLT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		state->cfg.lpf_wait = cfg->lpf_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		state->cfg.lpf_wait = default_cfg.lpf_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (cfg->fast_srch_wait != QM1D1C0042_CFG_WAIT_DFLT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		state->cfg.fast_srch_wait = cfg->fast_srch_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		state->cfg.fast_srch_wait = default_cfg.fast_srch_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (cfg->normal_srch_wait != QM1D1C0042_CFG_WAIT_DFLT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		state->cfg.normal_srch_wait = cfg->normal_srch_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		state->cfg.normal_srch_wait = default_cfg.normal_srch_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* divisor, vco_band parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*  {maxfreq,  param1(band?), param2(div?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const u32 conv_table[9][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	{ 2151000, 1, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{ 1950000, 1, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{ 1800000, 1, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{ 1600000, 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	{ 1450000, 1, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	{ 1250000, 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{ 1200000, 0, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{  975000, 0, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	{  950000, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int qm1d1c0042_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct qm1d1c0042_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u8 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u32 a, sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	s32 b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	freq = fe->dtv_property_cache.frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	state->regs[0x08] &= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	state->regs[0x08] |= 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	state->regs[0x13] &= 0x9f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	state->regs[0x13] |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* div2/vco_band */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	val = state->regs[0x02] & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		if (freq < conv_table[i][0] && freq >= conv_table[i + 1][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			val |= conv_table[i][1] << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			val |= conv_table[i][2] << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	ret = reg_write(state, 0x02, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	a = DIV_ROUND_CLOSEST(freq, state->cfg.xtal_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	state->regs[0x06] &= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	state->regs[0x06] |= (a - 12) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	ret = reg_write(state, 0x06, state->regs[0x06]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	state->regs[0x07] &= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	state->regs[0x07] |= (a - 4 * ((a - 12) / 4 + 1) - 5) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	ret = reg_write(state, 0x07, state->regs[0x07]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* LPF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	val = state->regs[0x08];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (state->cfg.lpf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		/* LPF_CLK, LPF_FC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		val &= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		val |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	ret = reg_write(state, 0x08, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * b = (freq / state->cfg.xtal_freq - a) << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 * sd = b          (b >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 *      1<<22 + b  (b < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	b = (s32)div64_s64(((s64) freq) << 20, state->cfg.xtal_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			   - (((s64) a) << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (b >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		sd = b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		sd = (1 << 22) + b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	state->regs[0x09] &= 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	state->regs[0x09] |= (sd >> 16) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	state->regs[0x0a] = (sd >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	state->regs[0x0b] = sd & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ret = reg_write(state, 0x09, state->regs[0x09]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		ret = reg_write(state, 0x0a, state->regs[0x0a]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		ret = reg_write(state, 0x0b, state->regs[0x0b]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (!state->cfg.lpf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		/* CSEL_Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		ret = reg_write(state, 0x13, state->regs[0x13]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* VCO_TM, LPF_TM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	mask = state->cfg.lpf ? 0x3f : 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	val = state->regs[0x0c] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	ret = reg_write(state, 0x0c, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	usleep_range(2000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	val = state->regs[0x0c] | ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	ret = reg_write(state, 0x0c, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (state->cfg.lpf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		msleep(state->cfg.lpf_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	else if (state->regs[0x03] & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		msleep(state->cfg.fast_srch_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		msleep(state->cfg.normal_srch_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (state->cfg.lpf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		/* LPF_FC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		ret = reg_write(state, 0x08, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		/* CSEL_Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		ret = reg_write(state, 0x13, state->regs[0x13]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int qm1d1c0042_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct qm1d1c0042_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	state->regs[0x01] &= (~(1 << 3)) & 0xff; /* BB_Reg_disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	state->regs[0x01] |= 1 << 0;             /* STDBY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	state->regs[0x05] |= 1 << 3;             /* pfd_rst STANDBY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ret = reg_write(state, 0x05, state->regs[0x05]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		ret = reg_write(state, 0x01, state->regs[0x01]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			__func__, fe->dvb->num, fe->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int qm1d1c0042_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	struct qm1d1c0042_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	reg_write(state, 0x01, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	reg_write(state, 0x01, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	ret = reg_write(state, 0x01, 0x0c); /* soft reset on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	usleep_range(2000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	ret = reg_write(state, 0x01, 0x1c); /* soft reset off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	/* check ID and choose initial registers corresponding ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ret = reg_read(state, 0x00, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	for (reg_index = 0; reg_index < QM1D1C0042_NUM_REG_ROWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	     reg_index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		if (val == reg_initval[reg_index][0x00])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (reg_index >= QM1D1C0042_NUM_REG_ROWS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	memcpy(state->regs, reg_initval[reg_index], QM1D1C0042_NUM_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	usleep_range(2000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	state->regs[0x0c] |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	ret = reg_write(state, 0x0c, state->regs[0x0c]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	msleep(state->cfg.lpf_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	/* set all writable registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	for (i = 1; i <= 0x0c ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		ret = reg_write(state, i, state->regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	for (i = 0x11; i < QM1D1C0042_NUM_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		ret = reg_write(state, i, state->regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	ret = qm1d1c0042_wakeup(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		__func__, fe->dvb->num, fe->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* I2C driver functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct dvb_tuner_ops qm1d1c0042_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		.name = "Sharp QM1D1C0042",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		.frequency_min_hz =  950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		.frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.init = qm1d1c0042_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	.sleep = qm1d1c0042_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	.set_config = qm1d1c0042_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	.set_params = qm1d1c0042_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int qm1d1c0042_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 			    const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	struct qm1d1c0042_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	struct qm1d1c0042_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	state->i2c = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	cfg = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	fe = cfg->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	fe->tuner_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	qm1d1c0042_set_config(fe, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	memcpy(&fe->ops.tuner_ops, &qm1d1c0042_ops, sizeof(qm1d1c0042_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	i2c_set_clientdata(client, &state->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	dev_info(&client->dev, "Sharp QM1D1C0042 attached.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int qm1d1c0042_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	struct qm1d1c0042_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	state = cfg_to_state(i2c_get_clientdata(client));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	state->cfg.fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct i2c_device_id qm1d1c0042_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	{"qm1d1c0042", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MODULE_DEVICE_TABLE(i2c, qm1d1c0042_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static struct i2c_driver qm1d1c0042_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.name	= "qm1d1c0042",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	.probe		= qm1d1c0042_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	.remove		= qm1d1c0042_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	.id_table	= qm1d1c0042_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) module_i2c_driver(qm1d1c0042_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_DESCRIPTION("Sharp QM1D1C0042 tuner");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_AUTHOR("Akihiro TSUKADA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_LICENSE("GPL");