Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Sharp QM1D1B0004 satellite tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * based on (former) drivers/media/pci/pt1/va1j5jf8007s.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Since the data-sheet of this tuner chip is not available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * this driver lacks some tuner_ops and config options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * In addition, the implementation might be dependent on the specific use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * in the FE module: VA1J5JF8007S and/or in the product: Earthsoft PT1/PT2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "qm1d1b0004.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * Tuner I/F (copied from the former va1j5jf8007s.c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * b[0] I2C addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * b[1] "0":1, BG:2, divider_quotient[7:3]:5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * b[2] divider_quotient[2:0]:3, divider_remainder:5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * b[3] "111":3, LPF[3:2]:2, TM:1, "0":1, REF:1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * b[4] BANDX, PSC:1, LPF[1:0]:2, DIV:1, "0":1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * PLL frequency step :=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *    REF == 0 -> PLL XTL frequency(4MHz) / 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *    REF == 1 -> PLL XTL frequency(4MHz) / 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * PreScaler :=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *    PSC == 0 -> x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *    PSC == 1 -> x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * divider_quotient := (frequency / PLL frequency step) / PreScaler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * divider_remainder := (frequency / PLL frequency step) % PreScaler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * LPF := LPF Frequency / 1000 / 2 - 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * LPF Frequency @ baudrate=28.86Mbps = 30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * band (1..9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *   band 1 (freq <  986000) -> DIV:1, BANDX:5, PSC:1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *   band 2 (freq < 1072000) -> DIV:1, BANDX:6, PSC:1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  *   band 3 (freq < 1154000) -> DIV:1, BANDX:7, PSC:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *   band 4 (freq < 1291000) -> DIV:0, BANDX:1, PSC:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  *   band 5 (freq < 1447000) -> DIV:0, BANDX:2, PSC:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  *   band 6 (freq < 1615000) -> DIV:0, BANDX:3, PSC:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  *   band 7 (freq < 1791000) -> DIV:0, BANDX:4, PSC:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *   band 8 (freq < 1972000) -> DIV:0, BANDX:5, PSC:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  *   band 9 (freq < 2150000) -> DIV:0, BANDX:6, PSC:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define QM1D1B0004_PSC_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define QM1D1B0004_XTL_FREQ 4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define QM1D1B0004_LPF_FALLBACK 30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #if 0 /* Currently unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static const struct qm1d1b0004_config default_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.lpf_freq = QM1D1B0004_CFG_LPF_DFLT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.half_step = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) struct qm1d1b0004_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct qm1d1b0004_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) struct qm1d1b0004_cb_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u8 cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static const struct qm1d1b0004_cb_map cb_maps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{  986000, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{ 1072000, 0xd2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{ 1154000, 0xe2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{ 1291000, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{ 1447000, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	{ 1615000, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{ 1791000, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{ 1972000, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static u8 lookup_cb(u32 frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	const struct qm1d1b0004_cb_map *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	for (i = 0; i < ARRAY_SIZE(cb_maps); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		map = &cb_maps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		if (frequency < map->frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			return map->cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int qm1d1b0004_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct qm1d1b0004_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	u32 frequency, pll, lpf_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u16 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	u8 buf[4], cb, lpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	frequency = fe->dtv_property_cache.frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	pll = QM1D1B0004_XTL_FREQ / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (state->cfg.half_step)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		pll /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	word = DIV_ROUND_CLOSEST(frequency, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	cb = lookup_cb(frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (cb & QM1D1B0004_PSC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		word = (word << 1 & ~0x1f) | (word & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* step.1: set frequency with BG:2, TM:0(4MHZ), LPF:4MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	buf[0] = 0x40 | word >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	buf[1] = word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* inconsisnten with the above I/F doc. maybe the doc is wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	buf[2] = 0xe0 | state->cfg.half_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	buf[3] = cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ret = i2c_master_send(state->i2c, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* step.2: set TM:1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	buf[0] = 0xe4 | state->cfg.half_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	ret = i2c_master_send(state->i2c, buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/* step.3: set LPF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	lpf_freq = state->cfg.lpf_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (lpf_freq == QM1D1B0004_CFG_LPF_DFLT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		lpf_freq = fe->dtv_property_cache.symbol_rate / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (lpf_freq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		lpf_freq = QM1D1B0004_LPF_FALLBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	lpf = DIV_ROUND_UP(lpf_freq, 2000) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	buf[0] = 0xe4 | ((lpf & 0x0c) << 1) | state->cfg.half_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	buf[1] = cb | ((lpf & 0x03) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ret = i2c_master_send(state->i2c, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* step.4: read PLL lock? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	buf[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ret = i2c_master_recv(state->i2c, buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int qm1d1b0004_set_config(struct dvb_frontend *fe, void *priv_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct qm1d1b0004_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	memcpy(&state->cfg, priv_cfg, sizeof(state->cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int qm1d1b0004_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct qm1d1b0004_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	u8 buf[2] = {0xf8, 0x04};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (state->cfg.half_step)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		buf[0] |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return i2c_master_send(state->i2c, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct dvb_tuner_ops qm1d1b0004_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.name = "Sharp qm1d1b0004",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.frequency_min_hz =  950 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.frequency_max_hz = 2150 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.init = qm1d1b0004_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.set_params = qm1d1b0004_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.set_config = qm1d1b0004_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) qm1d1b0004_probe(struct i2c_client *client, const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct qm1d1b0004_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct qm1d1b0004_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	cfg = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	fe = cfg->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	i2c_set_clientdata(client, fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	fe->tuner_priv = kzalloc(sizeof(struct qm1d1b0004_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (!fe->tuner_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		goto err_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	memcpy(&fe->ops.tuner_ops, &qm1d1b0004_ops, sizeof(fe->ops.tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	state->i2c = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ret = qm1d1b0004_set_config(fe, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		goto err_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	dev_info(&client->dev, "Sharp QM1D1B0004 attached.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) err_priv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	kfree(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) err_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int qm1d1b0004_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	fe = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	kfree(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct i2c_device_id qm1d1b0004_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	{"qm1d1b0004", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_DEVICE_TABLE(i2c, qm1d1b0004_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct i2c_driver qm1d1b0004_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.name = "qm1d1b0004",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.probe    = qm1d1b0004_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.remove   = qm1d1b0004_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.id_table = qm1d1b0004_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) module_i2c_driver(qm1d1b0004_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MODULE_DESCRIPTION("Sharp QM1D1B0004");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MODULE_AUTHOR("Akihiro Tsukada");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MODULE_LICENSE("GPL");