^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "tuner-i2c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "mxl5007t.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static DEFINE_MUTEX(mxl5007t_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static LIST_HEAD(hybrid_tuner_instance_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static int mxl5007t_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) module_param_named(debug, mxl5007t_debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MODULE_PARM_DESC(debug, "set debug level");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define mxl_printk(kern, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) printk(kern "%s: " fmt "\n", __func__, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define mxl_err(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) mxl_printk(KERN_ERR, "%d: " fmt, __LINE__, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define mxl_warn(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) mxl_printk(KERN_WARNING, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define mxl_info(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) mxl_printk(KERN_INFO, fmt, ##arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define mxl_debug(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (mxl5007t_debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) mxl_printk(KERN_DEBUG, fmt, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define mxl_fail(ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int __ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) __ret = (ret < 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (__ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mxl_printk(KERN_ERR, "error %d on line %d", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ret, __LINE__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum mxl5007t_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MxL_MODE_ISDBT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MxL_MODE_DVBT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MxL_MODE_ATSC = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MxL_MODE_CABLE = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum mxl5007t_chip_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MxL_UNKNOWN_ID = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MxL_5007_V1_F1 = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MxL_5007_V1_F2 = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MxL_5007_V4 = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MxL_5007_V2_100_F1 = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MxL_5007_V2_100_F2 = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MxL_5007_V2_200_F1 = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MxL_5007_V2_200_F2 = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct reg_pair_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct reg_pair_t init_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { 0x02, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 0x03, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 0x05, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 0x06, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 0x2e, 0x15 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 0x30, 0x10 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 0x45, 0x58 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 0x48, 0x19 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 0x52, 0x03 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 0x53, 0x44 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { 0x6a, 0x4b }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { 0x76, 0x00 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { 0x78, 0x18 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 0x7a, 0x17 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { 0x85, 0x06 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct reg_pair_t init_tab_cable[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { 0x02, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { 0x03, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { 0x05, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { 0x06, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 0x09, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0x0a, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0x0b, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { 0x2e, 0x15 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 0x30, 0x10 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 0x45, 0x58 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { 0x48, 0x19 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { 0x52, 0x03 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { 0x53, 0x44 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { 0x6a, 0x4b }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { 0x76, 0x00 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { 0x78, 0x18 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { 0x7a, 0x17 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { 0x85, 0x06 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct reg_pair_t reg_pair_rftune[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 0x0f, 0x00 }, /* abort tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 0x0c, 0x15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 0x0d, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { 0x0e, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 0x1f, 0x87 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 0x20, 0x1f }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 0x21, 0x87 }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { 0x22, 0x1f }, /* OVERRIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { 0x80, 0x01 }, /* freq dependent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 0x0f, 0x01 }, /* start tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct mxl5007t_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct list_head hybrid_tuner_instance_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct tuner_i2c_props i2c_props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct mxl5007t_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) enum mxl5007t_chip_version chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct reg_pair_t tab_init[ARRAY_SIZE(init_tab)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum mxl5007t_if_freq if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* called by _init and _rftun to manipulate the register arrays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) while (reg_pair[i].reg || reg_pair[i].val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (reg_pair[i].reg == reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) reg_pair[i].val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) reg_pair[i].val |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void copy_reg_bits(struct reg_pair_t *reg_pair1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct reg_pair_t *reg_pair2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) i = j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) while (reg_pair1[i].reg || reg_pair1[i].val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) while (reg_pair2[j].reg || reg_pair2[j].val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (reg_pair1[i].reg != reg_pair2[j].reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) reg_pair2[j].val = reg_pair1[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void mxl5007t_set_mode_bits(struct mxl5007t_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) enum mxl5007t_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) s32 if_diff_out_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case MxL_MODE_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case MxL_MODE_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case MxL_MODE_ISDBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) case MxL_MODE_CABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) set_reg_bits(state->tab_init_cable, 0x0a, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 8 - if_diff_out_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mxl_fail(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) enum mxl5007t_if_freq if_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int invert_if)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) switch (if_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case MxL_IF_4_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) val = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case MxL_IF_4_5_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case MxL_IF_4_57_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) val = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case MxL_IF_5_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) val = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case MxL_IF_5_38_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case MxL_IF_6_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) val = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case MxL_IF_6_28_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case MxL_IF_9_1915_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) val = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case MxL_IF_35_25_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val = 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case MxL_IF_36_15_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) val = 0x0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case MxL_IF_44_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) val = 0x0b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mxl_fail(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) set_reg_bits(state->tab_init, 0x02, 0x0f, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* set inverted IF or normal IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) state->if_freq = if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) enum mxl5007t_xtal_freq xtal_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) switch (xtal_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case MxL_XTAL_16_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* select xtal freq & ref freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case MxL_XTAL_20_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case MxL_XTAL_20_25_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case MxL_XTAL_20_48_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case MxL_XTAL_24_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case MxL_XTAL_25_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case MxL_XTAL_25_14_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case MxL_XTAL_27_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case MxL_XTAL_28_8_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case MxL_XTAL_32_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case MxL_XTAL_40_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case MxL_XTAL_44_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case MxL_XTAL_48_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case MxL_XTAL_49_3811_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mxl_fail(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) enum mxl5007t_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct mxl5007t_config *cfg = state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) memcpy(&state->tab_init, &init_tab, sizeof(init_tab));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (mode >= MxL_MODE_CABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) copy_reg_bits(state->tab_init, state->tab_init_cable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return state->tab_init_cable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return state->tab_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) enum mxl5007t_bw_mhz {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MxL_BW_6MHz = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MxL_BW_7MHz = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MxL_BW_8MHz = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void mxl5007t_set_bw_bits(struct mxl5007t_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) enum mxl5007t_bw_mhz bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) switch (bw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case MxL_BW_6MHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * and DIG_MODEINDEX_CSF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case MxL_BW_7MHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) val = 0x2a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case MxL_BW_8MHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) val = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mxl_fail(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 rf_freq, enum mxl5007t_bw_mhz bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 dig_rf_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 frac_divider = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) memcpy(&state->tab_rftune, ®_pair_rftune, sizeof(reg_pair_rftune));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mxl5007t_set_bw_bits(state, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Convert RF frequency into 16 bits =>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * 10 bit integer (MHz) + 6 bit fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dig_rf_freq = rf_freq / MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) temp = rf_freq % MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) for (i = 0; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dig_rf_freq <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) frac_divider /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (temp > frac_divider) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) temp -= frac_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dig_rf_freq++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* add to have shift center point by 7.8124 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (temp > 7812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dig_rf_freq++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (rf_freq >= 333000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return state->tab_rftune;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u8 buf[] = { reg, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) mxl_err("failed!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int mxl5007t_write_regs(struct mxl5007t_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct reg_pair_t *reg_pair)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = mxl5007t_write_reg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) reg_pair[i].reg, reg_pair[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u8 buf[2] = { 0xfb, reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { .addr = state->i2c_props.addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .buf = buf, .len = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { .addr = state->i2c_props.addr, .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .buf = val, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = i2c_transfer(state->i2c_props.adap, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) mxl_err("failed!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int mxl5007t_soft_reset(struct mxl5007t_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u8 d = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .addr = state->i2c_props.addr, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .buf = &d, .len = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mxl_err("failed!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int mxl5007t_tuner_init(struct mxl5007t_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) enum mxl5007t_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct reg_pair_t *init_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* calculate initialization reg array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) init_regs = mxl5007t_calc_init_regs(state, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = mxl5007t_write_regs(state, init_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) enum mxl5007t_bw_mhz bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct reg_pair_t *rf_tune_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* calculate channel change reg array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ret = mxl5007t_write_regs(state, rf_tune_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) msleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int mxl5007t_synth_lock_status(struct mxl5007t_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int *rf_locked, int *ref_locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u8 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *rf_locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) *ref_locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = mxl5007t_read_reg(state, 0xd8, &d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if ((d & 0x0c) == 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) *rf_locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if ((d & 0x03) == 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) *ref_locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int mxl5007t_get_status(struct dvb_frontend *fe, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct mxl5007t_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int rf_locked, ref_locked, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = mxl5007t_synth_lock_status(state, &rf_locked, &ref_locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) mxl_debug("%s%s", rf_locked ? "rf locked " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ref_locked ? "ref locked" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if ((rf_locked) || (ref_locked))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *status |= TUNER_STATUS_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int mxl5007t_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 delsys = c->delivery_system;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct mxl5007t_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) enum mxl5007t_bw_mhz bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) enum mxl5007t_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 freq = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) switch (delsys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case SYS_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) mode = MxL_MODE_ATSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) bw = MxL_BW_6MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case SYS_DVBC_ANNEX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mode = MxL_MODE_CABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) bw = MxL_BW_6MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case SYS_DVBT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mode = MxL_MODE_DVBT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) switch (c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) bw = MxL_BW_6MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) bw = MxL_BW_7MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) bw = MxL_BW_8MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) mxl_err("modulation type not supported!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mutex_lock(&state->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = mxl5007t_tuner_init(state, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret = mxl5007t_tuner_rf_tune(state, freq, bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) state->frequency = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) state->bandwidth = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) mutex_unlock(&state->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int mxl5007t_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct mxl5007t_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* wake from standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ret = mxl5007t_write_reg(state, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) mxl_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int mxl5007t_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct mxl5007t_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* enter standby mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = mxl5007t_write_reg(state, 0x01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) mxl_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = mxl5007t_write_reg(state, 0x0f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mxl_fail(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int mxl5007t_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct mxl5007t_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *frequency = state->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int mxl5007t_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct mxl5007t_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) *bandwidth = state->bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int mxl5007t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct mxl5007t_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) *frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) switch (state->if_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) case MxL_IF_4_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) *frequency = 4000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) case MxL_IF_4_5_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) *frequency = 4500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case MxL_IF_4_57_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) *frequency = 4570000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) case MxL_IF_5_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) *frequency = 5000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) case MxL_IF_5_38_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) *frequency = 5380000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) case MxL_IF_6_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) *frequency = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) case MxL_IF_6_28_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) *frequency = 6280000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) case MxL_IF_9_1915_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) *frequency = 9191500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case MxL_IF_35_25_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) *frequency = 35250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case MxL_IF_36_15_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) *frequency = 36150000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case MxL_IF_44_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) *frequency = 44000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static void mxl5007t_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct mxl5007t_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mutex_lock(&mxl5007t_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) hybrid_tuner_release_state(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) mutex_unlock(&mxl5007t_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const struct dvb_tuner_ops mxl5007t_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .name = "MaxLinear MxL5007T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .init = mxl5007t_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .sleep = mxl5007t_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .set_params = mxl5007t_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .get_status = mxl5007t_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .get_frequency = mxl5007t_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .get_bandwidth = mxl5007t_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .release = mxl5007t_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .get_if_frequency = mxl5007t_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int mxl5007t_get_chip_id(struct mxl5007t_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = mxl5007t_read_reg(state, 0xd9, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) case MxL_5007_V1_F1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) name = "MxL5007.v1.f1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) case MxL_5007_V1_F2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) name = "MxL5007.v1.f2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) case MxL_5007_V2_100_F1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) name = "MxL5007.v2.100.f1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case MxL_5007_V2_100_F2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) name = "MxL5007.v2.100.f2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case MxL_5007_V2_200_F1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) name = "MxL5007.v2.200.f1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) case MxL_5007_V2_200_F2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) name = "MxL5007.v2.200.f2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) case MxL_5007_V4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) name = "MxL5007T.v4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) name = "MxL5007T";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) id = MxL_UNKNOWN_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) state->chip_id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mxl_info("%s detected @ %d-%04x", name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) i2c_adapter_id(state->i2c_props.adap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) state->i2c_props.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) mxl_warn("unable to identify device @ %d-%04x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) i2c_adapter_id(state->i2c_props.adap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) state->i2c_props.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) state->chip_id = MxL_UNKNOWN_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct i2c_adapter *i2c, u8 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct mxl5007t_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct mxl5007t_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int instance, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) mutex_lock(&mxl5007t_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) instance = hybrid_tuner_request_state(struct mxl5007t_state, state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) hybrid_tuner_instance_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) i2c, addr, "mxl5007t");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) switch (instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* new tuner instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) state->config = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) mutex_init(&state->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = mxl5007t_get_chip_id(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* check return value of mxl5007t_get_chip_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* existing tuner instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ret = mxl5007t_soft_reset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = mxl5007t_write_reg(state, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) state->config->loop_thru_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (mxl_fail(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) fe->tuner_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) mutex_unlock(&mxl5007t_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) memcpy(&fe->ops.tuner_ops, &mxl5007t_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) mutex_unlock(&mxl5007t_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) mxl5007t_release(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) EXPORT_SYMBOL_GPL(mxl5007t_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) MODULE_VERSION("0.2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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