^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2008 MaxLinear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __MXL5005S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __MXL5005S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct mxl5005s_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* 7 bit i2c address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 i2c_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IF_FREQ_4570000HZ 4570000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IF_FREQ_4571429HZ 4571429
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IF_FREQ_5380000HZ 5380000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IF_FREQ_36000000HZ 36000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IF_FREQ_36125000HZ 36125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IF_FREQ_36166667HZ 36166667
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IF_FREQ_44000000HZ 44000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 if_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CRYSTAL_FREQ_4000000HZ 4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CRYSTAL_FREQ_16000000HZ 16000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CRYSTAL_FREQ_25000000HZ 25000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CRYSTAL_FREQ_28800000HZ 28800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 xtal_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MXL_DUAL_AGC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MXL_SINGLE_AGC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 agc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MXL_TF_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MXL_TF_OFF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MXL_TF_C 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MXL_TF_C_H 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MXL_TF_D 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MXL_TF_D_L 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MXL_TF_E 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MXL_TF_F 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MXL_TF_E_2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MXL_TF_E_NA 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MXL_TF_G 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 tracking_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MXL_RSSI_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MXL_RSSI_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 rssi_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MXL_CAP_SEL_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MXL_CAP_SEL_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 cap_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MXL_DIV_OUT_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MXL_DIV_OUT_4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 div_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MXL_CLOCK_OUT_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MXL_CLOCK_OUT_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 clock_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MXL5005S_IF_OUTPUT_LOAD_200_OHM 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MXL5005S_IF_OUTPUT_LOAD_300_OHM 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 output_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MXL5005S_TOP_5P5 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MXL5005S_TOP_7P2 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MXL5005S_TOP_9P2 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MXL5005S_TOP_11P0 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MXL5005S_TOP_12P9 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MXL5005S_TOP_14P7 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MXL5005S_TOP_16P8 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MXL5005S_TOP_19P4 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MXL5005S_TOP_21P2 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MXL5005S_TOP_23P2 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MXL5005S_TOP_25P2 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MXL5005S_TOP_27P1 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MXL5005S_TOP_29P2 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MXL5005S_TOP_31P7 317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MXL5005S_TOP_34P9 349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MXL_ANALOG_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MXL_DIGITAL_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 mod_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MXL_ZERO_IF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MXL_LOW_IF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 if_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Some boards need to override the built-in logic for determining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) the gain when in QAM mode (the HVR-1600 is one such case) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 qam_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Stuff I don't know what to do with */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 AgcMasterByte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #if IS_REACHABLE(CONFIG_MEDIA_TUNER_MXL5005S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct mxl5005s_config *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct mxl5005s_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif /* CONFIG_DVB_TUNER_MXL5005S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif /* __MXL5005S_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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