^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Copyright (C) 2008 MaxLinear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 2006 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Functions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) mxl5005s_reset()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) mxl5005s_writereg()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) mxl5005s_writeregs()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) mxl5005s_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) mxl5005s_reconfigure()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) mxl5005s_AssignTunerMode()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) mxl5005s_set_params()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) mxl5005s_get_frequency()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) mxl5005s_get_bandwidth()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) mxl5005s_release()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) mxl5005s_attach()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Copyright (C) 2008 Realtek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Copyright (C) 2008 Jan Hoogenraad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Functions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) mxl5005s_SetRfFreqHz()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) History of this driver (Steven Toth):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) I was given a public release of a linux driver that included
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) support for the MaxLinear MXL5005S silicon tuner. Analysis of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) the tuner driver showed clearly three things.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 1. The tuner driver didn't support the LinuxTV tuner API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) so the code Realtek added had to be removed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 2. A significant amount of the driver is reference driver code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) from MaxLinear, I felt it was important to identify and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) preserve this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 3. New code has to be added to interface correctly with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) LinuxTV API, as a regular kernel module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Other than the reference driver enum's, I've clearly marked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) sections of the code and retained the copyright of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) respective owners.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include "mxl5005s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define dprintk(level, arg...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (level <= debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) printk(arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TUNER_REGS_NUM 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define INITCTRL_NUM 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #ifdef _MXL_PRODUCTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CHCTRL_NUM 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CHCTRL_NUM 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MXLCTRL_NUM 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MASTER_CONTROL_ADDR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Enumeration of Master Control Register State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) enum master_control_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MC_LOAD_START = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MC_POWER_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MC_SYNTH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MC_SEQ_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Enumeration of MXL5005 Tuner Modulation Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MXL_DEFAULT_MODULATION = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MXL_DVBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MXL_ATSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MXL_QAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MXL_ANALOG_CABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MXL_ANALOG_OTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* MXL5005 Tuner Register Struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct TunerReg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u16 Reg_Num; /* Tuner Register Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u16 Reg_Val; /* Current sw programmed value waiting to be written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Initialization Control Names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DN_IQTN_AMP_CUT = 1, /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) BB_MODE, /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) BB_BUF, /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) BB_BUF_OA, /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) BB_ALPF_BANDSELECT, /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) BB_IQSWAP, /* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) BB_DLPF_BANDSEL, /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) RFSYN_CHP_GAIN, /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) RFSYN_EN_CHP_HIGAIN, /* 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) AGC_IF, /* 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) AGC_RF, /* 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) IF_DIVVAL, /* 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) IF_VCO_BIAS, /* 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CHCAL_INT_MOD_IF, /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) CHCAL_FRAC_MOD_IF, /* 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DRV_RES_SEL, /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) I_DRIVER, /* 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) EN_AAF, /* 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) EN_3P, /* 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) EN_AUX_3P, /* 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SEL_AAF_BAND, /* 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SEQ_ENCLK16_CLK_OUT, /* 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SEQ_SEL4_16B, /* 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) XTAL_CAPSELECT, /* 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) IF_SEL_DBL, /* 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) RFSYN_R_DIV, /* 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SEQ_EXTSYNTHCALIF, /* 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) SEQ_EXTDCCAL, /* 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) AGC_EN_RSSI, /* 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) RFA_ENCLKRFAGC, /* 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) RFA_RSSI_REFH, /* 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) RFA_RSSI_REF, /* 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) RFA_RSSI_REFL, /* 33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) RFA_FLR, /* 34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) RFA_CEIL, /* 35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) SEQ_EXTIQFSMPULSE, /* 36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) OVERRIDE_1, /* 37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) BB_INITSTATE_DLPF_TUNE, /* 38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) TG_R_DIV, /* 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EN_CHP_LIN_B, /* 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Channel Change Control Names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DN_POLY = 51, /* 51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DN_RFGAIN, /* 52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DN_CAP_RFLPF, /* 53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DN_EN_VHFUHFBAR, /* 54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DN_GAIN_ADJUST, /* 55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DN_IQTNBUF_AMP, /* 56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DN_IQTNGNBFBIAS_BST, /* 57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) RFSYN_EN_OUTMUX, /* 58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) RFSYN_SEL_VCO_OUT, /* 59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) RFSYN_SEL_VCO_HI, /* 60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) RFSYN_SEL_DIVM, /* 61 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) RFSYN_RF_DIV_BIAS, /* 62 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DN_SEL_FREQ, /* 63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) RFSYN_VCO_BIAS, /* 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) CHCAL_INT_MOD_RF, /* 65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CHCAL_FRAC_MOD_RF, /* 66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) RFSYN_LPF_R, /* 67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CHCAL_EN_INT_RF, /* 68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) TG_LO_DIVVAL, /* 69 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) TG_LO_SELVAL, /* 70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) TG_DIV_VAL, /* 71 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) TG_VCO_BIAS, /* 72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) SEQ_EXTPOWERUP, /* 73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) OVERRIDE_2, /* 74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) OVERRIDE_3, /* 75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) OVERRIDE_4, /* 76 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) SEQ_FSM_PULSE, /* 77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) GPIO_4B, /* 78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) GPIO_3B, /* 79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) GPIO_4, /* 80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) GPIO_3, /* 81 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) GPIO_1B, /* 82 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) DAC_A_ENABLE, /* 83 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DAC_B_ENABLE, /* 84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DAC_DIN_A, /* 85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DAC_DIN_B, /* 86 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #ifdef _MXL_PRODUCTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) RFSYN_EN_DIV, /* 87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) RFSYN_DIVM, /* 88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DN_BYPASS_AGC_I2C /* 89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * The following context is source code provided by MaxLinear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * MaxLinear source code - Common_MXL.h (?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MXL5005S_LATCH_BYTE 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Register address, MSB, and LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MXL5005S_BB_IQSWAP_ADDR 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MXL5005S_BB_IQSWAP_MSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MXL5005S_BB_IQSWAP_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MXL5005S_BB_DLPF_BANDSEL_ADDR 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MXL5005S_BB_DLPF_BANDSEL_MSB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MXL5005S_BB_DLPF_BANDSEL_LSB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Standard modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MXL5005S_STANDARD_DVBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MXL5005S_STANDARD_ATSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MXL5005S_STANDARD_MODE_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Bandwidth modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MXL5005S_BANDWIDTH_6MHZ = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MXL5005S_BANDWIDTH_7MHZ = 7000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MXL5005S_BANDWIDTH_8MHZ = 8000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MXL5005S_BANDWIDTH_MODE_NUM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* MXL5005 Tuner Control Struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct TunerControl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u16 Ctrl_Num; /* Control Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u16 size; /* Number of bits to represent Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u16 addr[25]; /* Array of Tuner Register Address for each bit pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u16 bit[25]; /* Array of bit pos in Reg Addr for each bit pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u16 val[25]; /* Binary representation of Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* MXL5005 Tuner Struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct mxl5005s_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 IF_OUT; /* Desired IF Out Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 RF_IN; /* RF Input Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 Fxtal; /* XTAL Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u16 TOP; /* Value: take over point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u8 CLOCK_OUT; /* 0: turn off clk out; 1: turn on clock out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 DIV_OUT; /* 4MHz or 16MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Modulation Type; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u8 Mod_Type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Tracking Filter Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 TF_Type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Calculated Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 RF_LO; /* Synth RF LO Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 IF_LO; /* Synth IF LO Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 TG_LO; /* Synth TG_LO Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Pointers to ControlName Arrays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u16 Init_Ctrl_Num; /* Number of INIT Control Names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct TunerControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u16 CH_Ctrl_Num; /* Number of CH Control Names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct TunerControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u16 MXL_Ctrl_Num; /* Number of MXL Control Names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct TunerControl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Pointer to Tuner Register Array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u16 TunerRegs_Num; /* Number of Tuner Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct TunerReg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Linux driver framework specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct mxl5005s_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct dvb_frontend *frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Cache values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 current_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static u16 MXL_GetMasterControl(u8 *MasterReg, int state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 bitVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 *RegVal, int *count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static u32 MXL_Ceiling(u32 value, u32 resolution);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 value, u16 controlGroup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 *RegVal, int *count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u8 *RegVal, int *count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u8 *datatable, u8 len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static u16 MXL_IFSynthInit(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* ----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Begin: Custom code salvaged from the Realtek driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Copyright (C) 2008 Realtek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Copyright (C) 2008 Jan Hoogenraad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * This code is placed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Released by Realtek under GPLv2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Thanks to Realtek for a lot of support we received !
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Revision: 080314 - original version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int TableLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 IfDivval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned char MasterControlByte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Set MxL5005S tuner RF frequency according to example code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Tuner RF frequency setting stage 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) AddrTable[0] = MASTER_CONTROL_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ByteTable[0] |= state->config->AgcMasterByte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Tuner RF frequency setting stage 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MXL_TuneRF(fe, RfFreqHz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MXL_ControlWrite(fe, IF_DIVVAL, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ByteTable[TableLen] = MasterControlByte |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) state->config->AgcMasterByte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) TableLen += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Wait 30 ms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Tuner RF frequency setting stage 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MXL_ControlWrite(fe, IF_DIVVAL, IfDivval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ByteTable[TableLen] = MasterControlByte |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) state->config->AgcMasterByte ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) TableLen += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* End: Custom code taken from the Realtek driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* ----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Begin: Reference driver code found in the Realtek driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Copyright (C) 2008 MaxLinear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) state->TunerRegs_Num = TUNER_REGS_NUM ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) state->TunerRegs[0].Reg_Num = 9 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) state->TunerRegs[0].Reg_Val = 0x40 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) state->TunerRegs[1].Reg_Num = 11 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) state->TunerRegs[1].Reg_Val = 0x19 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) state->TunerRegs[2].Reg_Num = 12 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) state->TunerRegs[2].Reg_Val = 0x60 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) state->TunerRegs[3].Reg_Num = 13 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) state->TunerRegs[3].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) state->TunerRegs[4].Reg_Num = 14 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) state->TunerRegs[4].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) state->TunerRegs[5].Reg_Num = 15 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) state->TunerRegs[5].Reg_Val = 0xC0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) state->TunerRegs[6].Reg_Num = 16 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) state->TunerRegs[6].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) state->TunerRegs[7].Reg_Num = 17 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) state->TunerRegs[7].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) state->TunerRegs[8].Reg_Num = 18 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) state->TunerRegs[8].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) state->TunerRegs[9].Reg_Num = 19 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) state->TunerRegs[9].Reg_Val = 0x34 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) state->TunerRegs[10].Reg_Num = 21 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) state->TunerRegs[10].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) state->TunerRegs[11].Reg_Num = 22 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) state->TunerRegs[11].Reg_Val = 0x6B ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) state->TunerRegs[12].Reg_Num = 23 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) state->TunerRegs[12].Reg_Val = 0x35 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) state->TunerRegs[13].Reg_Num = 24 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) state->TunerRegs[13].Reg_Val = 0x70 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) state->TunerRegs[14].Reg_Num = 25 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) state->TunerRegs[14].Reg_Val = 0x3E ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) state->TunerRegs[15].Reg_Num = 26 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) state->TunerRegs[15].Reg_Val = 0x82 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) state->TunerRegs[16].Reg_Num = 31 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) state->TunerRegs[16].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) state->TunerRegs[17].Reg_Num = 32 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) state->TunerRegs[17].Reg_Val = 0x40 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) state->TunerRegs[18].Reg_Num = 33 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) state->TunerRegs[18].Reg_Val = 0x53 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) state->TunerRegs[19].Reg_Num = 34 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) state->TunerRegs[19].Reg_Val = 0x81 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) state->TunerRegs[20].Reg_Num = 35 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) state->TunerRegs[20].Reg_Val = 0xC9 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) state->TunerRegs[21].Reg_Num = 36 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) state->TunerRegs[21].Reg_Val = 0x01 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) state->TunerRegs[22].Reg_Num = 37 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) state->TunerRegs[22].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) state->TunerRegs[23].Reg_Num = 41 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) state->TunerRegs[23].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) state->TunerRegs[24].Reg_Num = 42 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) state->TunerRegs[24].Reg_Val = 0xF8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) state->TunerRegs[25].Reg_Num = 43 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) state->TunerRegs[25].Reg_Val = 0x43 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) state->TunerRegs[26].Reg_Num = 44 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) state->TunerRegs[26].Reg_Val = 0x20 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) state->TunerRegs[27].Reg_Num = 45 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) state->TunerRegs[27].Reg_Val = 0x80 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) state->TunerRegs[28].Reg_Num = 46 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) state->TunerRegs[28].Reg_Val = 0x88 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) state->TunerRegs[29].Reg_Num = 47 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) state->TunerRegs[29].Reg_Val = 0x86 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) state->TunerRegs[30].Reg_Num = 48 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) state->TunerRegs[30].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) state->TunerRegs[31].Reg_Num = 49 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) state->TunerRegs[31].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) state->TunerRegs[32].Reg_Num = 53 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) state->TunerRegs[32].Reg_Val = 0x94 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) state->TunerRegs[33].Reg_Num = 54 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) state->TunerRegs[33].Reg_Val = 0xFA ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) state->TunerRegs[34].Reg_Num = 55 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) state->TunerRegs[34].Reg_Val = 0x92 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) state->TunerRegs[35].Reg_Num = 56 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) state->TunerRegs[35].Reg_Val = 0x80 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) state->TunerRegs[36].Reg_Num = 57 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) state->TunerRegs[36].Reg_Val = 0x41 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) state->TunerRegs[37].Reg_Num = 58 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) state->TunerRegs[37].Reg_Val = 0xDB ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) state->TunerRegs[38].Reg_Num = 59 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) state->TunerRegs[38].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) state->TunerRegs[39].Reg_Num = 60 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) state->TunerRegs[39].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) state->TunerRegs[40].Reg_Num = 61 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) state->TunerRegs[40].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) state->TunerRegs[41].Reg_Num = 62 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) state->TunerRegs[41].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) state->TunerRegs[42].Reg_Num = 65 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) state->TunerRegs[42].Reg_Val = 0xF8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) state->TunerRegs[43].Reg_Num = 66 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) state->TunerRegs[43].Reg_Val = 0xE4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) state->TunerRegs[44].Reg_Num = 67 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) state->TunerRegs[44].Reg_Val = 0x90 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) state->TunerRegs[45].Reg_Num = 68 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) state->TunerRegs[45].Reg_Val = 0xC0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) state->TunerRegs[46].Reg_Num = 69 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) state->TunerRegs[46].Reg_Val = 0x01 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) state->TunerRegs[47].Reg_Num = 70 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) state->TunerRegs[47].Reg_Val = 0x50 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) state->TunerRegs[48].Reg_Num = 71 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) state->TunerRegs[48].Reg_Val = 0x06 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) state->TunerRegs[49].Reg_Num = 72 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) state->TunerRegs[49].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) state->TunerRegs[50].Reg_Num = 73 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) state->TunerRegs[50].Reg_Val = 0x20 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) state->TunerRegs[51].Reg_Num = 76 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) state->TunerRegs[51].Reg_Val = 0xBB ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) state->TunerRegs[52].Reg_Num = 77 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) state->TunerRegs[52].Reg_Val = 0x13 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) state->TunerRegs[53].Reg_Num = 81 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) state->TunerRegs[53].Reg_Val = 0x04 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) state->TunerRegs[54].Reg_Num = 82 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) state->TunerRegs[54].Reg_Val = 0x75 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) state->TunerRegs[55].Reg_Num = 83 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) state->TunerRegs[55].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) state->TunerRegs[56].Reg_Num = 84 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) state->TunerRegs[56].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) state->TunerRegs[57].Reg_Num = 85 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) state->TunerRegs[57].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) state->TunerRegs[58].Reg_Num = 91 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) state->TunerRegs[58].Reg_Val = 0x70 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) state->TunerRegs[59].Reg_Num = 92 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) state->TunerRegs[59].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) state->TunerRegs[60].Reg_Num = 93 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) state->TunerRegs[60].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) state->TunerRegs[61].Reg_Num = 94 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) state->TunerRegs[61].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) state->TunerRegs[62].Reg_Num = 95 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) state->TunerRegs[62].Reg_Val = 0x0C ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) state->TunerRegs[63].Reg_Num = 96 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) state->TunerRegs[63].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) state->TunerRegs[64].Reg_Num = 97 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) state->TunerRegs[64].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) state->TunerRegs[65].Reg_Num = 98 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) state->TunerRegs[65].Reg_Val = 0xE2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) state->TunerRegs[66].Reg_Num = 99 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) state->TunerRegs[66].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) state->TunerRegs[67].Reg_Num = 100 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) state->TunerRegs[67].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) state->TunerRegs[68].Reg_Num = 101 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) state->TunerRegs[68].Reg_Val = 0x12 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) state->TunerRegs[69].Reg_Num = 102 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) state->TunerRegs[69].Reg_Val = 0x80 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) state->TunerRegs[70].Reg_Num = 103 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) state->TunerRegs[70].Reg_Val = 0x32 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) state->TunerRegs[71].Reg_Num = 104 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) state->TunerRegs[71].Reg_Val = 0xB4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) state->TunerRegs[72].Reg_Num = 105 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) state->TunerRegs[72].Reg_Val = 0x60 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) state->TunerRegs[73].Reg_Num = 106 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) state->TunerRegs[73].Reg_Val = 0x83 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) state->TunerRegs[74].Reg_Num = 107 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) state->TunerRegs[74].Reg_Val = 0x84 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) state->TunerRegs[75].Reg_Num = 108 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) state->TunerRegs[75].Reg_Val = 0x9C ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) state->TunerRegs[76].Reg_Num = 109 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) state->TunerRegs[76].Reg_Val = 0x02 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) state->TunerRegs[77].Reg_Num = 110 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) state->TunerRegs[77].Reg_Val = 0x81 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) state->TunerRegs[78].Reg_Num = 111 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) state->TunerRegs[78].Reg_Val = 0xC0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) state->TunerRegs[79].Reg_Num = 112 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) state->TunerRegs[79].Reg_Val = 0x10 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) state->TunerRegs[80].Reg_Num = 131 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) state->TunerRegs[80].Reg_Val = 0x8A ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) state->TunerRegs[81].Reg_Num = 132 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) state->TunerRegs[81].Reg_Val = 0x10 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) state->TunerRegs[82].Reg_Num = 133 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) state->TunerRegs[82].Reg_Val = 0x24 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) state->TunerRegs[83].Reg_Num = 134 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) state->TunerRegs[83].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) state->TunerRegs[84].Reg_Num = 135 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) state->TunerRegs[84].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) state->TunerRegs[85].Reg_Num = 136 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) state->TunerRegs[85].Reg_Val = 0x7E ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) state->TunerRegs[86].Reg_Num = 137 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) state->TunerRegs[86].Reg_Val = 0x40 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) state->TunerRegs[87].Reg_Num = 138 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) state->TunerRegs[87].Reg_Val = 0x38 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) state->TunerRegs[88].Reg_Num = 146 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) state->TunerRegs[88].Reg_Val = 0xF6 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) state->TunerRegs[89].Reg_Num = 147 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) state->TunerRegs[89].Reg_Val = 0x1A ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) state->TunerRegs[90].Reg_Num = 148 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) state->TunerRegs[90].Reg_Val = 0x62 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) state->TunerRegs[91].Reg_Num = 149 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) state->TunerRegs[91].Reg_Val = 0x33 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) state->TunerRegs[92].Reg_Num = 150 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) state->TunerRegs[92].Reg_Val = 0x80 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) state->TunerRegs[93].Reg_Num = 156 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) state->TunerRegs[93].Reg_Val = 0x56 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) state->TunerRegs[94].Reg_Num = 157 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) state->TunerRegs[94].Reg_Val = 0x17 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) state->TunerRegs[95].Reg_Num = 158 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) state->TunerRegs[95].Reg_Val = 0xA9 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) state->TunerRegs[96].Reg_Num = 159 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) state->TunerRegs[96].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) state->TunerRegs[97].Reg_Num = 160 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) state->TunerRegs[97].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) state->TunerRegs[98].Reg_Num = 161 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) state->TunerRegs[98].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) state->TunerRegs[99].Reg_Num = 162 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) state->TunerRegs[99].Reg_Val = 0x40 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) state->TunerRegs[100].Reg_Num = 166 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) state->TunerRegs[100].Reg_Val = 0xAE ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) state->TunerRegs[101].Reg_Num = 167 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) state->TunerRegs[101].Reg_Val = 0x1B ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) state->TunerRegs[102].Reg_Num = 168 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) state->TunerRegs[102].Reg_Val = 0xF2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) state->TunerRegs[103].Reg_Num = 195 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) state->TunerRegs[103].Reg_Val = 0x00 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static u16 MXL5005_ControlInit(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) state->Init_Ctrl_Num = INITCTRL_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) state->Init_Ctrl[0].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) state->Init_Ctrl[0].addr[0] = 73;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) state->Init_Ctrl[0].bit[0] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) state->Init_Ctrl[0].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) state->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) state->Init_Ctrl[1].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) state->Init_Ctrl[1].addr[0] = 53;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) state->Init_Ctrl[1].bit[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) state->Init_Ctrl[1].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) state->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) state->Init_Ctrl[2].size = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) state->Init_Ctrl[2].addr[0] = 53;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) state->Init_Ctrl[2].bit[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) state->Init_Ctrl[2].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) state->Init_Ctrl[2].addr[1] = 57;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) state->Init_Ctrl[2].bit[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) state->Init_Ctrl[2].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) state->Init_Ctrl[3].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) state->Init_Ctrl[3].addr[0] = 53;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) state->Init_Ctrl[3].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) state->Init_Ctrl[3].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) state->Init_Ctrl[4].size = 3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) state->Init_Ctrl[4].addr[0] = 53;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) state->Init_Ctrl[4].bit[0] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) state->Init_Ctrl[4].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) state->Init_Ctrl[4].addr[1] = 53;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) state->Init_Ctrl[4].bit[1] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) state->Init_Ctrl[4].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) state->Init_Ctrl[4].addr[2] = 53;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) state->Init_Ctrl[4].bit[2] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) state->Init_Ctrl[4].val[2] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) state->Init_Ctrl[5].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) state->Init_Ctrl[5].addr[0] = 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) state->Init_Ctrl[5].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) state->Init_Ctrl[5].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) state->Init_Ctrl[6].size = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) state->Init_Ctrl[6].addr[0] = 53;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) state->Init_Ctrl[6].bit[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) state->Init_Ctrl[6].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) state->Init_Ctrl[6].addr[1] = 53;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) state->Init_Ctrl[6].bit[1] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) state->Init_Ctrl[6].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) state->Init_Ctrl[7].size = 4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) state->Init_Ctrl[7].addr[0] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) state->Init_Ctrl[7].bit[0] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) state->Init_Ctrl[7].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) state->Init_Ctrl[7].addr[1] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) state->Init_Ctrl[7].bit[1] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) state->Init_Ctrl[7].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) state->Init_Ctrl[7].addr[2] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) state->Init_Ctrl[7].bit[2] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) state->Init_Ctrl[7].val[2] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) state->Init_Ctrl[7].addr[3] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) state->Init_Ctrl[7].bit[3] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) state->Init_Ctrl[7].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) state->Init_Ctrl[8].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) state->Init_Ctrl[8].addr[0] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) state->Init_Ctrl[8].bit[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) state->Init_Ctrl[8].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) state->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) state->Init_Ctrl[9].size = 4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) state->Init_Ctrl[9].addr[0] = 76;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) state->Init_Ctrl[9].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) state->Init_Ctrl[9].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) state->Init_Ctrl[9].addr[1] = 76;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) state->Init_Ctrl[9].bit[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) state->Init_Ctrl[9].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) state->Init_Ctrl[9].addr[2] = 76;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) state->Init_Ctrl[9].bit[2] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) state->Init_Ctrl[9].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) state->Init_Ctrl[9].addr[3] = 76;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) state->Init_Ctrl[9].bit[3] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) state->Init_Ctrl[9].val[3] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) state->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) state->Init_Ctrl[10].size = 4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) state->Init_Ctrl[10].addr[0] = 76;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) state->Init_Ctrl[10].bit[0] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) state->Init_Ctrl[10].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) state->Init_Ctrl[10].addr[1] = 76;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) state->Init_Ctrl[10].bit[1] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) state->Init_Ctrl[10].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) state->Init_Ctrl[10].addr[2] = 76;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) state->Init_Ctrl[10].bit[2] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) state->Init_Ctrl[10].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) state->Init_Ctrl[10].addr[3] = 76;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) state->Init_Ctrl[10].bit[3] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) state->Init_Ctrl[10].val[3] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) state->Init_Ctrl[11].size = 5 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) state->Init_Ctrl[11].addr[0] = 43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) state->Init_Ctrl[11].bit[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) state->Init_Ctrl[11].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) state->Init_Ctrl[11].addr[1] = 43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) state->Init_Ctrl[11].bit[1] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) state->Init_Ctrl[11].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) state->Init_Ctrl[11].addr[2] = 43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) state->Init_Ctrl[11].bit[2] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) state->Init_Ctrl[11].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) state->Init_Ctrl[11].addr[3] = 43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) state->Init_Ctrl[11].bit[3] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) state->Init_Ctrl[11].val[3] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) state->Init_Ctrl[11].addr[4] = 43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) state->Init_Ctrl[11].bit[4] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) state->Init_Ctrl[11].val[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) state->Init_Ctrl[12].size = 6 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) state->Init_Ctrl[12].addr[0] = 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) state->Init_Ctrl[12].bit[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) state->Init_Ctrl[12].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) state->Init_Ctrl[12].addr[1] = 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) state->Init_Ctrl[12].bit[1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) state->Init_Ctrl[12].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) state->Init_Ctrl[12].addr[2] = 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) state->Init_Ctrl[12].bit[2] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) state->Init_Ctrl[12].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) state->Init_Ctrl[12].addr[3] = 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) state->Init_Ctrl[12].bit[3] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) state->Init_Ctrl[12].val[3] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) state->Init_Ctrl[12].addr[4] = 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) state->Init_Ctrl[12].bit[4] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) state->Init_Ctrl[12].val[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) state->Init_Ctrl[12].addr[5] = 44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) state->Init_Ctrl[12].bit[5] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) state->Init_Ctrl[12].val[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) state->Init_Ctrl[13].size = 7 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) state->Init_Ctrl[13].addr[0] = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) state->Init_Ctrl[13].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) state->Init_Ctrl[13].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) state->Init_Ctrl[13].addr[1] = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) state->Init_Ctrl[13].bit[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) state->Init_Ctrl[13].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) state->Init_Ctrl[13].addr[2] = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) state->Init_Ctrl[13].bit[2] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) state->Init_Ctrl[13].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) state->Init_Ctrl[13].addr[3] = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) state->Init_Ctrl[13].bit[3] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) state->Init_Ctrl[13].val[3] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) state->Init_Ctrl[13].addr[4] = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) state->Init_Ctrl[13].bit[4] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) state->Init_Ctrl[13].val[4] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) state->Init_Ctrl[13].addr[5] = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) state->Init_Ctrl[13].bit[5] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) state->Init_Ctrl[13].val[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) state->Init_Ctrl[13].addr[6] = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) state->Init_Ctrl[13].bit[6] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) state->Init_Ctrl[13].val[6] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) state->Init_Ctrl[14].size = 16 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) state->Init_Ctrl[14].addr[0] = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) state->Init_Ctrl[14].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) state->Init_Ctrl[14].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) state->Init_Ctrl[14].addr[1] = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) state->Init_Ctrl[14].bit[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) state->Init_Ctrl[14].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) state->Init_Ctrl[14].addr[2] = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) state->Init_Ctrl[14].bit[2] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) state->Init_Ctrl[14].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) state->Init_Ctrl[14].addr[3] = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) state->Init_Ctrl[14].bit[3] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) state->Init_Ctrl[14].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) state->Init_Ctrl[14].addr[4] = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) state->Init_Ctrl[14].bit[4] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) state->Init_Ctrl[14].val[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) state->Init_Ctrl[14].addr[5] = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) state->Init_Ctrl[14].bit[5] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) state->Init_Ctrl[14].val[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) state->Init_Ctrl[14].addr[6] = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) state->Init_Ctrl[14].bit[6] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) state->Init_Ctrl[14].val[6] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) state->Init_Ctrl[14].addr[7] = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) state->Init_Ctrl[14].bit[7] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) state->Init_Ctrl[14].val[7] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) state->Init_Ctrl[14].addr[8] = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) state->Init_Ctrl[14].bit[8] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) state->Init_Ctrl[14].val[8] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) state->Init_Ctrl[14].addr[9] = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) state->Init_Ctrl[14].bit[9] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) state->Init_Ctrl[14].val[9] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) state->Init_Ctrl[14].addr[10] = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) state->Init_Ctrl[14].bit[10] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) state->Init_Ctrl[14].val[10] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) state->Init_Ctrl[14].addr[11] = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) state->Init_Ctrl[14].bit[11] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) state->Init_Ctrl[14].val[11] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) state->Init_Ctrl[14].addr[12] = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) state->Init_Ctrl[14].bit[12] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) state->Init_Ctrl[14].val[12] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) state->Init_Ctrl[14].addr[13] = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) state->Init_Ctrl[14].bit[13] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) state->Init_Ctrl[14].val[13] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) state->Init_Ctrl[14].addr[14] = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) state->Init_Ctrl[14].bit[14] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) state->Init_Ctrl[14].val[14] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) state->Init_Ctrl[14].addr[15] = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) state->Init_Ctrl[14].bit[15] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) state->Init_Ctrl[14].val[15] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) state->Init_Ctrl[15].size = 3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) state->Init_Ctrl[15].addr[0] = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) state->Init_Ctrl[15].bit[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) state->Init_Ctrl[15].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) state->Init_Ctrl[15].addr[1] = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) state->Init_Ctrl[15].bit[1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) state->Init_Ctrl[15].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) state->Init_Ctrl[15].addr[2] = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) state->Init_Ctrl[15].bit[2] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) state->Init_Ctrl[15].val[2] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) state->Init_Ctrl[16].size = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) state->Init_Ctrl[16].addr[0] = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) state->Init_Ctrl[16].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) state->Init_Ctrl[16].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) state->Init_Ctrl[16].addr[1] = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) state->Init_Ctrl[16].bit[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) state->Init_Ctrl[16].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) state->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) state->Init_Ctrl[17].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) state->Init_Ctrl[17].addr[0] = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) state->Init_Ctrl[17].bit[0] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) state->Init_Ctrl[17].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) state->Init_Ctrl[18].Ctrl_Num = EN_3P ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) state->Init_Ctrl[18].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) state->Init_Ctrl[18].addr[0] = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) state->Init_Ctrl[18].bit[0] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) state->Init_Ctrl[18].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) state->Init_Ctrl[19].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) state->Init_Ctrl[19].addr[0] = 156;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) state->Init_Ctrl[19].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) state->Init_Ctrl[19].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) state->Init_Ctrl[20].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) state->Init_Ctrl[20].addr[0] = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) state->Init_Ctrl[20].bit[0] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) state->Init_Ctrl[20].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) state->Init_Ctrl[21].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) state->Init_Ctrl[21].addr[0] = 137;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) state->Init_Ctrl[21].bit[0] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) state->Init_Ctrl[21].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) state->Init_Ctrl[22].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) state->Init_Ctrl[22].addr[0] = 137;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) state->Init_Ctrl[22].bit[0] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) state->Init_Ctrl[22].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) state->Init_Ctrl[23].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) state->Init_Ctrl[23].addr[0] = 91;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) state->Init_Ctrl[23].bit[0] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) state->Init_Ctrl[23].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) state->Init_Ctrl[24].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) state->Init_Ctrl[24].addr[0] = 43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) state->Init_Ctrl[24].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) state->Init_Ctrl[24].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) state->Init_Ctrl[25].size = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) state->Init_Ctrl[25].addr[0] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) state->Init_Ctrl[25].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) state->Init_Ctrl[25].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) state->Init_Ctrl[25].addr[1] = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) state->Init_Ctrl[25].bit[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) state->Init_Ctrl[25].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) state->Init_Ctrl[26].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) state->Init_Ctrl[26].addr[0] = 134;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) state->Init_Ctrl[26].bit[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) state->Init_Ctrl[26].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) state->Init_Ctrl[27].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) state->Init_Ctrl[27].addr[0] = 137;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) state->Init_Ctrl[27].bit[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) state->Init_Ctrl[27].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) state->Init_Ctrl[28].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) state->Init_Ctrl[28].addr[0] = 77;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) state->Init_Ctrl[28].bit[0] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) state->Init_Ctrl[28].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) state->Init_Ctrl[29].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) state->Init_Ctrl[29].addr[0] = 166;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) state->Init_Ctrl[29].bit[0] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) state->Init_Ctrl[29].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) state->Init_Ctrl[30].size = 3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) state->Init_Ctrl[30].addr[0] = 166;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) state->Init_Ctrl[30].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) state->Init_Ctrl[30].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) state->Init_Ctrl[30].addr[1] = 166;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) state->Init_Ctrl[30].bit[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) state->Init_Ctrl[30].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) state->Init_Ctrl[30].addr[2] = 166;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) state->Init_Ctrl[30].bit[2] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) state->Init_Ctrl[30].val[2] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) state->Init_Ctrl[31].size = 3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) state->Init_Ctrl[31].addr[0] = 166;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) state->Init_Ctrl[31].bit[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) state->Init_Ctrl[31].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) state->Init_Ctrl[31].addr[1] = 166;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) state->Init_Ctrl[31].bit[1] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) state->Init_Ctrl[31].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) state->Init_Ctrl[31].addr[2] = 166;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) state->Init_Ctrl[31].bit[2] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) state->Init_Ctrl[31].val[2] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) state->Init_Ctrl[32].size = 3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) state->Init_Ctrl[32].addr[0] = 167;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) state->Init_Ctrl[32].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) state->Init_Ctrl[32].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) state->Init_Ctrl[32].addr[1] = 167;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) state->Init_Ctrl[32].bit[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) state->Init_Ctrl[32].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) state->Init_Ctrl[32].addr[2] = 167;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) state->Init_Ctrl[32].bit[2] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) state->Init_Ctrl[32].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) state->Init_Ctrl[33].size = 4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) state->Init_Ctrl[33].addr[0] = 168;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) state->Init_Ctrl[33].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) state->Init_Ctrl[33].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) state->Init_Ctrl[33].addr[1] = 168;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) state->Init_Ctrl[33].bit[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) state->Init_Ctrl[33].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) state->Init_Ctrl[33].addr[2] = 168;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) state->Init_Ctrl[33].bit[2] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) state->Init_Ctrl[33].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) state->Init_Ctrl[33].addr[3] = 168;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) state->Init_Ctrl[33].bit[3] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) state->Init_Ctrl[33].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) state->Init_Ctrl[34].size = 4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) state->Init_Ctrl[34].addr[0] = 168;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) state->Init_Ctrl[34].bit[0] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) state->Init_Ctrl[34].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) state->Init_Ctrl[34].addr[1] = 168;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) state->Init_Ctrl[34].bit[1] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) state->Init_Ctrl[34].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) state->Init_Ctrl[34].addr[2] = 168;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) state->Init_Ctrl[34].bit[2] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) state->Init_Ctrl[34].val[2] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) state->Init_Ctrl[34].addr[3] = 168;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) state->Init_Ctrl[34].bit[3] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) state->Init_Ctrl[34].val[3] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) state->Init_Ctrl[35].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) state->Init_Ctrl[35].addr[0] = 135;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) state->Init_Ctrl[35].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) state->Init_Ctrl[35].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) state->Init_Ctrl[36].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) state->Init_Ctrl[36].addr[0] = 56;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) state->Init_Ctrl[36].bit[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) state->Init_Ctrl[36].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) state->Init_Ctrl[37].size = 7 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) state->Init_Ctrl[37].addr[0] = 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) state->Init_Ctrl[37].bit[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) state->Init_Ctrl[37].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) state->Init_Ctrl[37].addr[1] = 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) state->Init_Ctrl[37].bit[1] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) state->Init_Ctrl[37].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) state->Init_Ctrl[37].addr[2] = 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) state->Init_Ctrl[37].bit[2] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) state->Init_Ctrl[37].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) state->Init_Ctrl[37].addr[3] = 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) state->Init_Ctrl[37].bit[3] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) state->Init_Ctrl[37].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) state->Init_Ctrl[37].addr[4] = 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) state->Init_Ctrl[37].bit[4] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) state->Init_Ctrl[37].val[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) state->Init_Ctrl[37].addr[5] = 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) state->Init_Ctrl[37].bit[5] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) state->Init_Ctrl[37].val[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) state->Init_Ctrl[37].addr[6] = 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) state->Init_Ctrl[37].bit[6] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) state->Init_Ctrl[37].val[6] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) state->Init_Ctrl[38].size = 6 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) state->Init_Ctrl[38].addr[0] = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) state->Init_Ctrl[38].bit[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) state->Init_Ctrl[38].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) state->Init_Ctrl[38].addr[1] = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) state->Init_Ctrl[38].bit[1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) state->Init_Ctrl[38].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) state->Init_Ctrl[38].addr[2] = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) state->Init_Ctrl[38].bit[2] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) state->Init_Ctrl[38].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) state->Init_Ctrl[38].addr[3] = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) state->Init_Ctrl[38].bit[3] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) state->Init_Ctrl[38].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) state->Init_Ctrl[38].addr[4] = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) state->Init_Ctrl[38].bit[4] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) state->Init_Ctrl[38].val[4] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) state->Init_Ctrl[38].addr[5] = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) state->Init_Ctrl[38].bit[5] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) state->Init_Ctrl[38].val[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) state->Init_Ctrl[39].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) state->Init_Ctrl[39].addr[0] = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) state->Init_Ctrl[39].bit[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) state->Init_Ctrl[39].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) state->CH_Ctrl_Num = CHCTRL_NUM ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) state->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) state->CH_Ctrl[0].size = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) state->CH_Ctrl[0].addr[0] = 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) state->CH_Ctrl[0].bit[0] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) state->CH_Ctrl[0].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) state->CH_Ctrl[0].addr[1] = 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) state->CH_Ctrl[0].bit[1] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) state->CH_Ctrl[0].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) state->CH_Ctrl[1].size = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) state->CH_Ctrl[1].addr[0] = 70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) state->CH_Ctrl[1].bit[0] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) state->CH_Ctrl[1].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) state->CH_Ctrl[1].addr[1] = 70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) state->CH_Ctrl[1].bit[1] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) state->CH_Ctrl[1].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) state->CH_Ctrl[2].size = 9 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) state->CH_Ctrl[2].addr[0] = 69;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) state->CH_Ctrl[2].bit[0] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) state->CH_Ctrl[2].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) state->CH_Ctrl[2].addr[1] = 69;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) state->CH_Ctrl[2].bit[1] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) state->CH_Ctrl[2].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) state->CH_Ctrl[2].addr[2] = 69;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) state->CH_Ctrl[2].bit[2] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) state->CH_Ctrl[2].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) state->CH_Ctrl[2].addr[3] = 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) state->CH_Ctrl[2].bit[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) state->CH_Ctrl[2].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) state->CH_Ctrl[2].addr[4] = 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) state->CH_Ctrl[2].bit[4] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) state->CH_Ctrl[2].val[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) state->CH_Ctrl[2].addr[5] = 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) state->CH_Ctrl[2].bit[5] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) state->CH_Ctrl[2].val[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) state->CH_Ctrl[2].addr[6] = 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) state->CH_Ctrl[2].bit[6] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) state->CH_Ctrl[2].val[6] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) state->CH_Ctrl[2].addr[7] = 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) state->CH_Ctrl[2].bit[7] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) state->CH_Ctrl[2].val[7] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) state->CH_Ctrl[2].addr[8] = 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) state->CH_Ctrl[2].bit[8] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) state->CH_Ctrl[2].val[8] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) state->CH_Ctrl[3].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) state->CH_Ctrl[3].addr[0] = 70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) state->CH_Ctrl[3].bit[0] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) state->CH_Ctrl[3].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) state->CH_Ctrl[4].size = 3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) state->CH_Ctrl[4].addr[0] = 73;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) state->CH_Ctrl[4].bit[0] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) state->CH_Ctrl[4].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) state->CH_Ctrl[4].addr[1] = 73;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) state->CH_Ctrl[4].bit[1] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) state->CH_Ctrl[4].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) state->CH_Ctrl[4].addr[2] = 73;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) state->CH_Ctrl[4].bit[2] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) state->CH_Ctrl[4].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) state->CH_Ctrl[5].size = 4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) state->CH_Ctrl[5].addr[0] = 70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) state->CH_Ctrl[5].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) state->CH_Ctrl[5].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) state->CH_Ctrl[5].addr[1] = 70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) state->CH_Ctrl[5].bit[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) state->CH_Ctrl[5].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) state->CH_Ctrl[5].addr[2] = 70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) state->CH_Ctrl[5].bit[2] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) state->CH_Ctrl[5].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) state->CH_Ctrl[5].addr[3] = 70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) state->CH_Ctrl[5].bit[3] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) state->CH_Ctrl[5].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) state->CH_Ctrl[6].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) state->CH_Ctrl[6].addr[0] = 70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) state->CH_Ctrl[6].bit[0] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) state->CH_Ctrl[6].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) state->CH_Ctrl[7].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) state->CH_Ctrl[7].addr[0] = 111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) state->CH_Ctrl[7].bit[0] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) state->CH_Ctrl[7].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) state->CH_Ctrl[8].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) state->CH_Ctrl[8].addr[0] = 111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) state->CH_Ctrl[8].bit[0] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) state->CH_Ctrl[8].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) state->CH_Ctrl[9].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) state->CH_Ctrl[9].addr[0] = 111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) state->CH_Ctrl[9].bit[0] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) state->CH_Ctrl[9].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) state->CH_Ctrl[10].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) state->CH_Ctrl[10].addr[0] = 111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) state->CH_Ctrl[10].bit[0] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) state->CH_Ctrl[10].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) state->CH_Ctrl[11].size = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) state->CH_Ctrl[11].addr[0] = 110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) state->CH_Ctrl[11].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) state->CH_Ctrl[11].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) state->CH_Ctrl[11].addr[1] = 110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) state->CH_Ctrl[11].bit[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) state->CH_Ctrl[11].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) state->CH_Ctrl[12].size = 3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) state->CH_Ctrl[12].addr[0] = 69;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) state->CH_Ctrl[12].bit[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) state->CH_Ctrl[12].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) state->CH_Ctrl[12].addr[1] = 69;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) state->CH_Ctrl[12].bit[1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) state->CH_Ctrl[12].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) state->CH_Ctrl[12].addr[2] = 69;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) state->CH_Ctrl[12].bit[2] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) state->CH_Ctrl[12].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) state->CH_Ctrl[13].size = 6 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) state->CH_Ctrl[13].addr[0] = 110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) state->CH_Ctrl[13].bit[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) state->CH_Ctrl[13].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) state->CH_Ctrl[13].addr[1] = 110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) state->CH_Ctrl[13].bit[1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) state->CH_Ctrl[13].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) state->CH_Ctrl[13].addr[2] = 110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) state->CH_Ctrl[13].bit[2] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) state->CH_Ctrl[13].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) state->CH_Ctrl[13].addr[3] = 110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) state->CH_Ctrl[13].bit[3] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) state->CH_Ctrl[13].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) state->CH_Ctrl[13].addr[4] = 110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) state->CH_Ctrl[13].bit[4] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) state->CH_Ctrl[13].val[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) state->CH_Ctrl[13].addr[5] = 110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) state->CH_Ctrl[13].bit[5] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) state->CH_Ctrl[13].val[5] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) state->CH_Ctrl[14].size = 7 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) state->CH_Ctrl[14].addr[0] = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) state->CH_Ctrl[14].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) state->CH_Ctrl[14].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) state->CH_Ctrl[14].addr[1] = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) state->CH_Ctrl[14].bit[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) state->CH_Ctrl[14].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) state->CH_Ctrl[14].addr[2] = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) state->CH_Ctrl[14].bit[2] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) state->CH_Ctrl[14].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) state->CH_Ctrl[14].addr[3] = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) state->CH_Ctrl[14].bit[3] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) state->CH_Ctrl[14].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) state->CH_Ctrl[14].addr[4] = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) state->CH_Ctrl[14].bit[4] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) state->CH_Ctrl[14].val[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) state->CH_Ctrl[14].addr[5] = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) state->CH_Ctrl[14].bit[5] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) state->CH_Ctrl[14].val[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) state->CH_Ctrl[14].addr[6] = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) state->CH_Ctrl[14].bit[6] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) state->CH_Ctrl[14].val[6] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) state->CH_Ctrl[15].size = 18 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) state->CH_Ctrl[15].addr[0] = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) state->CH_Ctrl[15].bit[0] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) state->CH_Ctrl[15].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) state->CH_Ctrl[15].addr[1] = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) state->CH_Ctrl[15].bit[1] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) state->CH_Ctrl[15].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) state->CH_Ctrl[15].addr[2] = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) state->CH_Ctrl[15].bit[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) state->CH_Ctrl[15].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) state->CH_Ctrl[15].addr[3] = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) state->CH_Ctrl[15].bit[3] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) state->CH_Ctrl[15].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) state->CH_Ctrl[15].addr[4] = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) state->CH_Ctrl[15].bit[4] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) state->CH_Ctrl[15].val[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) state->CH_Ctrl[15].addr[5] = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) state->CH_Ctrl[15].bit[5] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) state->CH_Ctrl[15].val[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) state->CH_Ctrl[15].addr[6] = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) state->CH_Ctrl[15].bit[6] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) state->CH_Ctrl[15].val[6] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) state->CH_Ctrl[15].addr[7] = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) state->CH_Ctrl[15].bit[7] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) state->CH_Ctrl[15].val[7] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) state->CH_Ctrl[15].addr[8] = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) state->CH_Ctrl[15].bit[8] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) state->CH_Ctrl[15].val[8] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) state->CH_Ctrl[15].addr[9] = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) state->CH_Ctrl[15].bit[9] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) state->CH_Ctrl[15].val[9] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) state->CH_Ctrl[15].addr[10] = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) state->CH_Ctrl[15].bit[10] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) state->CH_Ctrl[15].val[10] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) state->CH_Ctrl[15].addr[11] = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) state->CH_Ctrl[15].bit[11] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) state->CH_Ctrl[15].val[11] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) state->CH_Ctrl[15].addr[12] = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) state->CH_Ctrl[15].bit[12] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) state->CH_Ctrl[15].val[12] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) state->CH_Ctrl[15].addr[13] = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) state->CH_Ctrl[15].bit[13] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) state->CH_Ctrl[15].val[13] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) state->CH_Ctrl[15].addr[14] = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) state->CH_Ctrl[15].bit[14] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) state->CH_Ctrl[15].val[14] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) state->CH_Ctrl[15].addr[15] = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) state->CH_Ctrl[15].bit[15] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) state->CH_Ctrl[15].val[15] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) state->CH_Ctrl[15].addr[16] = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) state->CH_Ctrl[15].bit[16] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) state->CH_Ctrl[15].val[16] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) state->CH_Ctrl[15].addr[17] = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) state->CH_Ctrl[15].bit[17] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) state->CH_Ctrl[15].val[17] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) state->CH_Ctrl[16].size = 5 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) state->CH_Ctrl[16].addr[0] = 112;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) state->CH_Ctrl[16].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) state->CH_Ctrl[16].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) state->CH_Ctrl[16].addr[1] = 112;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) state->CH_Ctrl[16].bit[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) state->CH_Ctrl[16].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) state->CH_Ctrl[16].addr[2] = 112;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) state->CH_Ctrl[16].bit[2] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) state->CH_Ctrl[16].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) state->CH_Ctrl[16].addr[3] = 112;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) state->CH_Ctrl[16].bit[3] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) state->CH_Ctrl[16].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) state->CH_Ctrl[16].addr[4] = 112;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) state->CH_Ctrl[16].bit[4] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) state->CH_Ctrl[16].val[4] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) state->CH_Ctrl[17].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) state->CH_Ctrl[17].addr[0] = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) state->CH_Ctrl[17].bit[0] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) state->CH_Ctrl[17].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) state->CH_Ctrl[18].size = 4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) state->CH_Ctrl[18].addr[0] = 107;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) state->CH_Ctrl[18].bit[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) state->CH_Ctrl[18].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) state->CH_Ctrl[18].addr[1] = 107;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) state->CH_Ctrl[18].bit[1] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) state->CH_Ctrl[18].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) state->CH_Ctrl[18].addr[2] = 107;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) state->CH_Ctrl[18].bit[2] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) state->CH_Ctrl[18].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) state->CH_Ctrl[18].addr[3] = 107;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) state->CH_Ctrl[18].bit[3] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) state->CH_Ctrl[18].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) state->CH_Ctrl[19].size = 3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) state->CH_Ctrl[19].addr[0] = 107;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) state->CH_Ctrl[19].bit[0] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) state->CH_Ctrl[19].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) state->CH_Ctrl[19].addr[1] = 106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) state->CH_Ctrl[19].bit[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) state->CH_Ctrl[19].val[1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) state->CH_Ctrl[19].addr[2] = 106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) state->CH_Ctrl[19].bit[2] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) state->CH_Ctrl[19].val[2] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) state->CH_Ctrl[20].size = 11 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) state->CH_Ctrl[20].addr[0] = 109;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) state->CH_Ctrl[20].bit[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) state->CH_Ctrl[20].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) state->CH_Ctrl[20].addr[1] = 109;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) state->CH_Ctrl[20].bit[1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) state->CH_Ctrl[20].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) state->CH_Ctrl[20].addr[2] = 109;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) state->CH_Ctrl[20].bit[2] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) state->CH_Ctrl[20].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) state->CH_Ctrl[20].addr[3] = 109;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) state->CH_Ctrl[20].bit[3] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) state->CH_Ctrl[20].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) state->CH_Ctrl[20].addr[4] = 109;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) state->CH_Ctrl[20].bit[4] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) state->CH_Ctrl[20].val[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) state->CH_Ctrl[20].addr[5] = 109;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) state->CH_Ctrl[20].bit[5] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) state->CH_Ctrl[20].val[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) state->CH_Ctrl[20].addr[6] = 108;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) state->CH_Ctrl[20].bit[6] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) state->CH_Ctrl[20].val[6] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) state->CH_Ctrl[20].addr[7] = 108;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) state->CH_Ctrl[20].bit[7] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) state->CH_Ctrl[20].val[7] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) state->CH_Ctrl[20].addr[8] = 108;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) state->CH_Ctrl[20].bit[8] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) state->CH_Ctrl[20].val[8] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) state->CH_Ctrl[20].addr[9] = 108;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) state->CH_Ctrl[20].bit[9] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) state->CH_Ctrl[20].val[9] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) state->CH_Ctrl[20].addr[10] = 108;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) state->CH_Ctrl[20].bit[10] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) state->CH_Ctrl[20].val[10] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) state->CH_Ctrl[21].size = 6 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) state->CH_Ctrl[21].addr[0] = 106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) state->CH_Ctrl[21].bit[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) state->CH_Ctrl[21].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) state->CH_Ctrl[21].addr[1] = 106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) state->CH_Ctrl[21].bit[1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) state->CH_Ctrl[21].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) state->CH_Ctrl[21].addr[2] = 106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) state->CH_Ctrl[21].bit[2] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) state->CH_Ctrl[21].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) state->CH_Ctrl[21].addr[3] = 106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) state->CH_Ctrl[21].bit[3] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) state->CH_Ctrl[21].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) state->CH_Ctrl[21].addr[4] = 106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) state->CH_Ctrl[21].bit[4] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) state->CH_Ctrl[21].val[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) state->CH_Ctrl[21].addr[5] = 106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) state->CH_Ctrl[21].bit[5] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) state->CH_Ctrl[21].val[5] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) state->CH_Ctrl[22].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) state->CH_Ctrl[22].addr[0] = 138;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) state->CH_Ctrl[22].bit[0] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) state->CH_Ctrl[22].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) state->CH_Ctrl[23].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) state->CH_Ctrl[23].addr[0] = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) state->CH_Ctrl[23].bit[0] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) state->CH_Ctrl[23].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) state->CH_Ctrl[24].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) state->CH_Ctrl[24].addr[0] = 111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) state->CH_Ctrl[24].bit[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) state->CH_Ctrl[24].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) state->CH_Ctrl[25].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) state->CH_Ctrl[25].addr[0] = 112;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) state->CH_Ctrl[25].bit[0] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) state->CH_Ctrl[25].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) state->CH_Ctrl[26].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) state->CH_Ctrl[26].addr[0] = 136;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) state->CH_Ctrl[26].bit[0] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) state->CH_Ctrl[26].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) state->CH_Ctrl[27].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) state->CH_Ctrl[27].addr[0] = 149;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) state->CH_Ctrl[27].bit[0] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) state->CH_Ctrl[27].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) state->CH_Ctrl[28].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) state->CH_Ctrl[28].addr[0] = 149;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) state->CH_Ctrl[28].bit[0] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) state->CH_Ctrl[28].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) state->CH_Ctrl[29].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) state->CH_Ctrl[29].addr[0] = 149;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) state->CH_Ctrl[29].bit[0] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) state->CH_Ctrl[29].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) state->CH_Ctrl[30].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) state->CH_Ctrl[30].addr[0] = 149;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) state->CH_Ctrl[30].bit[0] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) state->CH_Ctrl[30].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) state->CH_Ctrl[31].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) state->CH_Ctrl[31].addr[0] = 149;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) state->CH_Ctrl[31].bit[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) state->CH_Ctrl[31].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) state->CH_Ctrl[32].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) state->CH_Ctrl[32].addr[0] = 93;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) state->CH_Ctrl[32].bit[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) state->CH_Ctrl[32].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) state->CH_Ctrl[33].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) state->CH_Ctrl[33].addr[0] = 93;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) state->CH_Ctrl[33].bit[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) state->CH_Ctrl[33].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) state->CH_Ctrl[34].size = 6 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) state->CH_Ctrl[34].addr[0] = 92;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) state->CH_Ctrl[34].bit[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) state->CH_Ctrl[34].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) state->CH_Ctrl[34].addr[1] = 92;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) state->CH_Ctrl[34].bit[1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) state->CH_Ctrl[34].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) state->CH_Ctrl[34].addr[2] = 92;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) state->CH_Ctrl[34].bit[2] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) state->CH_Ctrl[34].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) state->CH_Ctrl[34].addr[3] = 92;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) state->CH_Ctrl[34].bit[3] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) state->CH_Ctrl[34].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) state->CH_Ctrl[34].addr[4] = 92;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) state->CH_Ctrl[34].bit[4] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) state->CH_Ctrl[34].val[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) state->CH_Ctrl[34].addr[5] = 92;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) state->CH_Ctrl[34].bit[5] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) state->CH_Ctrl[34].val[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) state->CH_Ctrl[35].size = 6 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) state->CH_Ctrl[35].addr[0] = 93;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) state->CH_Ctrl[35].bit[0] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) state->CH_Ctrl[35].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) state->CH_Ctrl[35].addr[1] = 93;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) state->CH_Ctrl[35].bit[1] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) state->CH_Ctrl[35].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) state->CH_Ctrl[35].addr[2] = 93;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) state->CH_Ctrl[35].bit[2] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) state->CH_Ctrl[35].val[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) state->CH_Ctrl[35].addr[3] = 93;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) state->CH_Ctrl[35].bit[3] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) state->CH_Ctrl[35].val[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) state->CH_Ctrl[35].addr[4] = 93;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) state->CH_Ctrl[35].bit[4] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) state->CH_Ctrl[35].val[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) state->CH_Ctrl[35].addr[5] = 93;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) state->CH_Ctrl[35].bit[5] = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) state->CH_Ctrl[35].val[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #ifdef _MXL_PRODUCTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) state->CH_Ctrl[36].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) state->CH_Ctrl[36].addr[0] = 109;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) state->CH_Ctrl[36].bit[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) state->CH_Ctrl[36].val[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) state->CH_Ctrl[37].size = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) state->CH_Ctrl[37].addr[0] = 112;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) state->CH_Ctrl[37].bit[0] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) state->CH_Ctrl[37].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) state->CH_Ctrl[37].addr[1] = 112;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) state->CH_Ctrl[37].bit[1] = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) state->CH_Ctrl[37].val[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) state->CH_Ctrl[38].size = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) state->CH_Ctrl[38].addr[0] = 65;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) state->CH_Ctrl[38].bit[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) state->CH_Ctrl[38].val[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static void InitTunerControls(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) MXL5005_RegisterInit(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) MXL5005_ControlInit(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #ifdef _MXL_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) MXL5005_MXLControlInit(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) u32 IF_out, /* Desired IF Out Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) u32 Fxtal, /* XTAL Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) u16 TOP, /* 0: Dual AGC; Value: take over point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) /* Modulation Type; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) u8 Mod_Type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) /* Tracking Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) u8 TF_Type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) state->Mode = Mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) state->IF_Mode = IF_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) state->Chan_Bandwidth = Bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) state->IF_OUT = IF_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) state->Fxtal = Fxtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) state->AGC_Mode = AGC_Mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) state->TOP = TOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) state->IF_OUT_LOAD = IF_OUT_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) state->CLOCK_OUT = CLOCK_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) state->DIV_OUT = DIV_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) state->CAPSELECT = CAPSELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) state->EN_RSSI = EN_RSSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) state->Mod_Type = Mod_Type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) state->TF_Type = TF_Type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* Initialize all the controls and registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) InitTunerControls(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /* Synthesizer LO frequency calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) MXL_SynthIFLO_Calc(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (state->Mode == 1) /* Digital Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) state->IF_LO = state->IF_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) else /* Analog Mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (state->IF_Mode == 0) /* Analog Zero IF mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) state->IF_LO = state->IF_OUT + 400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) else /* Analog Low IF mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (state->Mode == 1) /* Digital Mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /* remove 20.48MHz setting for 2.6.10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) state->RF_LO = state->RF_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /* change for 2.6.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) state->TG_LO = state->RF_IN - 750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) } else /* Analog Mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (state->IF_Mode == 0) /* Analog Zero IF mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) state->RF_LO = state->RF_IN - 400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) state->TG_LO = state->RF_IN - 1750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) } else /* Analog Low IF mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) state->TG_LO = state->RF_IN -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) state->Chan_Bandwidth + 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) status += MXL_ControlWrite(fe, OVERRIDE_1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) status += MXL_ControlWrite(fe, OVERRIDE_2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) status += MXL_ControlWrite(fe, OVERRIDE_3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) status += MXL_ControlWrite(fe, OVERRIDE_4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static u16 MXL_BlockInit(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) status += MXL_OverwriteICDefault(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* Downconverter Control Dig Ana */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) /* Filter Control Dig Ana */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /* Initialize Low-Pass Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (state->Mode) { /* Digital Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) switch (state->Chan_Bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) BB_DLPF_BANDSEL, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) } else { /* Analog Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) switch (state->Chan_Bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) case 8000000: /* Low Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) (state->IF_Mode ? 0 : 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) (state->IF_Mode ? 1 : 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) (state->IF_Mode ? 2 : 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* Charge Pump Control Dig Ana */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) /* AGC TOP Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if (state->AGC_Mode == 0) /* Dual AGC */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) status += MXL_ControlWrite(fe, AGC_IF, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) status += MXL_ControlWrite(fe, AGC_RF, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) } else /* Single AGC Mode Dig Ana */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (state->TOP == 55) /* TOP == 5.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) status += MXL_ControlWrite(fe, AGC_IF, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (state->TOP == 72) /* TOP == 7.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) status += MXL_ControlWrite(fe, AGC_IF, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) if (state->TOP == 92) /* TOP == 9.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) status += MXL_ControlWrite(fe, AGC_IF, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (state->TOP == 110) /* TOP == 11.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) status += MXL_ControlWrite(fe, AGC_IF, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (state->TOP == 129) /* TOP == 12.9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) status += MXL_ControlWrite(fe, AGC_IF, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (state->TOP == 147) /* TOP == 14.7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) status += MXL_ControlWrite(fe, AGC_IF, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (state->TOP == 168) /* TOP == 16.8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) status += MXL_ControlWrite(fe, AGC_IF, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (state->TOP == 194) /* TOP == 19.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) status += MXL_ControlWrite(fe, AGC_IF, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (state->TOP == 212) /* TOP == 21.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) status += MXL_ControlWrite(fe, AGC_IF, 0x9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (state->TOP == 232) /* TOP == 23.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) status += MXL_ControlWrite(fe, AGC_IF, 0xA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (state->TOP == 252) /* TOP == 25.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) status += MXL_ControlWrite(fe, AGC_IF, 0xB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (state->TOP == 271) /* TOP == 27.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) status += MXL_ControlWrite(fe, AGC_IF, 0xC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (state->TOP == 292) /* TOP == 29.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) status += MXL_ControlWrite(fe, AGC_IF, 0xD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (state->TOP == 317) /* TOP == 31.7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) status += MXL_ControlWrite(fe, AGC_IF, 0xE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) if (state->TOP == 349) /* TOP == 34.9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) status += MXL_ControlWrite(fe, AGC_IF, 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) /* IF Synthesizer Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) status += MXL_IFSynthInit(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) /* IF UpConverter Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (state->IF_OUT_LOAD == 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) status += MXL_ControlWrite(fe, DRV_RES_SEL, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) status += MXL_ControlWrite(fe, I_DRIVER, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) if (state->IF_OUT_LOAD == 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) status += MXL_ControlWrite(fe, DRV_RES_SEL, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) status += MXL_ControlWrite(fe, I_DRIVER, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /* Anti-Alias Filtering Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) * initialise Anti-Aliasing Filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (state->Mode) { /* Digital Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) status += MXL_ControlWrite(fe, EN_AAF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) status += MXL_ControlWrite(fe, EN_3P, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if ((state->IF_OUT == 36125000UL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) (state->IF_OUT == 36150000UL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) status += MXL_ControlWrite(fe, EN_AAF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) status += MXL_ControlWrite(fe, EN_3P, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) if (state->IF_OUT > 36150000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) status += MXL_ControlWrite(fe, EN_AAF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) status += MXL_ControlWrite(fe, EN_3P, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) } else { /* Analog Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) status += MXL_ControlWrite(fe, EN_AAF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) status += MXL_ControlWrite(fe, EN_3P, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (state->IF_OUT > 5000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) status += MXL_ControlWrite(fe, EN_AAF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) status += MXL_ControlWrite(fe, EN_3P, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) /* Demod Clock Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) if (state->CLOCK_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (state->DIV_OUT == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (state->DIV_OUT == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) /* Crystal Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (state->CAPSELECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) status += MXL_ControlWrite(fe, IF_SEL_DBL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) status += MXL_ControlWrite(fe, IF_SEL_DBL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /* Misc Controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /* Set TG_R_DIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) status += MXL_ControlWrite(fe, TG_R_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) MXL_Ceiling(state->Fxtal, 1000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* Apply Default value to BB_INITSTATE_DLPF_TUNE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) /* RSSI Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if (state->EN_RSSI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) /* RSSI reference point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) /* TOP point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) status += MXL_ControlWrite(fe, RFA_FLR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) status += MXL_ControlWrite(fe, RFA_CEIL, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) /* Modulation type bit settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) * Override the control values preset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) state->AGC_Mode = 1; /* Single AGC Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) /* Enable RSSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) /* RSSI reference point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* TOP point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) status += MXL_ControlWrite(fe, RFA_FLR, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) status += MXL_ControlWrite(fe, RFA_CEIL, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (state->IF_OUT <= 6280000UL) /* Low IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) else /* High IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) state->AGC_Mode = 1; /* Single AGC Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) /* Enable RSSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) /* RSSI reference point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* TOP point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) status += MXL_ControlWrite(fe, RFA_FLR, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) status += MXL_ControlWrite(fe, RFA_CEIL, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) /* Low Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) if (state->IF_OUT <= 6280000UL) /* Low IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) else /* High IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (state->Mod_Type == MXL_QAM) /* QAM Mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) state->Mode = MXL_DIGITAL_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) /* state->AGC_Mode = 1; */ /* Single AGC Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* Disable RSSI */ /* change here for v2.6.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /* RSSI reference point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) /* change here for v2.6.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (state->IF_OUT <= 6280000UL) /* Low IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) else /* High IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (state->Mod_Type == MXL_ANALOG_CABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) /* Analog Cable Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) /* state->Mode = MXL_DIGITAL_MODE; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) state->AGC_Mode = 1; /* Single AGC Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /* Disable RSSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) /* change for 2.6.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) status += MXL_ControlWrite(fe, AGC_IF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) status += MXL_ControlWrite(fe, AGC_RF, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (state->Mod_Type == MXL_ANALOG_OTA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) /* Analog OTA Terrestrial mode add for 2.6.7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) /* state->Mode = MXL_ANALOG_MODE; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) /* Enable RSSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) /* RSSI reference point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) /* RSSI disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if (state->EN_RSSI == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) static u16 MXL_IFSynthInit(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) u16 status = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) u32 Fref = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) u32 Kdbl, intModVal ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) u32 fracModVal ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) Kdbl = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) Kdbl = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) Kdbl = 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) /* IF Synthesizer Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (state->IF_LO == 41000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) Fref = 328000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if (state->IF_LO == 47000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) Fref = 376000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) if (state->IF_LO == 54000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) Fref = 324000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (state->IF_LO == 60000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) Fref = 360000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (state->IF_LO == 39250000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) Fref = 314000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if (state->IF_LO == 39650000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) Fref = 317200000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) if (state->IF_LO == 40150000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) Fref = 321200000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) if (state->IF_LO == 40650000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) Fref = 325200000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if (state->IF_LO == 57000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) Fref = 342000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if (state->IF_LO == 44000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) Fref = 352000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) if (state->IF_LO == 43750000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) Fref = 350000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) if (state->IF_LO == 36650000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) Fref = 366500000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) if (state->IF_LO == 36150000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) Fref = 361500000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) if (state->IF_LO == 36000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) Fref = 360000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (state->IF_LO == 35250000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) Fref = 352500000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if (state->IF_LO == 34750000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) Fref = 347500000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) if (state->IF_LO == 6280000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) Fref = 376800000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (state->IF_LO == 5000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) Fref = 360000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) if (state->IF_LO == 4500000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) Fref = 360000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) if (state->IF_LO == 4570000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) Fref = 365600000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) if (state->IF_LO == 4000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) Fref = 360000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) if (state->IF_LO == 57400000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) Fref = 344400000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (state->IF_LO == 44400000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) Fref = 355200000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) if (state->IF_LO == 44150000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) Fref = 353200000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) if (state->IF_LO == 37050000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) Fref = 370500000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) if (state->IF_LO == 36550000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) Fref = 365500000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) if (state->IF_LO == 36125000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) Fref = 361250000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) if (state->IF_LO == 6000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) Fref = 360000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) if (state->IF_LO == 5400000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) Fref = 324000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (state->IF_LO == 5380000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) Fref = 322800000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) if (state->IF_LO == 5200000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) Fref = 374400000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) if (state->IF_LO == 4900000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) Fref = 352800000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) if (state->IF_LO == 4400000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) Fref = 352000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) Fref = 365670000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) /* CHCAL_INT_MOD_IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) /* CHCAL_FRAC_MOD_IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) intModVal = Fref / (state->Fxtal * Kdbl/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) intModVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) return status ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) u32 divider_val, E3, E4, E5, E5A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) u32 Fmax, Fmin, FmaxBin, FminBin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) u32 Kdbl_RF = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) u32 tg_divval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) u32 tg_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) u32 Fref_TG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) u32 Fvco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) state->RF_IN = RF_Freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) MXL_SynthRFTGLO_Calc(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) Kdbl_RF = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) if (state->Fxtal > 22000000 && state->Fxtal <= 32000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) Kdbl_RF = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) /* Downconverter Controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) * Look-Up Table Implementation for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) * DN_POLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) * DN_RFGAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) * DN_CAP_RFLPF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) * DN_EN_VHFUHFBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) * DN_GAIN_ADJUST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) * Change the boundary reference from RF_IN to RF_LO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) if (state->RF_LO < 40000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) status += MXL_ControlWrite(fe, DN_POLY, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) status += MXL_ControlWrite(fe, DN_POLY, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) status += MXL_ControlWrite(fe, DN_POLY, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) status += MXL_ControlWrite(fe, DN_POLY, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) status += MXL_ControlWrite(fe, DN_POLY, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) status += MXL_ControlWrite(fe, DN_POLY, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) status += MXL_ControlWrite(fe, DN_RFGAIN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) status += MXL_ControlWrite(fe, DN_POLY, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) status += MXL_ControlWrite(fe, DN_RFGAIN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) if (state->RF_LO > 900000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) /* DN_IQTNBUF_AMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) /* DN_IQTNGNBFBIAS_BST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) * Set RF Synth and LO Path Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) * Look-Up table implementation for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) * RFSYN_EN_OUTMUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) * RFSYN_SEL_VCO_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) * RFSYN_SEL_VCO_HI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) * RFSYN_SEL_DIVM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) * RFSYN_RF_DIV_BIAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) * DN_SEL_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) * Set divider_val, Fmax, Fmix to use in Equations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) FminBin = 28000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) FmaxBin = 42500000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) divider_val = 64 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) FminBin = 42500000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) FmaxBin = 56000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) divider_val = 64 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) FminBin = 56000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) FmaxBin = 85000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) divider_val = 32 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) FminBin = 85000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) FmaxBin = 112000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) divider_val = 32 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) FminBin = 112000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) FmaxBin = 170000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) divider_val = 16 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) FminBin = 170000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) FmaxBin = 225000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) divider_val = 16 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) FminBin = 225000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) FmaxBin = 300000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) divider_val = 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) Fmax = 340000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) FminBin = 300000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) FmaxBin = 340000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) divider_val = 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) Fmin = 225000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) FminBin = 340000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) FmaxBin = 450000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) divider_val = 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) FminBin = 450000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) FmaxBin = 680000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) divider_val = 4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) FminBin = 680000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) FmaxBin = 900000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) divider_val = 4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) /* CHCAL_INT_MOD_RF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) * CHCAL_FRAC_MOD_RF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) * RFSYN_LPF_R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) * CHCAL_EN_INT_RF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) /* Equation E3 RFSYN_VCO_BIAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) /* Equation E4 CHCAL_INT_MOD_RF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) /* Equation E5 CHCAL_FRAC_MOD_RF CHCAL_EN_INT_RF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) E5 = ((2<<17)*(state->RF_LO/10000*divider_val -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) (E4*(2*state->Fxtal*Kdbl_RF)/10000))) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) (2*state->Fxtal*Kdbl_RF/10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) /* Equation E5A RFSYN_LPF_R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) /* Euqation E5B CHCAL_EN_INIT_RF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) /*if (E5 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) * status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) *else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) * status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) * Set TG Synth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) * Look-Up table implementation for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) * TG_LO_DIVVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) * TG_LO_SELVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) * Set divider_val, Fmax, Fmix to use in Equations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) if (state->TG_LO < 33000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) FminBin = 33000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) FmaxBin = 50000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) divider_val = 36 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) FminBin = 50000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) FmaxBin = 67000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) divider_val = 24 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) FminBin = 67000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) FmaxBin = 100000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) divider_val = 18 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) FminBin = 100000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) FmaxBin = 150000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) divider_val = 12 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) FminBin = 150000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) FmaxBin = 200000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) divider_val = 8 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) FminBin = 200000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) FmaxBin = 300000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) divider_val = 6 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) FminBin = 300000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) FmaxBin = 400000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) divider_val = 4 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) FminBin = 400000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) FmaxBin = 600000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) divider_val = 3 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) Fmax = FmaxBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) Fmin = FminBin ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) FminBin = 600000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) FmaxBin = 900000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) divider_val = 2 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) /* TG_DIV_VAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) tg_divval = (state->TG_LO*divider_val/100000) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) (MXL_Ceiling(state->Fxtal, 1000000) * 100) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) (state->Fxtal/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) if (state->TG_LO > 600000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) Fmax = 1800000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) Fmin = 1200000000UL ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) /* prevent overflow of 32 bit unsigned integer, use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) * following equation. Edit for v2.6.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) /* Fref_TF = Fref_TG * 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) /* Fvco = Fvco/10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) Fvco = (state->TG_LO/10000) * divider_val * Fref_TG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) /* below equation is same as above but much harder to debug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) * static u32 MXL_GetXtalInt(u32 Xtal_Freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) * {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) * if ((Xtal_Freq % 1000000) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) * return (Xtal_Freq / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) * else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) * return (((Xtal_Freq / 1000000) + 1)*100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) * u32 Xtal_Int = MXL_GetXtalInt(state->Fxtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) * tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) * ((state->TG_LO/10000)*divider_val *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) * Xtal_Int/100) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) /* add for 2.6.5 Special setting for QAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) if (state->Mod_Type == MXL_QAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) if (state->config->qam_gain != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) state->config->qam_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) else if (state->RF_IN < 680000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) /* Off Chip Tracking Filter Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) if (state->TF_Type == MXL_TF_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) /* Tracking Filter Off State; turn off all the banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) status += MXL_ControlWrite(fe, DAC_DIN_B, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) status += MXL_ControlWrite(fe, DAC_DIN_B, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) status += MXL_ControlWrite(fe, DAC_DIN_B, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) if (state->TF_Type == MXL_TF_C_H) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) /* Tracking Filter type C-H for Hauppauge only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) if (state->TF_Type == MXL_TF_D_L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) /* Tracking Filter type D-L for Lumanate ONLY change 2.6.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) /* if UHF and terrestrial => Turn off Tracking Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) if (state->RF_IN >= 471000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) (state->RF_IN - 471000000)%6000000 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) /* Turn off all the banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) status += MXL_ControlWrite(fe, AGC_IF, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) /* if VHF or cable => Turn on Tracking Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) if (state->RF_IN >= 43000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) state->RF_IN < 140000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) if (state->RF_IN >= 140000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) state->RF_IN < 240000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) if (state->RF_IN >= 240000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) state->RF_IN < 340000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) if (state->RF_IN >= 340000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) state->RF_IN < 430000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) if (state->RF_IN >= 430000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) state->RF_IN < 470000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) if (state->RF_IN >= 470000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) state->RF_IN < 570000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) if (state->RF_IN >= 570000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) state->RF_IN < 620000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) if (state->RF_IN >= 620000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) state->RF_IN < 760000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) if (state->RF_IN >= 760000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) state->RF_IN <= 900000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) if (state->TF_Type == MXL_TF_F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) /* Tracking Filter type F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) if (state->TF_Type == MXL_TF_E_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) /* Tracking Filter type E_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) if (state->TF_Type == MXL_TF_G) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) /* Tracking Filter type G add for v2.6.8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) if (state->TF_Type == MXL_TF_E_NA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) /* Tracking Filter type E-NA for Empia ONLY change for 2.6.8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) /* if UHF and terrestrial=> Turn off Tracking Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) if (state->RF_IN >= 471000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) (state->RF_IN - 471000000)%6000000 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) /* Turn off all the banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) /* 2.6.12 Turn on RSSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) /* RSSI reference point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) /* following parameter is from analog OTA mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) * can be change to seek better performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) /* if VHF or Cable => Turn on Tracking Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) /* 2.6.12 Turn off RSSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) /* change back from above condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) status += MXL_SetGPIO(fe, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) status += MXL_SetGPIO(fe, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) status += MXL_SetGPIO(fe, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) status += MXL_SetGPIO(fe, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) status += MXL_SetGPIO(fe, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) status += MXL_SetGPIO(fe, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) return status ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) if (GPIO_Num == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) /* GPIO2 is not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) if (GPIO_Num == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) if (GPIO_Val == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) status += MXL_ControlWrite(fe, GPIO_3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) status += MXL_ControlWrite(fe, GPIO_3B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) if (GPIO_Val == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) status += MXL_ControlWrite(fe, GPIO_3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) status += MXL_ControlWrite(fe, GPIO_3B, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) if (GPIO_Val == 3) { /* tri-state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) status += MXL_ControlWrite(fe, GPIO_3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) status += MXL_ControlWrite(fe, GPIO_3B, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) if (GPIO_Num == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) if (GPIO_Val == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) status += MXL_ControlWrite(fe, GPIO_4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) status += MXL_ControlWrite(fe, GPIO_4B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) if (GPIO_Val == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) status += MXL_ControlWrite(fe, GPIO_4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) status += MXL_ControlWrite(fe, GPIO_4B, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) if (GPIO_Val == 3) { /* tri-state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) status += MXL_ControlWrite(fe, GPIO_4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) status += MXL_ControlWrite(fe, GPIO_4B, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) /* Will write ALL Matching Control Name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) /* Write Matching INIT Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) status += MXL_ControlWrite_Group(fe, ControlNum, value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) /* Write Matching CH Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) status += MXL_ControlWrite_Group(fe, ControlNum, value, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) #ifdef _MXL_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) /* Write Matching MXL Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) status += MXL_ControlWrite_Group(fe, ControlNum, value, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) u32 value, u16 controlGroup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) u16 i, j, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) u32 highLimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) u32 ctrlVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) if (controlGroup == 1) /* Initial Control */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) for (i = 0; i < state->Init_Ctrl_Num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) highLimit = 1 << state->Init_Ctrl[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) if (value < highLimit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) for (j = 0; j < state->Init_Ctrl[i].size; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) (u8)(state->Init_Ctrl[i].bit[j]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) (u8)((value>>j) & 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) ctrlVal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) for (k = 0; k < state->Init_Ctrl[i].size; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) if (controlGroup == 2) /* Chan change Control */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) for (i = 0; i < state->CH_Ctrl_Num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) highLimit = 1 << state->CH_Ctrl[i].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) if (value < highLimit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) for (j = 0; j < state->CH_Ctrl[i].size; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) (u8)(state->CH_Ctrl[i].bit[j]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) (u8)((value>>j) & 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) ctrlVal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) for (k = 0; k < state->CH_Ctrl[i].size; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) #ifdef _MXL_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) if (controlGroup == 3) /* Maxlinear Control */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) for (i = 0; i < state->MXL_Ctrl_Num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) highLimit = (1 << state->MXL_Ctrl[i].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) if (value < highLimit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) for (j = 0; j < state->MXL_Ctrl[i].size; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) (u8)(state->MXL_Ctrl[i].bit[j]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) (u8)((value>>j) & 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) ctrlVal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) for (k = 0; k < state->MXL_Ctrl[i].size; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) ctrlVal += state->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) MXL_Ctrl[i].val[k] *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) (1 << k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) return 0 ; /* successful return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) for (i = 0; i < 104; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) if (RegNum == state->TunerRegs[i].Reg_Num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) *RegVal = (u8)(state->TunerRegs[i].Reg_Val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) u32 ctrlVal ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) u16 i, k ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) for (i = 0; i < state->Init_Ctrl_Num ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) ctrlVal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) for (k = 0; k < state->Init_Ctrl[i].size; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) *value = ctrlVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) for (i = 0; i < state->CH_Ctrl_Num ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) ctrlVal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) for (k = 0; k < state->CH_Ctrl[i].size; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) *value = ctrlVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) #ifdef _MXL_INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) ctrlVal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) for (k = 0; k < state->MXL_Ctrl[i].size; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) *value = ctrlVal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) u8 bitVal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) const u8 AND_MAP[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) 0xFE, 0xFD, 0xFB, 0xF7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) 0xEF, 0xDF, 0xBF, 0x7F } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) const u8 OR_MAP[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) 0x01, 0x02, 0x04, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) 0x10, 0x20, 0x40, 0x80 } ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) for (i = 0; i < state->TunerRegs_Num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) if (state->TunerRegs[i].Reg_Num == address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) if (bitVal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) state->TunerRegs[i].Reg_Val |= OR_MAP[bit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) state->TunerRegs[i].Reg_Val &= AND_MAP[bit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) break ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) static u32 MXL_Ceiling(u32 value, u32 resolution)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) return value / resolution + (value % resolution > 0 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) /* Retrieve the Initialization Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) u8 *RegVal, int *count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) static const u8 RegAddr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) 76, 77, 91, 134, 135, 137, 147,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) 156, 166, 167, 168, 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) *count = ARRAY_SIZE(RegAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) status += MXL_BlockInit(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) for (i = 0 ; i < *count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) RegNum[i] = RegAddr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) int *count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) int i ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) /* add 77, 166, 167, 168 register for 2.6.12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) #ifdef _MXL_PRODUCTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) static const u8 RegAddr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) 14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) static const u8 RegAddr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) 14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) u8 RegAddr[171];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) for (i = 0; i <= 170; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) RegAddr[i] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) *count = ARRAY_SIZE(RegAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) for (i = 0 ; i < *count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) RegNum[i] = RegAddr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) u8 *RegVal, int *count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) u8 RegAddr[] = {43, 136};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) *count = ARRAY_SIZE(RegAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) for (i = 0; i < *count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) RegNum[i] = RegAddr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) static u16 MXL_GetMasterControl(u8 *MasterReg, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) if (state == 1) /* Load_Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) *MasterReg = 0xF3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) if (state == 2) /* Power_Down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) *MasterReg = 0x41;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) if (state == 3) /* Synth_Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) *MasterReg = 0xB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) if (state == 4) /* Seq_Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) *MasterReg = 0xF1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) #ifdef _MXL_PRODUCTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) u16 status = 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) if (VCO_Range == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) if (state->Mode == 0 && state->IF_Mode == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) /* Analog Low IF Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) CHCAL_FRAC_MOD_RF, 180224);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) if (state->Mode == 0 && state->IF_Mode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) /* Analog Zero IF Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) CHCAL_FRAC_MOD_RF, 222822);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) if (state->Mode == 1) /* Digital Mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) CHCAL_FRAC_MOD_RF, 229376);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) if (VCO_Range == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) if (state->Mode == 0 && state->IF_Mode == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) /* Analog Low IF Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) CHCAL_FRAC_MOD_RF, 206438);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) if (state->Mode == 0 && state->IF_Mode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) /* Analog Zero IF Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) CHCAL_FRAC_MOD_RF, 206438);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) if (state->Mode == 1) /* Digital Mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) CHCAL_FRAC_MOD_RF, 16384);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) if (VCO_Range == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) if (state->Mode == 0 && state->IF_Mode == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) /* Analog Low IF Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) CHCAL_FRAC_MOD_RF, 173670);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) if (state->Mode == 0 && state->IF_Mode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) /* Analog Zero IF Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) CHCAL_FRAC_MOD_RF, 173670);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) if (state->Mode == 1) /* Digital Mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) CHCAL_FRAC_MOD_RF, 245760);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) if (VCO_Range == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) if (state->Mode == 0 && state->IF_Mode == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) /* Analog Low IF Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) CHCAL_FRAC_MOD_RF, 206438);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) if (state->Mode == 0 && state->IF_Mode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) /* Analog Zero IF Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) CHCAL_FRAC_MOD_RF, 206438);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) if (state->Mode == 1) /* Digital Mode */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) status += MXL_ControlWrite(fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) CHCAL_FRAC_MOD_RF, 212992);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) if (Hystersis == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) /* End: Reference driver code found in the Realtek driver that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) * is copyright MaxLinear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) /* ----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) * Begin: Everything after here is new code to adapt the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) * proprietary Realtek driver into a Linux API tuner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) * Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) static int mxl5005s_reset(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) u8 buf[2] = { 0xff, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) dprintk(2, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) if (i2c_transfer(state->i2c, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) printk(KERN_WARNING "mxl5005s I2C reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) /* Write a single byte to a single reg, latch the value if required by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) * following the transaction with the latch byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) .buf = buf, .len = 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) if (latch == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) msg.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) if (i2c_transfer(state->i2c, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) printk(KERN_WARNING "mxl5005s I2C write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) u8 *datatable, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) for (i = 0 ; i < len-1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) static int mxl5005s_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) state->current_mode = MXL_QAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) int TableLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) mxl5005s_reset(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) /* Tuner initialization stage 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) AddrTable[0] = MASTER_CONTROL_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) ByteTable[0] |= state->config->AgcMasterByte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) mxl5005s_AssignTunerMode(fe, mod_type, bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) /* Tuner initialization stage 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) u32 bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) struct mxl5005s_config *c = state->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) InitTunerControls(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) /* Set MxL5005S parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) MXL5005_TunerConfig(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) c->mod_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) c->if_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) c->if_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) c->xtal_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) c->agc_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) c->top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) c->output_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) c->clock_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) c->div_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) c->cap_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) c->rssi_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) mod_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) c->tracking_filter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) static int mxl5005s_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) u32 delsys = c->delivery_system;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) u32 bw = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) u32 req_mode, req_bw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) switch (delsys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) case SYS_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) req_mode = MXL_ATSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) req_bw = MXL5005S_BANDWIDTH_6MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) case SYS_DVBC_ANNEX_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) req_mode = MXL_QAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) req_bw = MXL5005S_BANDWIDTH_6MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) default: /* Assume DVB-T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) req_mode = MXL_DVBT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) switch (bw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) req_bw = MXL5005S_BANDWIDTH_6MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) req_bw = MXL5005S_BANDWIDTH_7MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) req_bw = MXL5005S_BANDWIDTH_8MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) /* Change tuner for new modulation type if reqd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) if (req_mode != state->current_mode ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) req_bw != state->Chan_Bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) state->current_mode = req_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) ret = mxl5005s_reconfigure(fe, req_mode, req_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) dprintk(1, "%s() freq=%d\n", __func__, c->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) ret = mxl5005s_SetRfFreqHz(fe, c->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) *frequency = state->RF_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) *bandwidth = state->Chan_Bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) static int mxl5005s_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) struct mxl5005s_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) *frequency = state->IF_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) static void mxl5005s_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) kfree(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) static const struct dvb_tuner_ops mxl5005s_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) .name = "MaxLinear MXL5005S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) .frequency_min_hz = 48 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) .frequency_max_hz = 860 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) .frequency_step_hz = 50 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) .release = mxl5005s_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) .init = mxl5005s_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) .set_params = mxl5005s_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) .get_frequency = mxl5005s_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) .get_bandwidth = mxl5005s_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) .get_if_frequency = mxl5005s_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) struct mxl5005s_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) struct mxl5005s_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) state->frontend = fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) config->i2c_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) fe->tuner_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) EXPORT_SYMBOL(mxl5005s_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) MODULE_AUTHOR("Steven Toth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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