^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MaxLinear MxL301RF OFDM tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * NOTICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This driver is incomplete and lacks init/config of the chips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * as the necessary info is not disclosed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Other features like get_if_frequency() are missing as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * It assumes that users of this driver (such as a PCI bridge of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * DTV receiver cards) properly init and configure the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * via I2C *before* calling this driver's init() function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Currently, PT3 driver is the only one that uses this driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * and contains init/config code in its firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Thus some part of the code might be dependent on PT3 specific config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "mxl301rf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct mxl301rf_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct mxl301rf_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct mxl301rf_state *cfg_to_state(struct mxl301rf_config *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return container_of(c, struct mxl301rf_state, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int raw_write(struct mxl301rf_state *state, const u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ret = i2c_master_send(state->i2c, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (ret >= 0 && ret < len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return (ret == len) ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int reg_write(struct mxl301rf_state *state, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 buf[2] = { reg, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return raw_write(state, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int reg_read(struct mxl301rf_state *state, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 wbuf[2] = { 0xfb, reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ret = raw_write(state, wbuf, sizeof(wbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ret = i2c_master_recv(state->i2c, val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (ret >= 0 && ret < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return (ret == 1) ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* tuner_ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* get RSSI and update propery cache, set to *out in % */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int mxl301rf_get_rf_strength(struct dvb_frontend *fe, u16 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct mxl301rf_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 rf_in1, rf_in2, rf_off1, rf_off2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u16 rf_in, rf_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) s64 level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct dtv_fe_stats *rssi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) rssi = &fe->dtv_property_cache.strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) rssi->len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) rssi->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *out = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret = reg_write(state, 0x14, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = reg_read(state, 0x18, &rf_in1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = reg_read(state, 0x19, &rf_in2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ret = reg_read(state, 0xd6, &rf_off1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = reg_read(state, 0xd7, &rf_off2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rf_in = (rf_in2 & 0x07) << 8 | rf_in1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) rf_off = (rf_off2 & 0x0f) << 5 | (rf_off1 >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) level = rf_in - rf_off - (113 << 3); /* x8 dBm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) level = level * 1000 / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) rssi->stat[0].svalue = level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) rssi->stat[0].scale = FE_SCALE_DECIBEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* *out = (level - min) * 100 / (max - min) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *out = (rf_in - rf_off + (1 << 9) - 1) * 100 / ((5 << 9) - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* spur shift parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct shf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 freq; /* Channel center frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 ofst_th; /* Offset frequency threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 shf_val; /* Spur shift value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 shf_dir; /* Spur shift direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct shf shf_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 64500, 500, 0x92, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { 191500, 300, 0xe2, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 205500, 500, 0x2c, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 212500, 500, 0x1e, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 226500, 500, 0xd4, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 99143, 500, 0x9c, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 173143, 500, 0xd4, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 191143, 300, 0xd4, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 207143, 500, 0xce, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { 225143, 500, 0xce, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 243143, 500, 0xd4, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 261143, 500, 0xd4, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 291143, 500, 0xd4, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { 339143, 500, 0x2c, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { 117143, 500, 0x7a, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 135143, 300, 0x7a, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 153143, 500, 0x01, 0x07 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct reg_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct reg_val set_idac[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { 0x0d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { 0x0c, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { 0x6f, 0x89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 0x70, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { 0x6f, 0x8a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { 0x70, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { 0x6f, 0x8b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { 0x70, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int mxl301rf_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct reg_val tune0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 0x13, 0x00 }, /* abort tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { 0x3b, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 0x3b, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 0x10, 0x95 }, /* BW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { 0x1a, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { 0x61, 0x00 }, /* spur shift value (placeholder) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0x62, 0xa0 } /* spur shift direction (placeholder) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct reg_val tune1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 0x11, 0x40 }, /* RF frequency L (placeholder) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 0x12, 0x0e }, /* RF frequency H (placeholder) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 0x13, 0x01 } /* start tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct mxl301rf_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u16 f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 tmp, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) freq = fe->dtv_property_cache.frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* spur shift function (for analog) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) for (i = 0; i < ARRAY_SIZE(shf_tab); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (freq >= (shf_tab[i].freq - shf_tab[i].ofst_th) * 1000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) freq <= (shf_tab[i].freq + shf_tab[i].ofst_th) * 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) tune0[5].val = shf_tab[i].shf_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) tune0[6].val = 0xa0 | shf_tab[i].shf_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = raw_write(state, (u8 *) tune0, sizeof(tune0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) usleep_range(3000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* convert freq to 10.6 fixed point float [MHz] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) f = freq / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) tmp = freq % 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) div = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (i = 0; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) f <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) div >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (tmp > div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) tmp -= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) f |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (tmp > 7812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) f++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tune1[0].val = f & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tune1[1].val = f >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = raw_write(state, (u8 *) tune1, sizeof(tune1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) msleep(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = reg_write(state, 0x1a, 0x0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = raw_write(state, (u8 *) set_idac, sizeof(set_idac));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __func__, fe->dvb->num, fe->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const struct reg_val standby_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 0x01, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 0x13, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int mxl301rf_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct mxl301rf_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = raw_write(state, (u8 *)standby_data, sizeof(standby_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __func__, fe->dvb->num, fe->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* init sequence is not public.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * the parent must have init'ed the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * just wake up here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int mxl301rf_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct mxl301rf_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = reg_write(state, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __func__, fe->dvb->num, fe->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* I2C driver functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct dvb_tuner_ops mxl301rf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "MaxLinear MxL301RF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .frequency_min_hz = 93 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .frequency_max_hz = 803 * MHz + 142857,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .init = mxl301rf_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .sleep = mxl301rf_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .set_params = mxl301rf_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .get_rf_strength = mxl301rf_get_rf_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int mxl301rf_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct mxl301rf_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct mxl301rf_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) state = kzalloc(sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) state->i2c = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) cfg = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) memcpy(&state->cfg, cfg, sizeof(state->cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) fe = cfg->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) fe->tuner_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) memcpy(&fe->ops.tuner_ops, &mxl301rf_ops, sizeof(mxl301rf_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) i2c_set_clientdata(client, &state->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_info(&client->dev, "MaxLinear MxL301RF attached.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int mxl301rf_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct mxl301rf_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) state = cfg_to_state(i2c_get_clientdata(client));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) state->cfg.fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct i2c_device_id mxl301rf_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {"mxl301rf", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) MODULE_DEVICE_TABLE(i2c, mxl301rf_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct i2c_driver mxl301rf_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .name = "mxl301rf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .probe = mxl301rf_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .remove = mxl301rf_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .id_table = mxl301rf_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) module_i2c_driver(mxl301rf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_DESCRIPTION("MaxLinear MXL301RF tuner");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_AUTHOR("Akihiro TSUKADA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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