Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Driver for Microtune MT2266 "Direct conversion low power broadband tuner"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (c) 2007 Olivier DANET <odanet@caramail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "mt2266.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define I2C_ADDRESS 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define REG_PART_REV   0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define REG_TUNE       1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_BAND       6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_BANDWIDTH  8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define REG_LOCK       0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PART_REV 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct mt2266_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct mt2266_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct i2c_adapter   *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32 bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u8 band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MT2266_VHF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MT2266_UHF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* Here, frequencies are expressed in kiloHertz to avoid 32 bits overflows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "MT2266: " args); printk("\n"); }} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) // Reads a single register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int mt2266_readreg(struct mt2266_priv *priv, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		{ .addr = priv->cfg->i2c_address, .flags = 0,        .buf = &reg, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .buf = val,  .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (i2c_transfer(priv->i2c, msg, 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		printk(KERN_WARNING "MT2266 I2C read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) // Writes a single register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static int mt2266_writereg(struct mt2266_priv *priv, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u8 buf[2] = { reg, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		printk(KERN_WARNING "MT2266 I2C write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) // Writes a set of consecutive registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int mt2266_writeregs(struct mt2266_priv *priv,u8 *buf, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		printk(KERN_WARNING "MT2266 I2C write failed (len=%i)\n",(int)len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) // Initialisation sequences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static u8 mt2266_init1[] = { REG_TUNE, 0x00, 0x00, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				 0x00, 0x52, 0x99, 0x3f };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static u8 mt2266_init2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)     0x17, 0x6d, 0x71, 0x61, 0xc0, 0xbf, 0xff, 0xdc, 0x00, 0x0a, 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)     0x03, 0x64, 0x64, 0x64, 0x64, 0x22, 0xaa, 0xf2, 0x1e, 0x80, 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)     0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x7f, 0x5e, 0x3f, 0xff, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)     0xff, 0x00, 0x77, 0x0f, 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static u8 mt2266_init_8mhz[] = { REG_BANDWIDTH, 0x22, 0x22, 0x22, 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 						0x22, 0x22, 0x22, 0x22 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static u8 mt2266_init_7mhz[] = { REG_BANDWIDTH, 0x32, 0x32, 0x32, 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 						0x32, 0x32, 0x32, 0x32 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static u8 mt2266_init_6mhz[] = { REG_BANDWIDTH, 0xa7, 0xa7, 0xa7, 0xa7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 						0xa7, 0xa7, 0xa7, 0xa7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static u8 mt2266_uhf[] = { 0x1d, 0xdc, 0x00, 0x0a, 0xd4, 0x03, 0x64, 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			   0x64, 0x64, 0x22, 0xaa, 0xf2, 0x1e, 0x80, 0x14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static u8 mt2266_vhf[] = { 0x1d, 0xfe, 0x00, 0x00, 0xb4, 0x03, 0xa5, 0xa5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			   0xa5, 0xa5, 0x82, 0xaa, 0xf1, 0x17, 0x80, 0x1f };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define FREF 30000       // Quartz oscillator 30 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int mt2266_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct mt2266_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int ret=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u32 tune;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u8  lnaband;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u8  b[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u8 band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	freq = priv->frequency / 1000; /* Hz -> kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (freq < 470000 && freq > 230000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return -EINVAL; /* Gap between VHF and UHF bands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	priv->frequency = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	tune = 2 * freq * (8192/16) / (FREF/16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	band = (freq < 300000) ? MT2266_VHF : MT2266_UHF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (band == MT2266_VHF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		tune *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	switch (c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		mt2266_writeregs(priv, mt2266_init_6mhz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				 sizeof(mt2266_init_6mhz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		mt2266_writeregs(priv, mt2266_init_8mhz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 				 sizeof(mt2266_init_8mhz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		mt2266_writeregs(priv, mt2266_init_7mhz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				 sizeof(mt2266_init_7mhz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	priv->bandwidth = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (band == MT2266_VHF && priv->band == MT2266_UHF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		dprintk("Switch from UHF to VHF");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		mt2266_writereg(priv, 0x05, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		mt2266_writereg(priv, 0x19, 0x61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		mt2266_writeregs(priv, mt2266_vhf, sizeof(mt2266_vhf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	} else if (band == MT2266_UHF && priv->band == MT2266_VHF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		dprintk("Switch from VHF to UHF");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		mt2266_writereg(priv, 0x05, 0x52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		mt2266_writereg(priv, 0x19, 0x61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		mt2266_writeregs(priv, mt2266_uhf, sizeof(mt2266_uhf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (freq <= 495000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		lnaband = 0xEE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	else if (freq <= 525000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		lnaband = 0xDD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	else if (freq <= 550000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		lnaband = 0xCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	else if (freq <= 580000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		lnaband = 0xBB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	else if (freq <= 605000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		lnaband = 0xAA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	else if (freq <= 630000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		lnaband = 0x99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	else if (freq <= 655000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		lnaband = 0x88;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	else if (freq <= 685000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		lnaband = 0x77;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	else if (freq <= 710000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		lnaband = 0x66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	else if (freq <= 735000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		lnaband = 0x55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	else if (freq <= 765000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		lnaband = 0x44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	else if (freq <= 802000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		lnaband = 0x33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	else if (freq <= 840000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		lnaband = 0x22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		lnaband = 0x11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	b[0] = REG_TUNE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	b[1] = (tune >> 8) & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	b[2] = tune & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	b[3] = tune >> 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	mt2266_writeregs(priv,b,4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	dprintk("set_parms: tune=%d band=%d %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		(int) tune, (int) lnaband,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		(band == MT2266_UHF) ? "UHF" : "VHF");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	dprintk("set_parms: [1..3]: %2x %2x %2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		(int) b[1], (int) b[2], (int)b[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (band == MT2266_UHF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		b[0] = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		b[1] = (priv->band == MT2266_VHF) ? 0x52 : 0x62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		b[2] = lnaband;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		mt2266_writeregs(priv, b, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* Wait for pll lock or timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		mt2266_readreg(priv,REG_LOCK,b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		if (b[0] & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	} while (i<10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	dprintk("Lock when i=%i",(int)i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (band == MT2266_UHF && priv->band == MT2266_VHF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		mt2266_writereg(priv, 0x05, 0x62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	priv->band = band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void mt2266_calibrate(struct mt2266_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	mt2266_writereg(priv, 0x11, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	mt2266_writereg(priv, 0x11, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	mt2266_writeregs(priv, mt2266_init1, sizeof(mt2266_init1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	mt2266_writeregs(priv, mt2266_init2, sizeof(mt2266_init2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	mt2266_writereg(priv, 0x33, 0x5e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	mt2266_writereg(priv, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	mt2266_writereg(priv, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	mt2266_writeregs(priv, mt2266_init_8mhz, sizeof(mt2266_init_8mhz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	msleep(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	mt2266_writereg(priv, 0x17, 0x6d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	mt2266_writereg(priv, 0x1c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	msleep(75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	mt2266_writereg(priv, 0x17, 0x6d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	mt2266_writereg(priv, 0x1c, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int mt2266_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct mt2266_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	*frequency = priv->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int mt2266_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct mt2266_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	*bandwidth = priv->bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int mt2266_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct mt2266_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ret = mt2266_writereg(priv, 0x17, 0x6d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	ret = mt2266_writereg(priv, 0x1c, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int mt2266_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct mt2266_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	mt2266_writereg(priv, 0x17, 0x6d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	mt2266_writereg(priv, 0x1c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void mt2266_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	kfree(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct dvb_tuner_ops mt2266_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.name              = "Microtune MT2266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.frequency_min_hz  = 174 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		.frequency_max_hz  = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.frequency_step_hz =  50 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.release       = mt2266_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.init          = mt2266_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.sleep         = mt2266_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.set_params    = mt2266_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.get_frequency = mt2266_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.get_bandwidth = mt2266_get_bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2266_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct mt2266_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	u8 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	priv = kzalloc(sizeof(struct mt2266_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	priv->cfg      = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	priv->i2c      = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	priv->band     = MT2266_UHF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (mt2266_readreg(priv, 0, &id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (id != PART_REV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	printk(KERN_INFO "MT2266: successfully identified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	memcpy(&fe->ops.tuner_ops, &mt2266_tuner_ops, sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	mt2266_calibrate(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) EXPORT_SYMBOL(mt2266_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_AUTHOR("Olivier DANET");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_DESCRIPTION("Microtune MT2266 silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_LICENSE("GPL");