Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Driver for Microtune MT2131 "QAM/8VSB single chip tuner"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "mt2131.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "mt2131_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define dprintk(level,fmt, arg...) if (debug >= level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	printk(KERN_INFO "%s: " fmt, "mt2131", ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static u8 mt2131_config1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	0x50, 0x00, 0x50, 0x80, 0x00, 0x49, 0xfa, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	0x08, 0x77, 0x41, 0x04, 0x00, 0x00, 0x00, 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	0x7f, 0xda, 0x4c, 0x00, 0x10, 0xaa, 0x78, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	0xff, 0x68, 0xa0, 0xff, 0xdd, 0x00, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static u8 mt2131_config2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	0x7f, 0xc8, 0x0a, 0x5f, 0x00, 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static int mt2131_readreg(struct mt2131_priv *priv, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		{ .addr = priv->cfg->i2c_address, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		  .buf = &reg, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		  .buf = val,  .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (i2c_transfer(priv->i2c, msg, 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		printk(KERN_WARNING "mt2131 I2C read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static int mt2131_writereg(struct mt2131_priv *priv, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u8 buf[2] = { reg, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct i2c_msg msg = { .addr = priv->cfg->i2c_address, .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			       .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		printk(KERN_WARNING "mt2131 I2C write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static int mt2131_writeregs(struct mt2131_priv *priv,u8 *buf, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct i2c_msg msg = { .addr = priv->cfg->i2c_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			       .flags = 0, .buf = buf, .len = len };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		printk(KERN_WARNING "mt2131 I2C write failed (len=%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		       (int)len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static int mt2131_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct mt2131_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	int ret=0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u8  if_band_center;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u32 f_lo1, f_lo2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u32 div1, num1, div2, num2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u8  b[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u8 lockval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	freq = c->frequency / 1000;  /* Hz -> kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	dprintk(1, "%s() freq=%d\n", __func__, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	f_lo1 = freq + MT2131_IF1 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	f_lo1 = (f_lo1 / 250) * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	f_lo2 = f_lo1 - freq - MT2131_IF2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	priv->frequency =  (f_lo1 - f_lo2 - MT2131_IF2) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* Frequency LO1 = 16MHz * (DIV1 + NUM1/8192 ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	num1 = f_lo1 * 64 / (MT2131_FREF / 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	div1 = num1 / 8192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	num1 &= 0x1fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	num2 = f_lo2 * 64 / (MT2131_FREF / 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	div2 = num2 / 8192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	num2 &= 0x1fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (freq <=   82500) if_band_center = 0x00; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (freq <=  137500) if_band_center = 0x01; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (freq <=  192500) if_band_center = 0x02; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (freq <=  247500) if_band_center = 0x03; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (freq <=  302500) if_band_center = 0x04; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (freq <=  357500) if_band_center = 0x05; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (freq <=  412500) if_band_center = 0x06; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (freq <=  467500) if_band_center = 0x07; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (freq <=  522500) if_band_center = 0x08; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (freq <=  577500) if_band_center = 0x09; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (freq <=  632500) if_band_center = 0x0A; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (freq <=  687500) if_band_center = 0x0B; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (freq <=  742500) if_band_center = 0x0C; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (freq <=  797500) if_band_center = 0x0D; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (freq <=  852500) if_band_center = 0x0E; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (freq <=  907500) if_band_center = 0x0F; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (freq <=  962500) if_band_center = 0x10; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (freq <= 1017500) if_band_center = 0x11; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (freq <= 1072500) if_band_center = 0x12; else if_band_center = 0x13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	b[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	b[1] = (num1 >> 5) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	b[2] = (num1 & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	b[3] = div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	b[4] = (num2 >> 5) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	b[5] = num2 & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	b[6] = div2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	dprintk(1, "IF1: %dMHz IF2: %dMHz\n", MT2131_IF1, MT2131_IF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	dprintk(1, "PLL freq=%dkHz  band=%d\n", (int)freq, (int)if_band_center);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	dprintk(1, "PLL f_lo1=%dkHz  f_lo2=%dkHz\n", (int)f_lo1, (int)f_lo2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	dprintk(1, "PLL div1=%d  num1=%d  div2=%d  num2=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		(int)div1, (int)num1, (int)div2, (int)num2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	dprintk(1, "PLL [1..6]: %2x %2x %2x %2x %2x %2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		(int)b[1], (int)b[2], (int)b[3], (int)b[4], (int)b[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		(int)b[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	ret = mt2131_writeregs(priv,b,7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	mt2131_writereg(priv, 0x0b, if_band_center);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* Wait for lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		mt2131_readreg(priv, 0x08, &lockval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		if ((lockval & 0x88) == 0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		msleep(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	} while (i < 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int mt2131_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct mt2131_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	*frequency = priv->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int mt2131_get_status(struct dvb_frontend *fe, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct mt2131_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u8 lock_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u8 afc_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	*status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	mt2131_readreg(priv, 0x08, &lock_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if ((lock_status & 0x88) == 0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		*status = TUNER_STATUS_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	mt2131_readreg(priv, 0x09, &afc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	dprintk(1, "%s() - LO Status = 0x%x, AFC Status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		__func__, lock_status, afc_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int mt2131_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct mt2131_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if ((ret = mt2131_writeregs(priv, mt2131_config1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				    sizeof(mt2131_config1))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	mt2131_writereg(priv, 0x0b, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	mt2131_writereg(priv, 0x15, 0x47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	mt2131_writereg(priv, 0x07, 0xf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	mt2131_writereg(priv, 0x0b, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if ((ret = mt2131_writeregs(priv, mt2131_config2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 				    sizeof(mt2131_config2))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void mt2131_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	kfree(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct dvb_tuner_ops mt2131_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.name              = "Microtune MT2131",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.frequency_min_hz  =  48 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.frequency_max_hz  = 860 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.frequency_step_hz =  50 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.release       = mt2131_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.init          = mt2131_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.set_params    = mt2131_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.get_frequency = mt2131_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.get_status    = mt2131_get_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct dvb_frontend * mt2131_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				    struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				    struct mt2131_config *cfg, u16 if1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct mt2131_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	u8 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	priv = kzalloc(sizeof(struct mt2131_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	priv->cfg = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	priv->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (mt2131_readreg(priv, 0, &id) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if ( (id != 0x3E) && (id != 0x3F) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		printk(KERN_ERR "MT2131: Device not found at addr 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		       cfg->i2c_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	printk(KERN_INFO "MT2131: successfully identified at address 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	       cfg->i2c_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	memcpy(&fe->ops.tuner_ops, &mt2131_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	       sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) EXPORT_SYMBOL(mt2131_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MODULE_AUTHOR("Steven Toth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_DESCRIPTION("Microtune MT2131 silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_LICENSE("GPL");