^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for mt2063 Micronas tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Mauro Carvalho Chehab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This driver came from a driver originally written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Henry Wang <Henry.wang@AzureWave.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Made publicly available by Terratec, at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * http://linux.terratec.de/files/TERRATEC_H7/20110323_TERRATEC_H7_Linux.tar.gz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "mt2063.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static unsigned int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MODULE_PARM_DESC(debug, "Set Verbosity level");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define dprintk(level, fmt, arg...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (debug >= level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) printk(KERN_DEBUG "mt2063 %s: " fmt, __func__, ## arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* positive error codes used internally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Info: Unavoidable LO-related spur may be present in the output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MT2063_SPUR_PRESENT_ERR (0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Info: Mask of bits used for # of LO-related spurs that were avoided during tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MT2063_SPUR_CNT_MASK (0x001f0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MT2063_SPUR_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Info: Upconverter frequency is out of range (may be reason for MT_UPC_UNLOCK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MT2063_UPC_RANGE (0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Info: Downconverter frequency is out of range (may be reason for MT_DPC_UNLOCK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MT2063_DNC_RANGE (0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Constant defining the version of the following structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * and therefore the API for this code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * When compiling the tuner driver, the preprocessor will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * check against this version number to make sure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * it matches the version that the tuner driver knows about.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* DECT Frequency Avoidance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MT2063_DECT_AVOID_US_FREQS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MT2063_DECT_AVOID_EURO_FREQS 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MT2063_EXCLUDE_US_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_US_FREQS) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_EURO_FREQS) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum MT2063_DECT_Avoid_Type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MT2063_NO_DECT_AVOIDANCE = 0, /* Do not create DECT exclusion zones. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MT2063_AVOID_US_DECT = MT2063_DECT_AVOID_US_FREQS, /* Avoid US DECT frequencies. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MT2063_AVOID_EURO_DECT = MT2063_DECT_AVOID_EURO_FREQS, /* Avoid European DECT frequencies. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MT2063_AVOID_BOTH /* Avoid both regions. Not typically used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MT2063_MAX_ZONES 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct MT2063_ExclZone_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 min_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 max_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct MT2063_ExclZone_t *next_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Structure of data needed for Spur Avoidance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct MT2063_AvoidSpursData_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 f_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 f_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 f_LO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 f_if1_Center;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 f_if1_Request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 f_if1_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 f_LO2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 f_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 f_out_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 f_LO1_Step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 f_LO2_Step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 f_LO1_FracN_Avoid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 f_LO2_FracN_Avoid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 f_zif_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 f_min_LO_Separation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 maxH1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 maxH2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum MT2063_DECT_Avoid_Type avoidDECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 bSpurPresent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 bSpurAvoided;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 nSpursFound;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 nZones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct MT2063_ExclZone_t *freeZones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct MT2063_ExclZone_t *usedZones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct MT2063_ExclZone_t MT2063_ExclZones[MT2063_MAX_ZONES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Parameter for function MT2063_SetPowerMask that specifies the power down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * of various sections of the MT2063.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum MT2063_Mask_Bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MT2063_REG_SD = 0x0040, /* Shutdown regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MT2063_SRO_SD = 0x0020, /* Shutdown SRO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MT2063_AFC_SD = 0x0010, /* Shutdown AFC A/D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MT2063_PD_SD = 0x0002, /* Enable power detector shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MT2063_PDADC_SD = 0x0001, /* Enable power detector A/D shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MT2063_VCO_SD = 0x8000, /* Enable VCO shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MT2063_LTX_SD = 0x4000, /* Enable LTX shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MT2063_LT1_SD = 0x2000, /* Enable LT1 shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MT2063_LNA_SD = 0x1000, /* Enable LNA shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MT2063_UPC_SD = 0x0800, /* Enable upconverter shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MT2063_DNC_SD = 0x0400, /* Enable downconverter shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MT2063_VGA_SD = 0x0200, /* Enable VGA shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MT2063_AMP_SD = 0x0100, /* Enable AMP shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MT2063_ALL_SD = 0xFF73, /* All shutdown bits for this tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MT2063_NONE_SD = 0x0000 /* No shutdown bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Possible values for MT2063_DNC_OUTPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) enum MT2063_DNC_Output_Enable {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MT2063_DNC_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MT2063_DNC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MT2063_DNC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MT2063_DNC_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Two-wire serial bus subaddresses of the tuner registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Also known as the tuner's register addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) enum MT2063_Register_Offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MT2063_REG_PART_REV = 0, /* 0x00: Part/Rev Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MT2063_REG_LO1CQ_1, /* 0x01: LO1C Queued Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MT2063_REG_LO1CQ_2, /* 0x02: LO1C Queued Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MT2063_REG_LO2CQ_1, /* 0x03: LO2C Queued Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MT2063_REG_LO2CQ_2, /* 0x04: LO2C Queued Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MT2063_REG_LO2CQ_3, /* 0x05: LO2C Queued Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MT2063_REG_RSVD_06, /* 0x06: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MT2063_REG_LO_STATUS, /* 0x07: LO Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MT2063_REG_FIFFC, /* 0x08: FIFF Center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MT2063_REG_CLEARTUNE, /* 0x09: ClearTune Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MT2063_REG_ADC_OUT, /* 0x0A: ADC_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MT2063_REG_LO1C_1, /* 0x0B: LO1C Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MT2063_REG_LO1C_2, /* 0x0C: LO1C Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MT2063_REG_LO2C_1, /* 0x0D: LO2C Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MT2063_REG_LO2C_2, /* 0x0E: LO2C Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MT2063_REG_LO2C_3, /* 0x0F: LO2C Byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MT2063_REG_RSVD_10, /* 0x10: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MT2063_REG_PWR_1, /* 0x11: PWR Byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MT2063_REG_PWR_2, /* 0x12: PWR Byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MT2063_REG_TEMP_STATUS, /* 0x13: Temp Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MT2063_REG_XO_STATUS, /* 0x14: Crystal Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MT2063_REG_RF_STATUS, /* 0x15: RF Attn Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MT2063_REG_FIF_STATUS, /* 0x16: FIF Attn Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MT2063_REG_LNA_OV, /* 0x17: LNA Attn Override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MT2063_REG_RF_OV, /* 0x18: RF Attn Override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MT2063_REG_FIF_OV, /* 0x19: FIF Attn Override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MT2063_REG_LNA_TGT, /* 0x1A: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MT2063_REG_PD1_TGT, /* 0x1B: Pwr Det 1 Target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MT2063_REG_PD2_TGT, /* 0x1C: Pwr Det 2 Target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MT2063_REG_RSVD_1D, /* 0x1D: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MT2063_REG_RSVD_1E, /* 0x1E: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MT2063_REG_RSVD_1F, /* 0x1F: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MT2063_REG_RSVD_20, /* 0x20: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MT2063_REG_BYP_CTRL, /* 0x21: Bypass Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MT2063_REG_RSVD_22, /* 0x22: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MT2063_REG_RSVD_23, /* 0x23: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MT2063_REG_RSVD_24, /* 0x24: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MT2063_REG_RSVD_25, /* 0x25: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MT2063_REG_RSVD_26, /* 0x26: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MT2063_REG_RSVD_27, /* 0x27: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MT2063_REG_FIFF_CTRL, /* 0x28: FIFF Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MT2063_REG_FIFF_OFFSET, /* 0x29: FIFF Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MT2063_REG_CTUNE_CTRL, /* 0x2A: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MT2063_REG_CTUNE_OV, /* 0x2B: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MT2063_REG_CTRL_2C, /* 0x2C: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MT2063_REG_FIFF_CTRL2, /* 0x2D: Fiff Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MT2063_REG_RSVD_2E, /* 0x2E: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MT2063_REG_DNC_GAIN, /* 0x2F: DNC Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MT2063_REG_VGA_GAIN, /* 0x30: VGA Gain Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MT2063_REG_RSVD_31, /* 0x31: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MT2063_REG_TEMP_SEL, /* 0x32: Temperature Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MT2063_REG_RSVD_33, /* 0x33: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MT2063_REG_RSVD_34, /* 0x34: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MT2063_REG_RSVD_35, /* 0x35: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MT2063_REG_RSVD_36, /* 0x36: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MT2063_REG_RSVD_37, /* 0x37: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MT2063_REG_RSVD_38, /* 0x38: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MT2063_REG_RSVD_39, /* 0x39: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MT2063_REG_RSVD_3A, /* 0x3A: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MT2063_REG_RSVD_3B, /* 0x3B: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MT2063_REG_RSVD_3C, /* 0x3C: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MT2063_REG_END_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct mt2063_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) bool init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) const struct mt2063_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct dvb_tuner_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct dvb_frontend *frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 srate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 reference;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 tuner_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct MT2063_AvoidSpursData_t AS_Data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 f_IF1_actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 rcvr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 ctfilt_sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 CTFiltMax[31];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 reg[MT2063_REG_END_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * mt2063_write - Write data into the I2C bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int mt2063_write(struct mt2063_state *state, u8 reg, u8 *data, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct dvb_frontend *fe = state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u8 buf[60];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .addr = state->config->tuner_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .len = len + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) msg.buf[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) memcpy(msg.buf + 1, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = i2c_transfer(state->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) printk(KERN_ERR "%s error ret=%d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * mt2063_write - Write register data into the I2C bus, caching the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int mt2063_setreg(struct mt2063_state *state, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (reg >= MT2063_REG_END_REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) status = mt2063_write(state, reg, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) state->reg[reg] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * mt2063_read - Read data from the I2C bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int mt2063_read(struct mt2063_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 subAddress, u8 *pData, u32 cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int status = 0; /* Status to be returned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct dvb_frontend *fe = state->frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dprintk(2, "addr 0x%02x, cnt %d\n", subAddress, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (i = 0; i < cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 b0[] = { subAddress + i };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .addr = state->config->tuner_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .buf = b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .len = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .addr = state->config->tuner_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .buf = pData + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .len = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) status = i2c_transfer(state->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dprintk(2, "addr 0x%02x, ret = %d, val = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) subAddress + i, status, *(pData + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) printk(KERN_ERR "Can't read from address 0x%02x,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) subAddress + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * FIXME: Is this really needed?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int MT2063_Sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * ToDo: Add code here to implement a OS blocking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Microtune spur avoidance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Implement ceiling, floor functions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define ceil(n, d) (((n) < 0) ? (-((-(n))/(d))) : (n)/(d) + ((n)%(d) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define floor(n, d) (((n) < 0) ? (-((-(n))/(d))) - ((n)%(d) != 0) : (n)/(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct MT2063_FIFZone_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) s32 min_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) s32 max_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct MT2063_ExclZone_t *InsertNode(struct MT2063_AvoidSpursData_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *pAS_Info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct MT2063_ExclZone_t *pPrevNode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct MT2063_ExclZone_t *pNode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Check for a node in the free list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (pAS_Info->freeZones != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Use one from the free list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pNode = pAS_Info->freeZones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pAS_Info->freeZones = pNode->next_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Grab a node from the array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pNode = &pAS_Info->MT2063_ExclZones[pAS_Info->nZones];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (pPrevNode != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pNode->next_ = pPrevNode->next_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pPrevNode->next_ = pNode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else { /* insert at the beginning of the list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pNode->next_ = pAS_Info->usedZones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pAS_Info->usedZones = pNode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pAS_Info->nZones++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return pNode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct MT2063_ExclZone_t *RemoveNode(struct MT2063_AvoidSpursData_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) *pAS_Info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct MT2063_ExclZone_t *pPrevNode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct MT2063_ExclZone_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *pNodeToRemove)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct MT2063_ExclZone_t *pNext = pNodeToRemove->next_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Make previous node point to the subsequent node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (pPrevNode != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pPrevNode->next_ = pNext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Add pNodeToRemove to the beginning of the freeZones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pNodeToRemove->next_ = pAS_Info->freeZones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pAS_Info->freeZones = pNodeToRemove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Decrement node count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pAS_Info->nZones--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return pNext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * MT_AddExclZone()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * Add (and merge) an exclusion zone into the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * If the range (f_min, f_max) is totally outside the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * 1st IF BW, ignore the entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * If the range (f_min, f_max) is negative, ignore the entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 f_min, u32 f_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct MT2063_ExclZone_t *pNode = pAS_Info->usedZones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct MT2063_ExclZone_t *pPrev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct MT2063_ExclZone_t *pNext = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Check to see if this overlaps the 1st IF filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if ((f_max > (pAS_Info->f_if1_Center - (pAS_Info->f_if1_bw / 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) && (f_min < (pAS_Info->f_if1_Center + (pAS_Info->f_if1_bw / 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) && (f_min < f_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * 1 2 3 4 5 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * New entry: |---| |--| |--| |-| |---| |--|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * or or or or or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Existing: |--| |--| |--| |---| |-| |--|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Check for our place in the list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) while ((pNode != NULL) && (pNode->max_ < f_min)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pPrev = pNode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pNode = pNode->next_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if ((pNode != NULL) && (pNode->min_ < f_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Combine me with pNode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (f_min < pNode->min_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pNode->min_ = f_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (f_max > pNode->max_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pNode->max_ = f_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) pNode = InsertNode(pAS_Info, pPrev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pNode->min_ = f_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pNode->max_ = f_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Look for merging possibilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pNext = pNode->next_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) while ((pNext != NULL) && (pNext->min_ < pNode->max_)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (pNext->max_ > pNode->max_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pNode->max_ = pNext->max_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Remove pNext, return ptr to pNext->next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pNext = RemoveNode(pAS_Info, pNode, pNext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * Reset all exclusion zones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Add zones to protect the PLL FracN regions near zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void MT2063_ResetExclZones(struct MT2063_AvoidSpursData_t *pAS_Info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 center;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pAS_Info->nZones = 0; /* this clears the used list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pAS_Info->usedZones = NULL; /* reset ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pAS_Info->freeZones = NULL; /* reset ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) center =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pAS_Info->f_ref *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ((pAS_Info->f_if1_Center - pAS_Info->f_if1_bw / 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pAS_Info->f_in) / pAS_Info->f_ref) - pAS_Info->f_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) while (center <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pAS_Info->f_if1_Center + pAS_Info->f_if1_bw / 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pAS_Info->f_LO1_FracN_Avoid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Exclude LO1 FracN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MT2063_AddExclZone(pAS_Info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) center - pAS_Info->f_LO1_FracN_Avoid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) center - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MT2063_AddExclZone(pAS_Info, center + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) center + pAS_Info->f_LO1_FracN_Avoid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) center += pAS_Info->f_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) center =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pAS_Info->f_ref *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ((pAS_Info->f_if1_Center - pAS_Info->f_if1_bw / 2 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pAS_Info->f_out) / pAS_Info->f_ref) + pAS_Info->f_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) while (center <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pAS_Info->f_if1_Center + pAS_Info->f_if1_bw / 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pAS_Info->f_LO2_FracN_Avoid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Exclude LO2 FracN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MT2063_AddExclZone(pAS_Info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) center - pAS_Info->f_LO2_FracN_Avoid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) center - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MT2063_AddExclZone(pAS_Info, center + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) center + pAS_Info->f_LO2_FracN_Avoid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) center += pAS_Info->f_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (MT2063_EXCLUDE_US_DECT_FREQUENCIES(pAS_Info->avoidDECT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Exclude LO1 values that conflict with DECT channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MT2063_AddExclZone(pAS_Info, 1920836000 - pAS_Info->f_in, 1922236000 - pAS_Info->f_in); /* Ctr = 1921.536 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MT2063_AddExclZone(pAS_Info, 1922564000 - pAS_Info->f_in, 1923964000 - pAS_Info->f_in); /* Ctr = 1923.264 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MT2063_AddExclZone(pAS_Info, 1924292000 - pAS_Info->f_in, 1925692000 - pAS_Info->f_in); /* Ctr = 1924.992 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MT2063_AddExclZone(pAS_Info, 1926020000 - pAS_Info->f_in, 1927420000 - pAS_Info->f_in); /* Ctr = 1926.720 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MT2063_AddExclZone(pAS_Info, 1927748000 - pAS_Info->f_in, 1929148000 - pAS_Info->f_in); /* Ctr = 1928.448 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(pAS_Info->avoidDECT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MT2063_AddExclZone(pAS_Info, 1896644000 - pAS_Info->f_in, 1898044000 - pAS_Info->f_in); /* Ctr = 1897.344 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MT2063_AddExclZone(pAS_Info, 1894916000 - pAS_Info->f_in, 1896316000 - pAS_Info->f_in); /* Ctr = 1895.616 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MT2063_AddExclZone(pAS_Info, 1893188000 - pAS_Info->f_in, 1894588000 - pAS_Info->f_in); /* Ctr = 1893.888 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MT2063_AddExclZone(pAS_Info, 1891460000 - pAS_Info->f_in, 1892860000 - pAS_Info->f_in); /* Ctr = 1892.16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MT2063_AddExclZone(pAS_Info, 1889732000 - pAS_Info->f_in, 1891132000 - pAS_Info->f_in); /* Ctr = 1890.432 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MT2063_AddExclZone(pAS_Info, 1888004000 - pAS_Info->f_in, 1889404000 - pAS_Info->f_in); /* Ctr = 1888.704 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MT2063_AddExclZone(pAS_Info, 1886276000 - pAS_Info->f_in, 1887676000 - pAS_Info->f_in); /* Ctr = 1886.976 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MT2063_AddExclZone(pAS_Info, 1884548000 - pAS_Info->f_in, 1885948000 - pAS_Info->f_in); /* Ctr = 1885.248 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MT2063_AddExclZone(pAS_Info, 1882820000 - pAS_Info->f_in, 1884220000 - pAS_Info->f_in); /* Ctr = 1883.52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MT2063_AddExclZone(pAS_Info, 1881092000 - pAS_Info->f_in, 1882492000 - pAS_Info->f_in); /* Ctr = 1881.792 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * MT_ChooseFirstIF - Choose the best available 1st IF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * If f_Desired is not excluded, choose that first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * Otherwise, return the value closest to f_Center that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * not excluded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static u32 MT2063_ChooseFirstIF(struct MT2063_AvoidSpursData_t *pAS_Info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * Update "f_Desired" to be the nearest "combinational-multiple" of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * "f_LO1_Step".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * The resulting number, F_LO1 must be a multiple of f_LO1_Step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * And F_LO1 is the arithmetic sum of f_in + f_Center.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * Neither f_in, nor f_Center must be a multiple of f_LO1_Step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * However, the sum must be.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) const u32 f_Desired =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pAS_Info->f_LO1_Step *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ((pAS_Info->f_if1_Request + pAS_Info->f_in +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pAS_Info->f_LO1_Step / 2) / pAS_Info->f_LO1_Step) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pAS_Info->f_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) const u32 f_Step =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) (pAS_Info->f_LO1_Step >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) pAS_Info->f_LO2_Step) ? pAS_Info->f_LO1_Step : pAS_Info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) f_LO2_Step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 f_Center;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) s32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) s32 j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 bDesiredExcluded = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 bZeroExcluded = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) s32 tmpMin, tmpMax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) s32 bestDiff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct MT2063_ExclZone_t *pNode = pAS_Info->usedZones;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct MT2063_FIFZone_t zones[MT2063_MAX_ZONES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (pAS_Info->nZones == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return f_Desired;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * f_Center needs to be an integer multiple of f_Step away
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * from f_Desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (pAS_Info->f_if1_Center > f_Desired)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) f_Center =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) f_Desired +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) f_Step *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ((pAS_Info->f_if1_Center - f_Desired +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) f_Step / 2) / f_Step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) f_Center =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) f_Desired -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) f_Step *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ((f_Desired - pAS_Info->f_if1_Center +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) f_Step / 2) / f_Step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * Take MT_ExclZones, center around f_Center and change the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * resolution to f_Step
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) while (pNode != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* floor function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) tmpMin =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) floor((s32) (pNode->min_ - f_Center), (s32) f_Step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* ceil function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) tmpMax =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ceil((s32) (pNode->max_ - f_Center), (s32) f_Step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if ((pNode->min_ < f_Desired) && (pNode->max_ > f_Desired))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) bDesiredExcluded = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if ((tmpMin < 0) && (tmpMax > 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) bZeroExcluded = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* See if this zone overlaps the previous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if ((j > 0) && (tmpMin < zones[j - 1].max_))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) zones[j - 1].max_ = tmpMax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Add new zone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) zones[j].min_ = tmpMin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) zones[j].max_ = tmpMax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pNode = pNode->next_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * If the desired is okay, return with it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (bDesiredExcluded == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return f_Desired;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * If the desired is excluded and the center is okay, return with it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (bZeroExcluded == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return f_Center;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Find the value closest to 0 (f_Center) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) bestDiff = zones[0].min_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) for (i = 0; i < j; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (abs(zones[i].min_) < abs(bestDiff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) bestDiff = zones[i].min_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (abs(zones[i].max_) < abs(bestDiff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) bestDiff = zones[i].max_;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (bestDiff < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return f_Center - ((u32) (-bestDiff) * f_Step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return f_Center + (bestDiff * f_Step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * IsSpurInBand() - Checks to see if a spur will be present within the IF's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * bandwidth. (fIFOut +/- fIFBW, -fIFOut +/- fIFBW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * ma mb mc md
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * <--+-+-+-------------------+-------------------+-+-+-->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * | ^ 0 ^ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * ^ b=-fIFOut+fIFBW/2 -b=+fIFOut-fIFBW/2 ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * a=-fIFOut-fIFBW/2 -a=+fIFOut+fIFBW/2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * Note that some equations are doubled to prevent round-off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * problems when calculating fIFBW/2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * @pAS_Info: Avoid Spurs information block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * @fm: If spur, amount f_IF1 has to move negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * @fp: If spur, amount f_IF1 has to move positive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * Returns 1 if an LO spur would be present, otherwise 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static u32 IsSpurInBand(struct MT2063_AvoidSpursData_t *pAS_Info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 *fm, u32 * fp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ** Calculate LO frequency settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u32 n, n0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) const u32 f_LO1 = pAS_Info->f_LO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) const u32 f_LO2 = pAS_Info->f_LO2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) const u32 d = pAS_Info->f_out + pAS_Info->f_out_bw / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) const u32 c = d - pAS_Info->f_out_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) const u32 f = pAS_Info->f_zif_bw / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) const u32 f_Scale = (f_LO1 / (UINT_MAX / 2 / pAS_Info->maxH1)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) s32 f_nsLO1, f_nsLO2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) s32 f_Spur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 ma, mb, mc, md, me, mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 lo_gcd, gd_Scale, gc_Scale, gf_Scale, hgds, hgfs, hgcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) *fm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ** For each edge (d, c & f), calculate a scale, based on the gcd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ** of f_LO1, f_LO2 and the edge value. Use the larger of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ** gcd-based scale factor or f_Scale.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) lo_gcd = gcd(f_LO1, f_LO2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) gd_Scale = max((u32) gcd(lo_gcd, d), f_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) hgds = gd_Scale / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) gc_Scale = max((u32) gcd(lo_gcd, c), f_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) hgcs = gc_Scale / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) gf_Scale = max((u32) gcd(lo_gcd, f), f_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) hgfs = gf_Scale / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) n0 = DIV_ROUND_UP(f_LO2 - d, f_LO1 - f_LO2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Check out all multiples of LO1 from n0 to m_maxLOSpurHarmonic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) for (n = n0; n <= pAS_Info->maxH1; ++n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) md = (n * ((f_LO1 + hgds) / gd_Scale) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ((d + hgds) / gd_Scale)) / ((f_LO2 + hgds) / gd_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* If # fLO2 harmonics > m_maxLOSpurHarmonic, then no spurs present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (md >= pAS_Info->maxH1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ma = (n * ((f_LO1 + hgds) / gd_Scale) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ((d + hgds) / gd_Scale)) / ((f_LO2 + hgds) / gd_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* If no spurs between +/- (f_out + f_IFBW/2), then try next harmonic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (md == ma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) mc = (n * ((f_LO1 + hgcs) / gc_Scale) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ((c + hgcs) / gc_Scale)) / ((f_LO2 + hgcs) / gc_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (mc != md) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) f_nsLO1 = (s32) (n * (f_LO1 / gc_Scale));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) f_nsLO2 = (s32) (mc * (f_LO2 / gc_Scale));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) f_Spur =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) (gc_Scale * (f_nsLO1 - f_nsLO2)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) n * (f_LO1 % gc_Scale) - mc * (f_LO2 % gc_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) *fp = ((f_Spur - (s32) c) / (mc - n)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) *fm = (((s32) d - f_Spur) / (mc - n)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Location of Zero-IF-spur to be checked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) me = (n * ((f_LO1 + hgfs) / gf_Scale) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ((f + hgfs) / gf_Scale)) / ((f_LO2 + hgfs) / gf_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mf = (n * ((f_LO1 + hgfs) / gf_Scale) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ((f + hgfs) / gf_Scale)) / ((f_LO2 + hgfs) / gf_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (me != mf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) f_nsLO1 = n * (f_LO1 / gf_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) f_nsLO2 = me * (f_LO2 / gf_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) f_Spur =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) (gf_Scale * (f_nsLO1 - f_nsLO2)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) n * (f_LO1 % gf_Scale) - me * (f_LO2 % gf_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) *fp = ((f_Spur + (s32) f) / (me - n)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) *fm = (((s32) f - f_Spur) / (me - n)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) mb = (n * ((f_LO1 + hgcs) / gc_Scale) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ((c + hgcs) / gc_Scale)) / ((f_LO2 + hgcs) / gc_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ma != mb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) f_nsLO1 = n * (f_LO1 / gc_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) f_nsLO2 = ma * (f_LO2 / gc_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) f_Spur =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) (gc_Scale * (f_nsLO1 - f_nsLO2)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) n * (f_LO1 % gc_Scale) - ma * (f_LO2 % gc_Scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) *fp = (((s32) d + f_Spur) / (ma - n)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) *fm = (-(f_Spur + (s32) c) / (ma - n)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* No spurs found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * MT_AvoidSpurs() - Main entry point to avoid spurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * Checks for existing spurs in present LO1, LO2 freqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * and if present, chooses spur-free LO1, LO2 combination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * that tunes the same input/output frequencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static u32 MT2063_AvoidSpurs(struct MT2063_AvoidSpursData_t *pAS_Info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u32 fm, fp; /* restricted range on LO's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) pAS_Info->bSpurAvoided = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) pAS_Info->nSpursFound = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (pAS_Info->maxH1 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * Avoid LO Generated Spurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * Make sure that have no LO-related spurs within the IF output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * bandwidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * If there is an LO spur in this band, start at the current IF1 frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * and work out until we find a spur-free frequency or run up against the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * 1st IF SAW band edge. Use temporary copies of fLO1 and fLO2 so that they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * will be unchanged if a spur-free setting is not found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) pAS_Info->bSpurPresent = IsSpurInBand(pAS_Info, &fm, &fp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (pAS_Info->bSpurPresent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u32 zfIF1 = pAS_Info->f_LO1 - pAS_Info->f_in; /* current attempt at a 1st IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u32 zfLO1 = pAS_Info->f_LO1; /* current attempt at an LO1 freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 zfLO2 = pAS_Info->f_LO2; /* current attempt at an LO2 freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u32 delta_IF1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u32 new_IF1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ** Spur was found, attempt to find a spur-free 1st IF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) pAS_Info->nSpursFound++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* Raise f_IF1_upper, if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) MT2063_AddExclZone(pAS_Info, zfIF1 - fm, zfIF1 + fp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* Choose next IF1 that is closest to f_IF1_CENTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) new_IF1 = MT2063_ChooseFirstIF(pAS_Info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (new_IF1 > zfIF1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) pAS_Info->f_LO1 += (new_IF1 - zfIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) pAS_Info->f_LO2 += (new_IF1 - zfIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) pAS_Info->f_LO1 -= (zfIF1 - new_IF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pAS_Info->f_LO2 -= (zfIF1 - new_IF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) zfIF1 = new_IF1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (zfIF1 > pAS_Info->f_if1_Center)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) delta_IF1 = zfIF1 - pAS_Info->f_if1_Center;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) delta_IF1 = pAS_Info->f_if1_Center - zfIF1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) pAS_Info->bSpurPresent = IsSpurInBand(pAS_Info, &fm, &fp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * Continue while the new 1st IF is still within the 1st IF bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * and there is a spur in the band (again)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) } while ((2 * delta_IF1 + pAS_Info->f_out_bw <= pAS_Info->f_if1_bw) && pAS_Info->bSpurPresent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * Use the LO-spur free values found. If the search went all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * the way to the 1st IF band edge and always found spurs, just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * leave the original choice. It's as "good" as any other.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (pAS_Info->bSpurPresent == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) status |= MT2063_SPUR_PRESENT_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) pAS_Info->f_LO1 = zfLO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) pAS_Info->f_LO2 = zfLO2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) pAS_Info->bSpurAvoided = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ((pAS_Info->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) nSpursFound << MT2063_SPUR_SHIFT) & MT2063_SPUR_CNT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * Constants used by the tuning algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define MT2063_REF_FREQ (16000000UL) /* Reference oscillator Frequency (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define MT2063_IF1_BW (22000000UL) /* The IF1 filter bandwidth (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define MT2063_TUNE_STEP_SIZE (50000UL) /* Tune in steps of 50 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define MT2063_SPUR_STEP_HZ (250000UL) /* Step size (in Hz) to move IF1 when avoiding spurs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define MT2063_ZIF_BW (2000000UL) /* Zero-IF spur-free bandwidth (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define MT2063_MAX_HARMONICS_1 (15UL) /* Highest intra-tuner LO Spur Harmonic to be avoided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define MT2063_MAX_HARMONICS_2 (5UL) /* Highest inter-tuner LO Spur Harmonic to be avoided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define MT2063_MIN_LO_SEP (1000000UL) /* Minimum inter-tuner LO frequency separation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define MT2063_LO1_FRACN_AVOID (0UL) /* LO1 FracN numerator avoid region (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define MT2063_LO2_FRACN_AVOID (199999UL) /* LO2 FracN numerator avoid region (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define MT2063_MIN_FIN_FREQ (44000000UL) /* Minimum input frequency (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define MT2063_MAX_FIN_FREQ (1100000000UL) /* Maximum input frequency (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define MT2063_MIN_FOUT_FREQ (36000000UL) /* Minimum output frequency (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define MT2063_MAX_FOUT_FREQ (57000000UL) /* Maximum output frequency (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define MT2063_MIN_DNC_FREQ (1293000000UL) /* Minimum LO2 frequency (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define MT2063_MAX_DNC_FREQ (1614000000UL) /* Maximum LO2 frequency (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define MT2063_MIN_UPC_FREQ (1396000000UL) /* Minimum LO1 frequency (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define MT2063_MAX_UPC_FREQ (2750000000UL) /* Maximum LO1 frequency (in Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * Define the supported Part/Rev codes for the MT2063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define MT2063_B0 (0x9B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define MT2063_B1 (0x9C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define MT2063_B2 (0x9D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define MT2063_B3 (0x9E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * mt2063_lockStatus - Checks to see if LO1 and LO2 are locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * @state: struct mt2063_state pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * This function returns 0, if no lock, 1 if locked and a value < 1 if error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int mt2063_lockStatus(struct mt2063_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) const u32 nMaxWait = 100; /* wait a maximum of 100 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) const u32 nPollRate = 2; /* poll status bits every 2 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) const u32 nMaxLoops = nMaxWait / nPollRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) const u8 LO1LK = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) u8 LO2LK = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u32 nDelays = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* LO2 Lock bit was in a different place for B0 version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (state->tuner_id == MT2063_B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) LO2LK = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) status = mt2063_read(state, MT2063_REG_LO_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) &state->reg[MT2063_REG_LO_STATUS], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) (LO1LK | LO2LK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return TUNER_STATUS_LOCKED | TUNER_STATUS_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) msleep(nPollRate); /* Wait between retries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) } while (++nDelays < nMaxLoops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * Got no lock or partial lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * Constants for setting receiver modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * (6 modes defined at this time, enumerated by mt2063_delivery_sys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * (DNC1GC & DNC2GC are the values, which are used, when the specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * DNC Output is selected, the other is always off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * enum mt2063_delivery_sys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * -------------+----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * Mode 0 : | MT2063_CABLE_QAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * Mode 1 : | MT2063_CABLE_ANALOG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * Mode 2 : | MT2063_OFFAIR_COFDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * Mode 3 : | MT2063_OFFAIR_COFDM_SAWLESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * Mode 4 : | MT2063_OFFAIR_ANALOG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * Mode 5 : | MT2063_OFFAIR_8VSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * --------------+----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * |<---------- Mode -------------->|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * Reg Field | 0 | 1 | 2 | 3 | 4 | 5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * ------------+-----+-----+-----+-----+-----+-----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * RFAGCen | OFF | OFF | OFF | OFF | OFF | OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * LNARin | 0 | 0 | 3 | 3 | 3 | 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * FIFFQen | 1 | 1 | 1 | 1 | 1 | 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * FIFFq | 0 | 0 | 0 | 0 | 0 | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * DNC1gc | 0 | 0 | 0 | 0 | 0 | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * DNC2gc | 0 | 0 | 0 | 0 | 0 | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * GCU Auto | 1 | 1 | 1 | 1 | 1 | 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * LNA max Atn | 31 | 31 | 31 | 31 | 31 | 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * LNA Target | 44 | 43 | 43 | 43 | 43 | 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * ign RF Ovl | 0 | 0 | 0 | 0 | 0 | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * RF max Atn | 31 | 31 | 31 | 31 | 31 | 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * PD1 Target | 36 | 36 | 38 | 38 | 36 | 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * ign FIF Ovl | 0 | 0 | 0 | 0 | 0 | 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * FIF max Atn | 5 | 5 | 5 | 5 | 5 | 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * PD2 Target | 40 | 33 | 42 | 42 | 33 | 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) enum mt2063_delivery_sys {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) MT2063_CABLE_QAM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) MT2063_CABLE_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) MT2063_OFFAIR_COFDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) MT2063_OFFAIR_COFDM_SAWLESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) MT2063_OFFAIR_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) MT2063_OFFAIR_8VSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) MT2063_NUM_RCVR_MODES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const char *mt2063_mode_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) [MT2063_CABLE_QAM] = "digital cable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) [MT2063_CABLE_ANALOG] = "analog cable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) [MT2063_OFFAIR_COFDM] = "digital offair",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) [MT2063_OFFAIR_COFDM_SAWLESS] = "digital offair without SAW",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [MT2063_OFFAIR_ANALOG] = "analog offair",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) [MT2063_OFFAIR_8VSB] = "analog offair 8vsb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static const u8 RFAGCEN[] = { 0, 0, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static const u8 LNARIN[] = { 0, 0, 3, 3, 3, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static const u8 FIFFQEN[] = { 1, 1, 1, 1, 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static const u8 FIFFQ[] = { 0, 0, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static const u8 DNC1GC[] = { 0, 0, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static const u8 DNC2GC[] = { 0, 0, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static const u8 ACLNAMAX[] = { 31, 31, 31, 31, 31, 31 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static const u8 LNATGT[] = { 44, 43, 43, 43, 43, 43 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static const u8 RFOVDIS[] = { 0, 0, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static const u8 ACRFMAX[] = { 31, 31, 31, 31, 31, 31 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const u8 PD1TGT[] = { 36, 36, 38, 38, 36, 38 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const u8 FIFOVDIS[] = { 0, 0, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static const u8 ACFIFMAX[] = { 29, 29, 29, 29, 29, 29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static const u8 PD2TGT[] = { 40, 33, 38, 42, 30, 38 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * mt2063_set_dnc_output_enable()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static u32 mt2063_get_dnc_output_enable(struct mt2063_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) enum MT2063_DNC_Output_Enable *pValue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if ((state->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) *pValue = MT2063_DNC_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) *pValue = MT2063_DNC_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) } else { /* DNC1 is on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) *pValue = MT2063_DNC_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) *pValue = MT2063_DNC_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * mt2063_set_dnc_output_enable()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) enum MT2063_DNC_Output_Enable nValue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) int status = 0; /* Status to be returned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* selects, which DNC output is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) switch (nValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) case MT2063_DNC_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (state->reg[MT2063_REG_DNC_GAIN] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) mt2063_setreg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) MT2063_REG_DNC_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (state->reg[MT2063_REG_VGA_GAIN] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) mt2063_setreg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) MT2063_REG_VGA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (state->reg[MT2063_REG_RSVD_20] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) mt2063_setreg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) MT2063_REG_RSVD_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) case MT2063_DNC_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (state->reg[MT2063_REG_DNC_GAIN] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) mt2063_setreg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) MT2063_REG_DNC_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (state->reg[MT2063_REG_VGA_GAIN] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) mt2063_setreg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) MT2063_REG_VGA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (state->reg[MT2063_REG_RSVD_20] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) mt2063_setreg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) MT2063_REG_RSVD_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) case MT2063_DNC_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (state->reg[MT2063_REG_DNC_GAIN] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) mt2063_setreg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) MT2063_REG_DNC_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (state->reg[MT2063_REG_VGA_GAIN] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) mt2063_setreg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) MT2063_REG_VGA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (state->reg[MT2063_REG_RSVD_20] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) mt2063_setreg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) MT2063_REG_RSVD_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) case MT2063_DNC_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (state->reg[MT2063_REG_DNC_GAIN] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) mt2063_setreg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) MT2063_REG_DNC_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (state->reg[MT2063_REG_VGA_GAIN] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) mt2063_setreg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) MT2063_REG_VGA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (state->reg[MT2063_REG_RSVD_20] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) mt2063_setreg(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) MT2063_REG_RSVD_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * MT2063_SetReceiverMode() - Set the MT2063 receiver mode, according with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * the selected enum mt2063_delivery_sys type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * (DNC1GC & DNC2GC are the values, which are used, when the specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * DNC Output is selected, the other is always off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * @state: ptr to mt2063_state structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * @Mode: desired receiver delivery system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * Note: Register cache must be valid for it to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) enum mt2063_delivery_sys Mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) int status = 0; /* Status to be returned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) u32 longval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (Mode >= MT2063_NUM_RCVR_MODES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) status = -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* RFAGCen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) (state->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) reg[MT2063_REG_PD1_TGT] & ~0x40) | (RFAGCEN[Mode]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ? 0x40 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (state->reg[MT2063_REG_PD1_TGT] != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* LNARin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) u8 val = (state->reg[MT2063_REG_CTRL_2C] & ~0x03) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) (LNARIN[Mode] & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (state->reg[MT2063_REG_CTRL_2C] != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) status |= mt2063_setreg(state, MT2063_REG_CTRL_2C, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* FIFFQEN and FIFFQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) (state->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) reg[MT2063_REG_FIFF_CTRL2] & ~0xF0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) (FIFFQEN[Mode] << 7) | (FIFFQ[Mode] << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (state->reg[MT2063_REG_FIFF_CTRL2] != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) mt2063_setreg(state, MT2063_REG_FIFF_CTRL2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* trigger FIFF calibration, needed after changing FIFFQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) (state->reg[MT2063_REG_FIFF_CTRL] | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) (state->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) reg[MT2063_REG_FIFF_CTRL] & ~0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* DNC1GC & DNC2GC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) status |= mt2063_get_dnc_output_enable(state, &longval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) status |= mt2063_set_dnc_output_enable(state, longval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* acLNAmax */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) u8 val = (state->reg[MT2063_REG_LNA_OV] & ~0x1F) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) (ACLNAMAX[Mode] & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (state->reg[MT2063_REG_LNA_OV] != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) status |= mt2063_setreg(state, MT2063_REG_LNA_OV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* LNATGT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) u8 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x3F) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) (LNATGT[Mode] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (state->reg[MT2063_REG_LNA_TGT] != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* ACRF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) u8 val = (state->reg[MT2063_REG_RF_OV] & ~0x1F) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) (ACRFMAX[Mode] & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (state->reg[MT2063_REG_RF_OV] != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) status |= mt2063_setreg(state, MT2063_REG_RF_OV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* PD1TGT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) u8 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x3F) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) (PD1TGT[Mode] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (state->reg[MT2063_REG_PD1_TGT] != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* FIFATN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) u8 val = ACFIFMAX[Mode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (state->reg[MT2063_REG_PART_REV] != MT2063_B3 && val > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) val = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) val = (state->reg[MT2063_REG_FIF_OV] & ~0x1F) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) (val & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (state->reg[MT2063_REG_FIF_OV] != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) status |= mt2063_setreg(state, MT2063_REG_FIF_OV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* PD2TGT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) u8 val = (state->reg[MT2063_REG_PD2_TGT] & ~0x3F) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) (PD2TGT[Mode] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (state->reg[MT2063_REG_PD2_TGT] != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) status |= mt2063_setreg(state, MT2063_REG_PD2_TGT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* Ignore ATN Overload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) val = (state->reg[MT2063_REG_LNA_TGT] & ~0x80) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) (RFOVDIS[Mode] ? 0x80 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (state->reg[MT2063_REG_LNA_TGT] != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* Ignore FIF Overload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) val = (state->reg[MT2063_REG_PD1_TGT] & ~0x80) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) (FIFOVDIS[Mode] ? 0x80 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (state->reg[MT2063_REG_PD1_TGT] != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) state->rcvr_mode = Mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) dprintk(1, "mt2063 mode changed to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) mt2063_mode_name[state->rcvr_mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * MT2063_ClearPowerMaskBits () - Clears the power-down mask bits for various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * sections of the MT2063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * @Bits: Mask bits to be cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * See definition of MT2063_Mask_Bits type for description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * of each of the power bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static u32 MT2063_ClearPowerMaskBits(struct mt2063_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) enum MT2063_Mask_Bits Bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) Bits = (enum MT2063_Mask_Bits)(Bits & MT2063_ALL_SD); /* Only valid bits for this tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if ((Bits & 0xFF00) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) state->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) mt2063_write(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) MT2063_REG_PWR_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) &state->reg[MT2063_REG_PWR_2], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if ((Bits & 0xFF) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) mt2063_write(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) MT2063_REG_PWR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) &state->reg[MT2063_REG_PWR_1], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * MT2063_SoftwareShutdown() - Enables or disables software shutdown function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * When Shutdown is 1, any section whose power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * mask is set will be shutdown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static u32 MT2063_SoftwareShutdown(struct mt2063_state *state, u8 Shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (Shutdown == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) state->reg[MT2063_REG_PWR_1] |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) state->reg[MT2063_REG_PWR_1] &= ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) status = mt2063_write(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) MT2063_REG_PWR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) &state->reg[MT2063_REG_PWR_1], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (Shutdown != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) state->reg[MT2063_REG_BYP_CTRL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) (state->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) mt2063_write(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) MT2063_REG_BYP_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) &state->reg[MT2063_REG_BYP_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) state->reg[MT2063_REG_BYP_CTRL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) (state->reg[MT2063_REG_BYP_CTRL] & 0x9F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) mt2063_write(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) MT2063_REG_BYP_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) &state->reg[MT2063_REG_BYP_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) static u32 MT2063_Round_fLO(u32 f_LO, u32 f_LO_Step, u32 f_ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return f_ref * (f_LO / f_ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) + f_LO_Step * (((f_LO % f_ref) + (f_LO_Step / 2)) / f_LO_Step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * fLO_FractionalTerm() - Calculates the portion contributed by FracN / denom.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * This function preserves maximum precision without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * risk of overflow. It accurately calculates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * f_ref * num / denom to within 1 HZ with fixed math.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * @f_ref: SRO frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * @num: Fractional portion of the multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * @denom: denominator portion of the ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * This calculation handles f_ref as two separate 14-bit fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * Therefore, a maximum value of 2^28-1 may safely be used for f_ref.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * This is the genesis of the magic number "14" and the magic mask value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * 0x03FFF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * This routine successfully handles denom values up to and including 2^18.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * Returns: f_ref * num / denom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static u32 MT2063_fLO_FractionalTerm(u32 f_ref, u32 num, u32 denom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) u32 t1 = (f_ref >> 14) * num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) u32 term1 = t1 / denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) u32 loss = t1 % denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) u32 term2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) (((f_ref & 0x00003FFF) * num + (loss << 14)) + (denom / 2)) / denom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return (term1 << 14) + term2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * CalcLO1Mult()- Calculates Integer divider value and the numerator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * value for a FracN PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * This function assumes that the f_LO and f_Ref are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * evenly divisible by f_LO_Step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * @Div: OUTPUT: Whole number portion of the multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * @FracN: OUTPUT: Fractional portion of the multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * @f_LO: desired LO frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * @f_LO_Step: Minimum step size for the LO (in Hz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * @f_Ref: SRO frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) * @f_Avoid: Range of PLL frequencies to avoid near integer multiples
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * of f_Ref (in Hz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * Returns: Recalculated LO frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static u32 MT2063_CalcLO1Mult(u32 *Div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) u32 *FracN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) u32 f_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) u32 f_LO_Step, u32 f_Ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* Calculate the whole number portion of the divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) *Div = f_LO / f_Ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* Calculate the numerator value (round to nearest f_LO_Step) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) *FracN =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) (64 * (((f_LO % f_Ref) + (f_LO_Step / 2)) / f_LO_Step) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) (f_Ref / f_LO_Step / 2)) / (f_Ref / f_LO_Step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return (f_Ref * (*Div)) + MT2063_fLO_FractionalTerm(f_Ref, *FracN, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) * CalcLO2Mult() - Calculates Integer divider value and the numerator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * value for a FracN PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * This function assumes that the f_LO and f_Ref are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * evenly divisible by f_LO_Step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * @Div: OUTPUT: Whole number portion of the multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * @FracN: OUTPUT: Fractional portion of the multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * @f_LO: desired LO frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * @f_LO_Step: Minimum step size for the LO (in Hz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * @f_Ref: SRO frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * Returns: Recalculated LO frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static u32 MT2063_CalcLO2Mult(u32 *Div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) u32 *FracN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) u32 f_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) u32 f_LO_Step, u32 f_Ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* Calculate the whole number portion of the divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) *Div = f_LO / f_Ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /* Calculate the numerator value (round to nearest f_LO_Step) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) *FracN =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) (8191 * (((f_LO % f_Ref) + (f_LO_Step / 2)) / f_LO_Step) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) (f_Ref / f_LO_Step / 2)) / (f_Ref / f_LO_Step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return (f_Ref * (*Div)) + MT2063_fLO_FractionalTerm(f_Ref, *FracN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) 8191);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) * FindClearTuneFilter() - Calculate the corrrect ClearTune filter to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) * used for a given input frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * @state: ptr to tuner data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * @f_in: RF input center frequency (in Hz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) * Returns: ClearTune filter number (0-31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static u32 FindClearTuneFilter(struct mt2063_state *state, u32 f_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) u32 RFBand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) u32 idx; /* index loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) ** Find RF Band setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) RFBand = 31; /* def when f_in > all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) for (idx = 0; idx < 31; ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (state->CTFiltMax[idx] >= f_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) RFBand = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return RFBand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * MT2063_Tune() - Change the tuner's tuned frequency to RFin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static u32 MT2063_Tune(struct mt2063_state *state, u32 f_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) { /* RF input center frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) u32 LO1; /* 1st LO register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) u32 Num1; /* Numerator for LO1 reg. value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) u32 f_IF1; /* 1st IF requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) u32 LO2; /* 2nd LO register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) u32 Num2; /* Numerator for LO2 reg. value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) u32 ofLO1, ofLO2; /* last time's LO frequencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) u8 fiffc = 0x80; /* FIFF center freq from tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) u32 fiffof; /* Offset from FIFF center freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) const u8 LO1LK = 0x80; /* Mask for LO1 Lock bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) u8 LO2LK = 0x08; /* Mask for LO2 Lock bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) u32 RFBand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) /* Check the input and output frequency ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if ((f_in < MT2063_MIN_FIN_FREQ) || (f_in > MT2063_MAX_FIN_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if ((state->AS_Data.f_out < MT2063_MIN_FOUT_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) || (state->AS_Data.f_out > MT2063_MAX_FOUT_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * Save original LO1 and LO2 register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ofLO1 = state->AS_Data.f_LO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) ofLO2 = state->AS_Data.f_LO2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * Find and set RF Band setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) if (state->ctfilt_sw == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (state->reg[MT2063_REG_CTUNE_CTRL] != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) mt2063_setreg(state, MT2063_REG_CTUNE_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) val = state->reg[MT2063_REG_CTUNE_OV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) RFBand = FindClearTuneFilter(state, f_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) state->reg[MT2063_REG_CTUNE_OV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) (u8) ((state->reg[MT2063_REG_CTUNE_OV] & ~0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) | RFBand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (state->reg[MT2063_REG_CTUNE_OV] != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) mt2063_setreg(state, MT2063_REG_CTUNE_OV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * Read the FIFF Center Frequency from the tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) mt2063_read(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) MT2063_REG_FIFFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) &state->reg[MT2063_REG_FIFFC], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) fiffc = state->reg[MT2063_REG_FIFFC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) * Assign in the requested values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) state->AS_Data.f_in = f_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* Request a 1st IF such that LO1 is on a step size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) state->AS_Data.f_if1_Request =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) MT2063_Round_fLO(state->AS_Data.f_if1_Request + f_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) state->AS_Data.f_LO1_Step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) state->AS_Data.f_ref) - f_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) * Calculate frequency settings. f_IF1_FREQ + f_in is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * desired LO1 frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) MT2063_ResetExclZones(&state->AS_Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) f_IF1 = MT2063_ChooseFirstIF(&state->AS_Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) state->AS_Data.f_LO1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) MT2063_Round_fLO(f_IF1 + f_in, state->AS_Data.f_LO1_Step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) state->AS_Data.f_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) state->AS_Data.f_LO2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) * Check for any LO spurs in the output bandwidth and adjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) * the LO settings to avoid them if needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) status |= MT2063_AvoidSpurs(&state->AS_Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) * MT_AvoidSpurs spurs may have changed the LO1 & LO2 values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) * Recalculate the LO frequencies and the values to be placed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) * in the tuning registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) state->AS_Data.f_LO1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) MT2063_CalcLO1Mult(&LO1, &Num1, state->AS_Data.f_LO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) state->AS_Data.f_LO1_Step, state->AS_Data.f_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) state->AS_Data.f_LO2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) state->AS_Data.f_LO2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) MT2063_CalcLO2Mult(&LO2, &Num2, state->AS_Data.f_LO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * Check the upconverter and downconverter frequency ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if ((state->AS_Data.f_LO1 < MT2063_MIN_UPC_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) || (state->AS_Data.f_LO1 > MT2063_MAX_UPC_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) status |= MT2063_UPC_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if ((state->AS_Data.f_LO2 < MT2063_MIN_DNC_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) || (state->AS_Data.f_LO2 > MT2063_MAX_DNC_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) status |= MT2063_DNC_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) /* LO2 Lock bit was in a different place for B0 version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (state->tuner_id == MT2063_B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) LO2LK = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * If we have the same LO frequencies and we're already locked,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * then skip re-programming the LO registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if ((ofLO1 != state->AS_Data.f_LO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) || (ofLO2 != state->AS_Data.f_LO2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) || ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) (LO1LK | LO2LK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) * Calculate the FIFFOF register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) * IF1_Actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) * FIFFOF = ------------ - 8 * FIFFC - 4992
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) * f_ref/64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) fiffof =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) (state->AS_Data.f_LO1 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) f_in) / (state->AS_Data.f_ref / 64) - 8 * (u32) fiffc -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) 4992;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (fiffof > 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) fiffof = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) * Place all of the calculated values into the local tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) * register fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (status >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) state->reg[MT2063_REG_LO1CQ_1] = (u8) (LO1 & 0xFF); /* DIV1q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) state->reg[MT2063_REG_LO1CQ_2] = (u8) (Num1 & 0x3F); /* NUM1q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) state->reg[MT2063_REG_LO2CQ_1] = (u8) (((LO2 & 0x7F) << 1) /* DIV2q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) |(Num2 >> 12)); /* NUM2q (hi) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) state->reg[MT2063_REG_LO2CQ_2] = (u8) ((Num2 & 0x0FF0) >> 4); /* NUM2q (mid) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) state->reg[MT2063_REG_LO2CQ_3] = (u8) (0xE0 | (Num2 & 0x000F)); /* NUM2q (lo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * Now write out the computed register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) * IMPORTANT: There is a required order for writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) * (0x05 must follow all the others).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) status |= mt2063_write(state, MT2063_REG_LO1CQ_1, &state->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (state->tuner_id == MT2063_B0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) /* Re-write the one-shot bits to trigger the tune operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) status |= mt2063_write(state, MT2063_REG_LO2CQ_3, &state->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) /* Write out the FIFF offset only if it's changing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (state->reg[MT2063_REG_FIFF_OFFSET] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) (u8) fiffof) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) state->reg[MT2063_REG_FIFF_OFFSET] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) (u8) fiffof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) mt2063_write(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) MT2063_REG_FIFF_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) &state->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) reg[MT2063_REG_FIFF_OFFSET],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) * Check for LO's locking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) status = mt2063_lockStatus(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) return -EINVAL; /* Couldn't lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) * If we locked OK, assign calculated data to mt2063_state structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) state->f_IF1_actual = state->AS_Data.f_LO1 - f_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) static const u8 MT2063B0_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /* Reg, Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) 0x19, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) 0x1B, 0x1D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) 0x1C, 0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) 0x1D, 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) 0x1E, 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) 0x1F, 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) 0x20, 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) 0x22, 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) 0x23, 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) 0x24, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) 0x25, 0x3F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) 0x27, 0xEE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) 0x2C, 0x27, /* bit at 0x20 is cleared below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) 0x30, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) 0x2C, 0x07, /* bit at 0x20 is cleared here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) 0x2D, 0x87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) 0x2E, 0xAA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) 0x28, 0xE1, /* Set the FIFCrst bit here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) 0x28, 0xE0, /* Clear the FIFCrst bit here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) static const u8 MT2063B1_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /* Reg, Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) 0x05, 0xF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) 0x11, 0x10, /* New Enable AFCsd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) 0x19, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) 0x1A, 0x6C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) 0x1B, 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) 0x1C, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) 0x1D, 0x8F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) 0x1E, 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) 0x1F, 0x8F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) 0x20, 0x57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) 0x22, 0x21, /* New - ver 1.03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) 0x23, 0x3C, /* New - ver 1.10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) 0x24, 0x20, /* New - ver 1.03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) 0x2C, 0x24, /* bit at 0x20 is cleared below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) 0x2D, 0x87, /* FIFFQ=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) 0x2F, 0xF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) 0x30, 0x0C, /* New - ver 1.11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) 0x31, 0x1B, /* New - ver 1.11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) 0x2C, 0x04, /* bit at 0x20 is cleared here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) 0x28, 0xE1, /* Set the FIFCrst bit here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) 0x28, 0xE0, /* Clear the FIFCrst bit here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static const u8 MT2063B3_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) /* Reg, Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) 0x05, 0xF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) 0x19, 0x3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) 0x2C, 0x24, /* bit at 0x20 is cleared below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) 0x2C, 0x04, /* bit at 0x20 is cleared here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) 0x28, 0xE1, /* Set the FIFCrst bit here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) 0x28, 0xE0, /* Clear the FIFCrst bit here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) static int mt2063_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) struct mt2063_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) u8 all_resets = 0xF0; /* reset/load bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) const u8 *def = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) char *step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) u32 FCRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) s32 maxReads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) u32 fcu_osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) state->rcvr_mode = MT2063_CABLE_QAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) /* Read the Part/Rev code from the tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) status = mt2063_read(state, MT2063_REG_PART_REV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) &state->reg[MT2063_REG_PART_REV], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) printk(KERN_ERR "Can't read mt2063 part ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) /* Check the part/rev code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) switch (state->reg[MT2063_REG_PART_REV]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) case MT2063_B0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) step = "B0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) case MT2063_B1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) step = "B1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) case MT2063_B2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) step = "B2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) case MT2063_B3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) step = "B3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) printk(KERN_ERR "mt2063: Unknown mt2063 device ID (0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) state->reg[MT2063_REG_PART_REV]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return -ENODEV; /* Wrong tuner Part/Rev code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* Check the 2nd byte of the Part/Rev code from the tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) status = mt2063_read(state, MT2063_REG_RSVD_3B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) &state->reg[MT2063_REG_RSVD_3B], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) /* b7 != 0 ==> NOT MT2063 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if (status < 0 || ((state->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) printk(KERN_ERR "mt2063: Unknown part ID (0x%02x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) state->reg[MT2063_REG_PART_REV],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) state->reg[MT2063_REG_RSVD_3B]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return -ENODEV; /* Wrong tuner Part/Rev code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) printk(KERN_INFO "mt2063: detected a mt2063 %s\n", step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) /* Reset the tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) status = mt2063_write(state, MT2063_REG_LO2CQ_3, &all_resets, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /* change all of the default values that vary from the HW reset values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* def = (state->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) switch (state->reg[MT2063_REG_PART_REV]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) case MT2063_B3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) def = MT2063B3_defaults;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) case MT2063_B1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) def = MT2063B1_defaults;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) case MT2063_B0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) def = MT2063B0_defaults;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) while (status >= 0 && *def) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) u8 reg = *def++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) u8 val = *def++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) status = mt2063_write(state, reg, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /* Wait for FIFF location to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) FCRUN = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) maxReads = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) msleep(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) status = mt2063_read(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) MT2063_REG_XO_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) &state->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) reg[MT2063_REG_XO_STATUS], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) FCRUN = (state->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (FCRUN != 0 || status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) status = mt2063_read(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) MT2063_REG_FIFFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) &state->reg[MT2063_REG_FIFFC], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /* Read back all the registers from the tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) status = mt2063_read(state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) MT2063_REG_PART_REV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) state->reg, MT2063_REG_END_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) /* Initialize the tuner state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) state->tuner_id = state->reg[MT2063_REG_PART_REV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) state->AS_Data.f_ref = MT2063_REF_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) state->AS_Data.f_if1_Center = (state->AS_Data.f_ref / 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ((u32) state->reg[MT2063_REG_FIFFC] + 640);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) state->AS_Data.f_if1_bw = MT2063_IF1_BW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) state->AS_Data.f_out = 43750000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) state->AS_Data.f_out_bw = 6750000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) state->AS_Data.f_zif_bw = MT2063_ZIF_BW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) state->AS_Data.f_LO1_Step = state->AS_Data.f_ref / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) state->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) state->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) state->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) state->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) state->AS_Data.f_if1_Request = state->AS_Data.f_if1_Center;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) state->AS_Data.f_LO1 = 2181000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) state->AS_Data.f_LO2 = 1486249786UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) state->f_IF1_actual = state->AS_Data.f_if1_Center;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) state->AS_Data.f_in = state->AS_Data.f_LO1 - state->f_IF1_actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) state->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) state->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) state->num_regs = MT2063_REG_END_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) state->AS_Data.avoidDECT = MT2063_AVOID_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) state->ctfilt_sw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) state->CTFiltMax[0] = 69230000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) state->CTFiltMax[1] = 105770000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) state->CTFiltMax[2] = 140350000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) state->CTFiltMax[3] = 177110000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) state->CTFiltMax[4] = 212860000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) state->CTFiltMax[5] = 241130000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) state->CTFiltMax[6] = 274370000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) state->CTFiltMax[7] = 309820000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) state->CTFiltMax[8] = 342450000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) state->CTFiltMax[9] = 378870000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) state->CTFiltMax[10] = 416210000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) state->CTFiltMax[11] = 456500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) state->CTFiltMax[12] = 495790000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) state->CTFiltMax[13] = 534530000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) state->CTFiltMax[14] = 572610000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) state->CTFiltMax[15] = 598970000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) state->CTFiltMax[16] = 635910000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) state->CTFiltMax[17] = 672130000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) state->CTFiltMax[18] = 714840000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) state->CTFiltMax[19] = 739660000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) state->CTFiltMax[20] = 770410000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) state->CTFiltMax[21] = 814660000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) state->CTFiltMax[22] = 846950000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) state->CTFiltMax[23] = 867820000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) state->CTFiltMax[24] = 915980000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) state->CTFiltMax[25] = 947450000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) state->CTFiltMax[26] = 983110000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) state->CTFiltMax[27] = 1021630000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) state->CTFiltMax[28] = 1061870000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) state->CTFiltMax[29] = 1098330000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) state->CTFiltMax[30] = 1138990000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) ** Fetch the FCU osc value and use it and the fRef value to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) ** scale all of the Band Max values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) status = mt2063_write(state, MT2063_REG_CTUNE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) &state->reg[MT2063_REG_CTUNE_CTRL], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /* Read the ClearTune filter calibration value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) status = mt2063_read(state, MT2063_REG_FIFFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) &state->reg[MT2063_REG_FIFFC], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) fcu_osc = state->reg[MT2063_REG_FIFFC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) state->reg[MT2063_REG_CTUNE_CTRL] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) status = mt2063_write(state, MT2063_REG_CTUNE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) &state->reg[MT2063_REG_CTUNE_CTRL], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) /* Adjust each of the values in the ClearTune filter cross-over table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) for (i = 0; i < 31; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) state->CTFiltMax[i] = (state->CTFiltMax[i] / 768) * (fcu_osc + 640);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) status = MT2063_SoftwareShutdown(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) status = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) state->init = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) static int mt2063_get_status(struct dvb_frontend *fe, u32 *tuner_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) struct mt2063_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) if (!state->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) *tuner_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) status = mt2063_lockStatus(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) *tuner_status = TUNER_STATUS_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) dprintk(1, "Tuner status: %d", *tuner_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) static void mt2063_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) struct mt2063_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) static int mt2063_set_analog_params(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) struct analog_parameters *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) struct mt2063_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) s32 pict_car;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) s32 pict2chanb_vsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) s32 ch_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) s32 if_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) s32 rcvr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) if (!state->init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) status = mt2063_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) switch (params->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) case V4L2_TUNER_RADIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) pict_car = 38900000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) ch_bw = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) pict2chanb_vsb = -(ch_bw / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) rcvr_mode = MT2063_OFFAIR_ANALOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) case V4L2_TUNER_ANALOG_TV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) rcvr_mode = MT2063_CABLE_ANALOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (params->std & ~V4L2_STD_MN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) pict_car = 38900000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) ch_bw = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) pict2chanb_vsb = -1250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) } else if (params->std & V4L2_STD_PAL_G) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) pict_car = 38900000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) ch_bw = 7000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) pict2chanb_vsb = -1250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) } else { /* PAL/SECAM standards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) pict_car = 38900000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) ch_bw = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) pict2chanb_vsb = -1250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) if_mid = pict_car - (pict2chanb_vsb + (ch_bw / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) state->AS_Data.f_LO2_Step = 125000; /* FIXME: probably 5000 for FM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) state->AS_Data.f_out = if_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) state->AS_Data.f_out_bw = ch_bw + 750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) status = MT2063_SetReceiverMode(state, rcvr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) dprintk(1, "Tuning to frequency: %d, bandwidth %d, foffset %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) params->frequency, ch_bw, pict2chanb_vsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) status = MT2063_Tune(state, (params->frequency + (pict2chanb_vsb + (ch_bw / 2))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) state->frequency = params->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) * As defined on EN 300 429, the DVB-C roll-off factor is 0.15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) * So, the amount of the needed bandwidth is given by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) * Bw = Symbol_rate * (1 + 0.15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) * As such, the maximum symbol rate supported by 6 MHz is given by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) * max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) #define MAX_SYMBOL_RATE_6MHz 5217391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) static int mt2063_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) struct mt2063_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) s32 pict_car;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) s32 pict2chanb_vsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) s32 ch_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) s32 if_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) s32 rcvr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (!state->init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) status = mt2063_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) if (c->bandwidth_hz == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) if (c->bandwidth_hz <= 6000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) ch_bw = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) else if (c->bandwidth_hz <= 7000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) ch_bw = 7000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) ch_bw = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) switch (c->delivery_system) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) case SYS_DVBT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) rcvr_mode = MT2063_OFFAIR_COFDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) pict_car = 36125000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) pict2chanb_vsb = -(ch_bw / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) case SYS_DVBC_ANNEX_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) case SYS_DVBC_ANNEX_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) rcvr_mode = MT2063_CABLE_QAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) pict_car = 36125000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) pict2chanb_vsb = -(ch_bw / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if_mid = pict_car - (pict2chanb_vsb + (ch_bw / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) state->AS_Data.f_LO2_Step = 125000; /* FIXME: probably 5000 for FM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) state->AS_Data.f_out = if_mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) state->AS_Data.f_out_bw = ch_bw + 750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) status = MT2063_SetReceiverMode(state, rcvr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) dprintk(1, "Tuning to frequency: %d, bandwidth %d, foffset %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) c->frequency, ch_bw, pict2chanb_vsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) status = MT2063_Tune(state, (c->frequency + (pict2chanb_vsb + (ch_bw / 2))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) state->frequency = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) static int mt2063_get_if_frequency(struct dvb_frontend *fe, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) struct mt2063_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) if (!state->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) *freq = state->AS_Data.f_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) dprintk(1, "IF frequency: %d\n", *freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) static int mt2063_get_bandwidth(struct dvb_frontend *fe, u32 *bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) struct mt2063_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (!state->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) *bw = state->AS_Data.f_out_bw - 750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) dprintk(1, "bandwidth: %d\n", *bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) static const struct dvb_tuner_ops mt2063_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .name = "MT2063 Silicon Tuner",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .frequency_min_hz = 45 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .frequency_max_hz = 865 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .init = mt2063_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .sleep = MT2063_Sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .get_status = mt2063_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .set_analog_params = mt2063_set_analog_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .set_params = mt2063_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .get_if_frequency = mt2063_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .get_bandwidth = mt2063_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .release = mt2063_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) struct mt2063_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) struct i2c_adapter *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) struct mt2063_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) state = kzalloc(sizeof(struct mt2063_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) state->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) state->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) state->frontend = fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) state->reference = config->refclock / 1000; /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) fe->tuner_priv = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) fe->ops.tuner_ops = mt2063_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) printk(KERN_INFO "%s: Attaching MT2063\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) EXPORT_SYMBOL_GPL(mt2063_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) * Ancillary routines visible outside mt2063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) * FIXME: Remove them in favor of using standard tuner callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) static int tuner_MT2063_SoftwareShutdown(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) struct mt2063_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) err = MT2063_SoftwareShutdown(state, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) printk(KERN_ERR "%s: Couldn't shutdown\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) static int tuner_MT2063_ClearPowerMaskBits(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) struct mt2063_state *state = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) dprintk(2, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) err = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) printk(KERN_ERR "%s: Invalid parameter\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) MODULE_AUTHOR("Mauro Carvalho Chehab");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) MODULE_DESCRIPTION("MT2063 Silicon tuner");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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