^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Microtune MT2060 "Single chip dual conversion broadband tuner"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2006 Olivier DANET <odanet@caramail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef MT2060_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define MT2060_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) // Uncomment the #define below to enable spurs checking. The results where quite unconvincing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) // #define MT2060_SPURCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* This driver is based on the information available in the datasheet of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "Comtech SDVBT-3K6M" tuner ( K1000737843.pdf ) which features the MT2060 register map :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) I2C Address : 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Reg.No | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | ( defaults )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) --------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 00 | [ PART ] | [ REV ] | R = 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 01 | [ LNABAND ] | [ NUM1(5:2) ] | RW = 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 02 | [ DIV1 ] | RW = 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 03 | FM1CA | FM1SS | [ NUM1(1:0) ] | [ NUM2(3:0) ] | RW = 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 04 | NUM2(11:4) ] | RW = 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 05 | [ DIV2 ] |NUM2(12)| RW = 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 06 | L1LK | [ TAD1 ] | L2LK | [ TAD2 ] | R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 07 | [ FMF ] | R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 08 | ? | FMCAL | ? | ? | ? | ? | ? | TEMP | R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 09 | 0 | 0 | [ FMGC ] | 0 | GP02 | GP01 | 0 | RW = 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 0A | ??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 0B | 0 | 0 | 1 | 1 | 0 | 0 | [ VGAG ] | RW = 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 0C | V1CSE | 1 | 1 | 1 | 1 | 1 | 1 | 1 | RW = 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 0D | 1 | 0 | [ V1CS ] | RW = 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 0E | ??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 0F | ??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 10 | ??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 11 | [ LOTO ] | 0 | 0 | 1 | 0 | RW = 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PART : Part code : 6 for MT2060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) REV : Revision code : 3 for current revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) LNABAND : Input frequency range : ( See code for details )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) NUM1 / DIV1 / NUM2 / DIV2 : Frequencies programming ( See code for details )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) FM1CA : Calibration Start Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) FM1SS : Calibration Single Step bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) L1LK : LO1 Lock Detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) TAD1 : Tune Line ADC ( ? )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) L2LK : LO2 Lock Detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) TAD2 : Tune Line ADC ( ? )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FMF : Estimated first IF Center frequency Offset ( ? )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FM1CAL : Calibration done bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) TEMP : On chip temperature sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) FMCG : Mixer 1 Cap Gain ( ? )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GP01 / GP02 : Programmable digital outputs. Unconnected pins ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) V1CSE : LO1 VCO Automatic Capacitor Select Enable ( ? )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) V1CS : LO1 Capacitor Selection Value ( ? )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) LOTO : LO Timeout ( ? )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) VGAG : Tuner Output gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2C_ADDRESS 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_PART_REV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_LO1C1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_LO1C2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_LO2C1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_LO2C2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_LO2C3 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_LO_STATUS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define REG_FM_FREQ 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_MISC_STAT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define REG_MISC_CTRL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REG_RESERVED_A 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_VGAG 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_LO1B1 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_LO1B2 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_LOTO 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PART_REV 0x63 // The current driver works only with PART=6 and REV=3 chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct mt2060_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct mt2060_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct mt2060_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 i2c_max_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u16 if1_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 fmfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Use REG_MISC_CTRL register for sleep. That drops sleep power usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * about 0.9W (huge!). Register bit meanings are unknown, so let it be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * disabled by default to avoid possible regression. Convert driver to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * i2c model in order to enable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bool sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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