^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Microtune MT2060 "Single chip dual conversion broadband tuner"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2006 Olivier DANET <odanet@caramail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* In that file, frequencies are expressed in kiloHertz to avoid 32 bits overflows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "mt2060.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "mt2060_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "MT2060: " args); printk("\n"); }} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) // Reads a single register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int mt2060_readreg(struct mt2060_priv *priv, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { .addr = priv->cfg->i2c_address, .flags = 0, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) b = kmalloc(2, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (!b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) b[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) b[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) msg[0].buf = b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) msg[1].buf = b + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (i2c_transfer(priv->i2c, msg, 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) printk(KERN_WARNING "mt2060 I2C read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) rc = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *val = b[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) kfree(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) // Writes a single register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int mt2060_writereg(struct mt2060_priv *priv, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .addr = priv->cfg->i2c_address, .flags = 0, .len = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) buf = kmalloc(2, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) buf[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) printk(KERN_WARNING "mt2060 I2C write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) rc = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) // Writes a set of consecutive registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int mt2060_writeregs(struct mt2060_priv *priv,u8 *buf, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int rem, val_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 *xfer_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .addr = priv->cfg->i2c_address, .flags = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) xfer_buf = kmalloc(16, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!xfer_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) msg.buf = xfer_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) for (rem = len - 1; rem > 0; rem -= priv->i2c_max_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) val_len = min_t(int, rem, priv->i2c_max_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) msg.len = 1 + val_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) xfer_buf[0] = buf[0] + len - 1 - rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) memcpy(&xfer_buf[1], &buf[1 + len - 1 - rem], val_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) printk(KERN_WARNING "mt2060 I2C write failed (len=%i)\n", val_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rc = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) kfree(xfer_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) // Initialisation sequences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) // LNABAND=3, NUM1=0x3C, DIV1=0x74, NUM2=0x1080, DIV2=0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static u8 mt2060_config1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) REG_LO1C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0x3F, 0x74, 0x00, 0x08, 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) // FMCG=2, GP2=0, GP1=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static u8 mt2060_config2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) REG_MISC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0x20, 0x1E, 0x30, 0xff, 0x80, 0xff, 0x00, 0x2c, 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) // VGAG=3, V1CSE=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #ifdef MT2060_SPURCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* The function below calculates the frequency offset between the output frequency if2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) and the closer cross modulation subcarrier between lo1 and lo2 up to the tenth harmonic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int mt2060_spurcalc(u32 lo1,u32 lo2,u32 if2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int I,J;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int dia,diamin,diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) diamin=1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) for (I = 1; I < 10; I++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) J = ((2*I*lo1)/lo2+1)/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) diff = I*(int)lo1-J*(int)lo2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (diff < 0) diff=-diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dia = (diff-(int)if2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (dia < 0) dia=-dia;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (diamin > dia) diamin=dia;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return diamin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BANDWIDTH 4000 // kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Calculates the frequency offset to add to avoid spurs. Returns 0 if no offset is needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int mt2060_spurcheck(u32 lo1,u32 lo2,u32 if2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 Spur,Sp1,Sp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int I,J;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) I=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) J=1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) Spur=mt2060_spurcalc(lo1,lo2,if2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (Spur < BANDWIDTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Potential spurs detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dprintk("Spurs before : f_lo1: %d f_lo2: %d (kHz)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (int)lo1,(int)lo2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) I=1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) Sp1 = mt2060_spurcalc(lo1+I,lo2+I,if2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) Sp2 = mt2060_spurcalc(lo1-I,lo2-I,if2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (Sp1 < Sp2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) J=-J; I=-I; Spur=Sp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) Spur=Sp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) while (Spur < BANDWIDTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) I += J;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) Spur = mt2060_spurcalc(lo1+I,lo2+I,if2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dprintk("Spurs after : f_lo1: %d f_lo2: %d (kHz)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) (int)(lo1+I),(int)(lo2+I));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return I;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IF2 36150 // IF2 frequency = 36.150 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define FREF 16000 // Quartz oscillator 16 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int mt2060_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct mt2060_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int i=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 lnaband;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 f_lo1,f_lo2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 div1,num1,div2,num2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 b[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 if1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if1 = priv->if1_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) b[0] = REG_LO1B1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) b[1] = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mt2060_writeregs(priv,b,2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) freq = c->frequency / 1000; /* Hz -> kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) f_lo1 = freq + if1 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) f_lo1 = (f_lo1 / 250) * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) f_lo2 = f_lo1 - freq - IF2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) // From the Comtech datasheet, the step used is 50kHz. The tuner chip could be more precise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) f_lo2 = ((f_lo2 + 25) / 50) * 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) priv->frequency = (f_lo1 - f_lo2 - IF2) * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #ifdef MT2060_SPURCHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) // LO-related spurs detection and correction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) num1 = mt2060_spurcheck(f_lo1,f_lo2,IF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) f_lo1 += num1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) f_lo2 += num1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) //Frequency LO1 = 16MHz * (DIV1 + NUM1/64 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) num1 = f_lo1 / (FREF / 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) div1 = num1 / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) num1 &= 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) // Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) num2 = f_lo2 * 64 / (FREF / 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) div2 = num2 / 8192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) num2 &= 0x1fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (freq <= 95000) lnaband = 0xB0; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (freq <= 180000) lnaband = 0xA0; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (freq <= 260000) lnaband = 0x90; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (freq <= 335000) lnaband = 0x80; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (freq <= 425000) lnaband = 0x70; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (freq <= 480000) lnaband = 0x60; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (freq <= 570000) lnaband = 0x50; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (freq <= 645000) lnaband = 0x40; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (freq <= 730000) lnaband = 0x30; else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (freq <= 810000) lnaband = 0x20; else lnaband = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) b[0] = REG_LO1C1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) b[1] = lnaband | ((num1 >>2) & 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) b[2] = div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) b[3] = (num2 & 0x0F) | ((num1 & 3) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) b[4] = num2 >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) b[5] = ((num2 >>12) & 1) | (div2 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dprintk("IF1: %dMHz",(int)if1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dprintk("PLL freq=%dkHz f_lo1=%dkHz f_lo2=%dkHz",(int)freq,(int)f_lo1,(int)f_lo2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dprintk("PLL [1..5]: %2x %2x %2x %2x %2x",(int)b[1],(int)b[2],(int)b[3],(int)b[4],(int)b[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mt2060_writeregs(priv,b,6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) //Waits for pll lock or timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mt2060_readreg(priv,REG_LO_STATUS,b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if ((b[0] & 0x88)==0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) msleep(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } while (i<10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void mt2060_calibrate(struct mt2060_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u8 b = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (mt2060_writeregs(priv,mt2060_config1,sizeof(mt2060_config1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (mt2060_writeregs(priv,mt2060_config2,sizeof(mt2060_config2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* initialize the clock output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mt2060_writereg(priv, REG_VGAG, (priv->cfg->clock_out << 6) | 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) b |= (1 << 6); // FM1SS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mt2060_writereg(priv, REG_LO2C1,b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) b |= (1 << 7); // FM1CA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mt2060_writereg(priv, REG_LO2C1,b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) b &= ~(1 << 7); // FM1CA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) b &= ~(1 << 6); // FM1SS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mt2060_writereg(priv, REG_LO2C1,b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } while (i < 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) while (i++ < 10 && mt2060_readreg(priv, REG_MISC_STAT, &b) == 0 && (b & (1 << 6)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (i <= 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mt2060_readreg(priv, REG_FM_FREQ, &priv->fmfreq); // now find out, what is fmreq used for :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dprintk("calibration was successful: %d", (int)priv->fmfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dprintk("FMCAL timed out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int mt2060_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct mt2060_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *frequency = priv->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int mt2060_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *frequency = IF2 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int mt2060_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct mt2060_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (priv->sleep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = mt2060_writereg(priv, REG_MISC_CTRL, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) goto err_i2c_gate_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = mt2060_writereg(priv, REG_VGAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) (priv->cfg->clock_out << 6) | 0x33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) err_i2c_gate_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int mt2060_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct mt2060_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = mt2060_writereg(priv, REG_VGAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) (priv->cfg->clock_out << 6) | 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) goto err_i2c_gate_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (priv->sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = mt2060_writereg(priv, REG_MISC_CTRL, 0xe8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) err_i2c_gate_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void mt2060_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) kfree(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct dvb_tuner_ops mt2060_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .name = "Microtune MT2060",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .frequency_min_hz = 48 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .frequency_max_hz = 860 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .frequency_step_hz = 50 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .release = mt2060_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .init = mt2060_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .sleep = mt2060_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .set_params = mt2060_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .get_frequency = mt2060_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .get_if_frequency = mt2060_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* This functions tries to identify a MT2060 tuner by reading the PART/REV register. This is hasty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2060_config *cfg, u16 if1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct mt2060_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u8 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) priv = kzalloc(sizeof(struct mt2060_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) priv->cfg = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) priv->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) priv->if1_freq = if1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) priv->i2c_max_regs = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (mt2060_readreg(priv,REG_PART_REV,&id) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (id != PART_REV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) printk(KERN_INFO "MT2060: successfully identified (IF1 = %d)\n", if1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) memcpy(&fe->ops.tuner_ops, &mt2060_tuner_ops, sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mt2060_calibrate(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) EXPORT_SYMBOL(mt2060_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int mt2060_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct mt2060_platform_data *pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct mt2060_priv *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u8 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_err(&client->dev, "Cannot proceed without platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) fe = pdata->dvb_frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev->config.i2c_address = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev->config.clock_out = pdata->clock_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev->cfg = &dev->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev->i2c = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev->if1_freq = pdata->if1 ? pdata->if1 : 1220;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev->i2c_max_regs = pdata->i2c_write_max ? pdata->i2c_write_max - 1 : ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev->sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = mt2060_readreg(dev, REG_PART_REV, &chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_dbg(&client->dev, "chip id=%02x\n", chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (chip_id != PART_REV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Power on, calibrate, sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = mt2060_writereg(dev, REG_MISC_CTRL, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) mt2060_calibrate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = mt2060_writereg(dev, REG_MISC_CTRL, 0xe8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev_info(&client->dev, "Microtune MT2060 successfully identified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) memcpy(&fe->ops.tuner_ops, &mt2060_tuner_ops, sizeof(fe->ops.tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) fe->ops.tuner_ops.release = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) fe->tuner_priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) i2c_set_clientdata(client, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int mt2060_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static const struct i2c_device_id mt2060_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {"mt2060", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MODULE_DEVICE_TABLE(i2c, mt2060_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static struct i2c_driver mt2060_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .name = "mt2060",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .probe = mt2060_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .remove = mt2060_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .id_table = mt2060_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) module_i2c_driver(mt2060_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MODULE_AUTHOR("Olivier DANET");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MODULE_DESCRIPTION("Microtune MT2060 silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags