^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Mirics MSi001 silicon tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static const struct v4l2_frequency_band bands[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .type = V4L2_TUNER_RF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .rangelow = 49000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .rangehigh = 263000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .type = V4L2_TUNER_RF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .rangelow = 390000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .rangehigh = 960000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct msi001_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct v4l2_ctrl *bandwidth_auto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct v4l2_ctrl *bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct v4l2_ctrl *lna_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct v4l2_ctrl *mixer_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct v4l2_ctrl *if_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int f_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline struct msi001_dev *sd_to_msi001_dev(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return container_of(sd, struct msi001_dev, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int msi001_wreg(struct msi001_dev *dev, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Register format: 4 bits addr + 20 bits value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return spi_write(dev->spi, &data, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int msi001_set_gain(struct msi001_dev *dev, int lna_gain, int mixer_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int if_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct spi_device *spi = dev->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dev_dbg(&spi->dev, "lna=%d mixer=%d if=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) lna_gain, mixer_gain, if_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg = 1 << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reg |= (59 - if_gain) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reg |= 0 << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) reg |= (1 - mixer_gain) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) reg |= (1 - lna_gain) << 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) reg |= 4 << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg |= 0 << 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = msi001_wreg(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dev_dbg(&spi->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int msi001_set_tuner(struct msi001_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct spi_device *spi = dev->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int uitmp, div_n, k, k_thresh, k_frac, div_lo, f_if1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u64 f_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 mode, filter_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 rf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 div_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) } band_lut[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { 50000000, 0xe1, 16}, /* AM_MODE2, antenna 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {108000000, 0x42, 32}, /* VHF_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {330000000, 0x44, 16}, /* B3_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {960000000, 0x48, 4}, /* B45_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { ~0U, 0x50, 2}, /* BL_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 filter_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } if_freq_lut[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 0, 0x03}, /* Zero IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 450000, 0x02}, /* 450 kHz IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {1620000, 0x01}, /* 1.62 MHz IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {2048000, 0x00}, /* 2.048 MHz IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) } bandwidth_lut[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { 200000, 0x00}, /* 200 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { 300000, 0x01}, /* 300 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 600000, 0x02}, /* 600 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {1536000, 0x03}, /* 1.536 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {5000000, 0x04}, /* 5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {6000000, 0x05}, /* 6 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {7000000, 0x06}, /* 7 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {8000000, 0x07}, /* 8 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int f_rf = dev->f_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * bandwidth (Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * 200000, 300000, 600000, 1536000, 5000000, 6000000, 7000000, 8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * intermediate frequency (Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * 0, 450000, 1620000, 2048000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int f_if = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define F_REF 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DIV_PRE_N 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define F_VCO_STEP div_lo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_dbg(&spi->dev, "f_rf=%d f_if=%d\n", f_rf, f_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) for (i = 0; i < ARRAY_SIZE(band_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (f_rf <= band_lut[i].rf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mode = band_lut[i].mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) div_lo = band_lut[i].div_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (i == ARRAY_SIZE(band_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* AM_MODE is upconverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if ((mode >> 0) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) f_if1 = 5 * F_REF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) f_if1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) for (i = 0; i < ARRAY_SIZE(if_freq_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (f_if == if_freq_lut[i].freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) filter_mode = if_freq_lut[i].filter_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (i == ARRAY_SIZE(if_freq_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bandwidth = dev->bandwidth->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) bandwidth = clamp(bandwidth, 200000U, 8000000U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for (i = 0; i < ARRAY_SIZE(bandwidth_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (bandwidth <= bandwidth_lut[i].freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bandwidth = bandwidth_lut[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (i == ARRAY_SIZE(bandwidth_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev->bandwidth->val = bandwidth_lut[i].freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_dbg(&spi->dev, "bandwidth selected=%d\n", bandwidth_lut[i].freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Fractional-N synthesizer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * +---------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * v |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Fref +----+ +-------+ +----+ +------+ +---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * ------> | PD | --> | VCO | ------> | /4 | --> | /N.F | <-- | K |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * +----+ +-------+ +----+ +------+ +---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * +-------+ Fout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * | /Rout | ------>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * +-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Calculate PLL integer and fractional control word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) f_vco = (u64) (f_rf + f_if + f_if1) * div_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) div_n = div_u64_rem(f_vco, DIV_PRE_N * F_REF, &k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) k_thresh = (DIV_PRE_N * F_REF) / F_VCO_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) k_frac = div_u64((u64) k * k_thresh, (DIV_PRE_N * F_REF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Find out greatest common divisor and divide to smaller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) uitmp = gcd(k_thresh, k_frac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) k_thresh /= uitmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) k_frac /= uitmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Force divide to reg max. Resolution will be reduced. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) uitmp = DIV_ROUND_UP(k_thresh, 4095);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) k_thresh = DIV_ROUND_CLOSEST(k_thresh, uitmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) k_frac = DIV_ROUND_CLOSEST(k_frac, uitmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Calculate real RF set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) uitmp = (unsigned int) F_REF * DIV_PRE_N * div_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) uitmp += (unsigned int) F_REF * DIV_PRE_N * k_frac / k_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) uitmp /= div_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_dbg(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "f_rf=%u:%u f_vco=%llu div_n=%u k_thresh=%u k_frac=%u div_lo=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) f_rf, uitmp, f_vco, div_n, k_thresh, k_frac, div_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = msi001_wreg(dev, 0x00000e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = msi001_wreg(dev, 0x000003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) reg = 0 << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) reg |= mode << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) reg |= filter_mode << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) reg |= bandwidth << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) reg |= 0x02 << 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) reg |= 0x00 << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = msi001_wreg(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) reg = 5 << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) reg |= k_thresh << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) reg |= 1 << 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) reg |= 1 << 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = msi001_wreg(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) reg = 2 << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) reg |= k_frac << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) reg |= div_n << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = msi001_wreg(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret = msi001_set_gain(dev, dev->lna_gain->cur.val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev->mixer_gain->cur.val, dev->if_gain->cur.val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) reg = 6 << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) reg |= 63 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) reg |= 4095 << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = msi001_wreg(dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_dbg(&spi->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int msi001_standby(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct msi001_dev *dev = sd_to_msi001_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return msi001_wreg(dev, 0x000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int msi001_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct msi001_dev *dev = sd_to_msi001_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct spi_device *spi = dev->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_dbg(&spi->dev, "index=%d\n", v->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) strscpy(v->name, "Mirics MSi001", sizeof(v->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) v->type = V4L2_TUNER_RF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) v->rangelow = 49000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) v->rangehigh = 960000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int msi001_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct msi001_dev *dev = sd_to_msi001_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct spi_device *spi = dev->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_dbg(&spi->dev, "index=%d\n", v->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int msi001_g_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct msi001_dev *dev = sd_to_msi001_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct spi_device *spi = dev->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_dbg(&spi->dev, "tuner=%d\n", f->tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) f->frequency = dev->f_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int msi001_s_frequency(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) const struct v4l2_frequency *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct msi001_dev *dev = sd_to_msi001_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct spi_device *spi = dev->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_dbg(&spi->dev, "tuner=%d type=%d frequency=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) f->tuner, f->type, f->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (f->frequency < ((bands[0].rangehigh + bands[1].rangelow) / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) band = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev->f_tuner = clamp_t(unsigned int, f->frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) bands[band].rangelow, bands[band].rangehigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return msi001_set_tuner(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int msi001_enum_freq_bands(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct v4l2_frequency_band *band)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct msi001_dev *dev = sd_to_msi001_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct spi_device *spi = dev->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_dbg(&spi->dev, "tuner=%d type=%d index=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) band->tuner, band->type, band->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (band->index >= ARRAY_SIZE(bands))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) band->capability = bands[band->index].capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) band->rangelow = bands[band->index].rangelow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) band->rangehigh = bands[band->index].rangehigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct v4l2_subdev_tuner_ops msi001_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .standby = msi001_standby,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .g_tuner = msi001_g_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .s_tuner = msi001_s_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .g_frequency = msi001_g_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .s_frequency = msi001_s_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .enum_freq_bands = msi001_enum_freq_bands,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct v4l2_subdev_ops msi001_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .tuner = &msi001_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int msi001_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct msi001_dev *dev = container_of(ctrl->handler, struct msi001_dev, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct spi_device *spi = dev->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_dbg(&spi->dev, "id=%d name=%s val=%d min=%lld max=%lld step=%lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ctrl->id, ctrl->name, ctrl->val, ctrl->minimum, ctrl->maximum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ctrl->step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case V4L2_CID_RF_TUNER_BANDWIDTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = msi001_set_tuner(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case V4L2_CID_RF_TUNER_LNA_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = msi001_set_gain(dev, dev->lna_gain->val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev->mixer_gain->cur.val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev->if_gain->cur.val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case V4L2_CID_RF_TUNER_MIXER_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = msi001_set_gain(dev, dev->lna_gain->cur.val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev->mixer_gain->val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev->if_gain->cur.val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case V4L2_CID_RF_TUNER_IF_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = msi001_set_gain(dev, dev->lna_gain->cur.val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev->mixer_gain->cur.val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev->if_gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_dbg(&spi->dev, "unknown control %d\n", ctrl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct v4l2_ctrl_ops msi001_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .s_ctrl = msi001_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int msi001_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct msi001_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_dbg(&spi->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev->f_tuner = bands[0].rangelow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) v4l2_spi_subdev_init(&dev->sd, spi, &msi001_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Register controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) v4l2_ctrl_handler_init(&dev->hdl, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev->bandwidth_auto = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev->bandwidth = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) V4L2_CID_RF_TUNER_BANDWIDTH, 200000, 8000000, 1, 200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (dev->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = dev->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev_err(&spi->dev, "Could not initialize controls\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* control init failed, free handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) goto err_ctrl_handler_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) v4l2_ctrl_auto_cluster(2, &dev->bandwidth_auto, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev->lna_gain = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) V4L2_CID_RF_TUNER_LNA_GAIN, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dev->mixer_gain = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev->if_gain = v4l2_ctrl_new_std(&dev->hdl, &msi001_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) V4L2_CID_RF_TUNER_IF_GAIN, 0, 59, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (dev->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = dev->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_err(&spi->dev, "Could not initialize controls\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* control init failed, free handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) goto err_ctrl_handler_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev->sd.ctrl_handler = &dev->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) err_ctrl_handler_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) v4l2_ctrl_handler_free(&dev->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int msi001_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct v4l2_subdev *sd = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct msi001_dev *dev = sd_to_msi001_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_dbg(&spi->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * Registered by v4l2_spi_new_subdev() from master driver, but we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * unregister it from here. Weird.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) v4l2_device_unregister_subdev(&dev->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) v4l2_ctrl_handler_free(&dev->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const struct spi_device_id msi001_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {"msi001", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MODULE_DEVICE_TABLE(spi, msi001_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static struct spi_driver msi001_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .name = "msi001",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .probe = msi001_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .remove = msi001_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .id_table = msi001_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) module_spi_driver(msi001_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MODULE_DESCRIPTION("Mirics MSi001");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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