^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Freescale MC44S803 Low Power CMOS Broadband Tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2009 Jochen Friedrich <jochen@scram.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef MC44S803_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define MC44S803_PRIV_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* This driver is based on the information available in the datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) http://www.freescale.com/files/rf_if/doc/data_sheet/MC44S803.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) SPI or I2C Address : 0xc0-0xc6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Reg.No | Function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) -------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 00 | Power Down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 01 | Reference Oszillator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 02 | Reference Dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 03 | Mixer and Reference Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 04 | Reset/Serial Out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 05 | LO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 06 | LO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 07 | Circuit Adjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 08 | Test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 09 | Digital Tune
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 0A | LNA AGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 0B | Data Register Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 0C | Regulator Test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 0D | VCO Test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 0E | LNA Gain/Input Power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 0F | ID Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MC44S803_OSC 26000000 /* 26 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MC44S803_IF1 1086000000 /* 1086 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MC44S803_IF2 36125000 /* 36.125 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MC44S803_REG_POWER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MC44S803_REG_REFOSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MC44S803_REG_REFDIV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MC44S803_REG_MIXER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MC44S803_REG_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MC44S803_REG_LO1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MC44S803_REG_LO2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MC44S803_REG_CIRCADJ 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MC44S803_REG_TEST 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MC44S803_REG_DIGTUNE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MC44S803_REG_LNAAGC 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MC44S803_REG_DATAREG 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MC44S803_REG_REGTEST 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MC44S803_REG_VCOTEST 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MC44S803_REG_LNAGAIN 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MC44S803_REG_ID 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MC44S803_ADDR 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MC44S803_ADDR_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* REG_POWER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MC44S803_POWER 0xFFFFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MC44S803_POWER_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* REG_REFOSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MC44S803_REFOSC 0x1FF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MC44S803_REFOSC_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MC44S803_OSCSEL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MC44S803_OSCSEL_S 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* REG_REFDIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MC44S803_R2 0x1FF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MC44S803_R2_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MC44S803_REFBUF_EN 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MC44S803_REFBUF_EN_S 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MC44S803_R1 0x7C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MC44S803_R1_S 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* REG_MIXER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MC44S803_R3 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MC44S803_R3_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MC44S803_MUX3 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MC44S803_MUX3_S 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MC44S803_MUX4 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MC44S803_MUX4_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MC44S803_OSC_SCR 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MC44S803_OSC_SCR_S 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MC44S803_TRI_STATE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MC44S803_TRI_STATE_S 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MC44S803_BUF_GAIN 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MC44S803_BUF_GAIN_S 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MC44S803_BUF_IO 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MC44S803_BUF_IO_S 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MC44S803_MIXER_RES 0xFE000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MC44S803_MIXER_RES_S 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* REG_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MC44S803_RS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MC44S803_RS_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MC44S803_SO 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MC44S803_SO_S 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* REG_LO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MC44S803_LO1 0xFFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MC44S803_LO1_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* REG_LO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MC44S803_LO2 0x7FFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MC44S803_LO2_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* REG_CIRCADJ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MC44S803_G1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MC44S803_G1_S 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MC44S803_G3 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MC44S803_G3_S 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MC44S803_CIRCADJ_RES 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MC44S803_CIRCADJ_RES_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MC44S803_G6 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MC44S803_G6_S 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MC44S803_G7 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MC44S803_G7_S 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MC44S803_S1 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MC44S803_S1_S 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MC44S803_LP 0x7E000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MC44S803_LP_S 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MC44S803_CLRF 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MC44S803_CLRF_S 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MC44S803_CLIF 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MC44S803_CLIF_S 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* REG_TEST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* REG_DIGTUNE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MC44S803_DA 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MC44S803_DA_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MC44S803_XOD 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MC44S803_XOD_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MC44S803_RST 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MC44S803_RST_S 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MC44S803_LO_REF 0x1FFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MC44S803_LO_REF_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MC44S803_AT 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MC44S803_AT_S 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MC44S803_MT 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MC44S803_MT_S 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* REG_LNAAGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MC44S803_G 0x3F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MC44S803_G_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MC44S803_AT1 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MC44S803_AT1_S 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MC44S803_AT2 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MC44S803_AT2_S 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MC44S803_HL_GR_EN 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MC44S803_HL_GR_EN_S 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MC44S803_AGC_AN_DIG 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MC44S803_AGC_AN_DIG_S 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MC44S803_ATTEN_EN 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MC44S803_ATTEN_EN_S 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MC44S803_AGC_READ_EN 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MC44S803_AGC_READ_EN_S 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MC44S803_LNA0 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MC44S803_LNA0_S 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MC44S803_AGC_SEL 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MC44S803_AGC_SEL_S 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MC44S803_AT0 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MC44S803_AT0_S 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MC44S803_B 0xC00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MC44S803_B_S 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* REG_DATAREG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MC44S803_D 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MC44S803_D_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* REG_REGTEST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* REG_VCOTEST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* REG_LNAGAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MC44S803_IF_PWR 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MC44S803_IF_PWR_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MC44S803_RF_PWR 0x3800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MC44S803_RF_PWR_S 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MC44S803_LNA_GAIN 0xFC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MC44S803_LNA_GAIN_S 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* REG_ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MC44S803_ID 0x3E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MC44S803_ID_S 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Some macros to read/write fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* First shift, then mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MC44S803_REG_SM(_val, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) (((_val) << _reg##_S) & (_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* First mask, then shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MC44S803_REG_MS(_val, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) (((_val) & (_reg)) >> _reg##_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct mc44s803_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct mc44s803_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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