Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Driver for Freescale MC44S803 Low Power CMOS Broadband Tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (c) 2009 Jochen Friedrich <jochen@scram.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "mc44s803.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "mc44s803_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define mc_printk(level, format, arg...)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	printk(level "mc44s803: " format , ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* Writes a single register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static int mc44s803_writereg(struct mc44s803_priv *priv, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	buf[0] = (val & 0xff0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	buf[1] = (val & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	buf[2] = (val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		mc_printk(KERN_WARNING, "I2C write failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* Reads a single register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static int mc44s803_readreg(struct mc44s803_priv *priv, u8 reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u32 wval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		  .buf = buf, .len = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	wval = MC44S803_REG_SM(MC44S803_REG_DATAREG, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	       MC44S803_REG_SM(reg, MC44S803_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	ret = mc44s803_writereg(priv, wval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (i2c_transfer(priv->i2c, msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		mc_printk(KERN_WARNING, "I2C read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	*val = (buf[0] << 16) | (buf[1] << 8) | buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static void mc44s803_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct mc44s803_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int mc44s803_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct mc44s803_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* Reset chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	val = MC44S803_REG_SM(MC44S803_REG_RESET, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	      MC44S803_REG_SM(1, MC44S803_RS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	val = MC44S803_REG_SM(MC44S803_REG_RESET, MC44S803_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Power Up and Start Osc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	val = MC44S803_REG_SM(MC44S803_REG_REFOSC, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	      MC44S803_REG_SM(0xC0, MC44S803_REFOSC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	      MC44S803_REG_SM(1, MC44S803_OSCSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	val = MC44S803_REG_SM(MC44S803_REG_POWER, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	      MC44S803_REG_SM(0x200, MC44S803_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	val = MC44S803_REG_SM(MC44S803_REG_REFOSC, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	      MC44S803_REG_SM(0x40, MC44S803_REFOSC) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	      MC44S803_REG_SM(1, MC44S803_OSCSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Setup Mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	val = MC44S803_REG_SM(MC44S803_REG_MIXER, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	      MC44S803_REG_SM(1, MC44S803_TRI_STATE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	      MC44S803_REG_SM(0x7F, MC44S803_MIXER_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Setup Cirquit Adjust */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	val = MC44S803_REG_SM(MC44S803_REG_CIRCADJ, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	      MC44S803_REG_SM(1, MC44S803_G1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	      MC44S803_REG_SM(1, MC44S803_G3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	      MC44S803_REG_SM(0x3, MC44S803_CIRCADJ_RES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	      MC44S803_REG_SM(1, MC44S803_G6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	      MC44S803_REG_SM(priv->cfg->dig_out, MC44S803_S1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	      MC44S803_REG_SM(0x3, MC44S803_LP) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	      MC44S803_REG_SM(1, MC44S803_CLRF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	      MC44S803_REG_SM(1, MC44S803_CLIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	val = MC44S803_REG_SM(MC44S803_REG_CIRCADJ, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	      MC44S803_REG_SM(1, MC44S803_G1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	      MC44S803_REG_SM(1, MC44S803_G3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	      MC44S803_REG_SM(0x3, MC44S803_CIRCADJ_RES) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	      MC44S803_REG_SM(1, MC44S803_G6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	      MC44S803_REG_SM(priv->cfg->dig_out, MC44S803_S1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	      MC44S803_REG_SM(0x3, MC44S803_LP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Setup Digtune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	      MC44S803_REG_SM(3, MC44S803_XOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Setup AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	val = MC44S803_REG_SM(MC44S803_REG_LNAAGC, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	      MC44S803_REG_SM(1, MC44S803_AT1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	      MC44S803_REG_SM(1, MC44S803_AT2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	      MC44S803_REG_SM(1, MC44S803_AGC_AN_DIG) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	      MC44S803_REG_SM(1, MC44S803_AGC_READ_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	      MC44S803_REG_SM(1, MC44S803_LNA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	mc_printk(KERN_WARNING, "I/O Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int mc44s803_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct mc44s803_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u32 r1, r2, n1, n2, lo1, lo2, freq, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	priv->frequency = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	r1 = MC44S803_OSC / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	r2 = MC44S803_OSC /  100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	n1 = (c->frequency + MC44S803_IF1 + 500000) / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	freq = MC44S803_OSC / r1 * n1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	lo1 = ((60 * n1) + (r1 / 2)) / r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	freq = freq - c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	n2 = (freq - MC44S803_IF2 + 50000) / 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	lo2 = ((60 * n2) + (r2 / 2)) / r2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	val = MC44S803_REG_SM(MC44S803_REG_REFDIV, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	      MC44S803_REG_SM(r1-1, MC44S803_R1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	      MC44S803_REG_SM(r2-1, MC44S803_R2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	      MC44S803_REG_SM(1, MC44S803_REFBUF_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	val = MC44S803_REG_SM(MC44S803_REG_LO1, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	      MC44S803_REG_SM(n1-2, MC44S803_LO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	val = MC44S803_REG_SM(MC44S803_REG_LO2, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	      MC44S803_REG_SM(n2-2, MC44S803_LO2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	      MC44S803_REG_SM(1, MC44S803_DA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	      MC44S803_REG_SM(lo1, MC44S803_LO_REF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	      MC44S803_REG_SM(1, MC44S803_AT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	val = MC44S803_REG_SM(MC44S803_REG_DIGTUNE, MC44S803_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	      MC44S803_REG_SM(2, MC44S803_DA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	      MC44S803_REG_SM(lo2, MC44S803_LO_REF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	      MC44S803_REG_SM(1, MC44S803_AT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	err = mc44s803_writereg(priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	mc_printk(KERN_WARNING, "I/O Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int mc44s803_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct mc44s803_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	*frequency = priv->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int mc44s803_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	*frequency = MC44S803_IF2; /* 36.125 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct dvb_tuner_ops mc44s803_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.name              = "Freescale MC44S803",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.frequency_min_hz  =   48 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.frequency_max_hz  = 1000 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.frequency_step_hz =  100 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.release       = mc44s803_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.init          = mc44s803_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.set_params    = mc44s803_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.get_frequency = mc44s803_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.get_if_frequency = mc44s803_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* This functions tries to identify a MC44S803 tuner by reading the ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)    register. This is hasty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct dvb_frontend *mc44s803_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	 struct i2c_adapter *i2c, struct mc44s803_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct mc44s803_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	priv = kzalloc(sizeof(struct mc44s803_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	priv->cfg = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	priv->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	priv->fe  = fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	ret = mc44s803_readreg(priv, MC44S803_REG_ID, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	id = MC44S803_REG_MS(reg, MC44S803_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (id != 0x14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		mc_printk(KERN_ERR, "unsupported ID (%x should be 0x14)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			  id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	mc_printk(KERN_INFO, "successfully identified (ID = %x)\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	memcpy(&fe->ops.tuner_ops, &mc44s803_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	       sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) EXPORT_SYMBOL(mc44s803_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_AUTHOR("Jochen Friedrich");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_DESCRIPTION("Freescale MC44S803 silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_LICENSE("GPL");