Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  Driver for Maxim MAX2165 silicon tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (c) 2009 David T. L. Wong <davidtlwong@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __MAX2165_PRIV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __MAX2165_PRIV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define REG_NDIV_INT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define REG_NDIV_FRAC2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define REG_NDIV_FRAC1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define REG_NDIV_FRAC0 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define REG_TRACK_FILTER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define REG_LNA 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define REG_PLL_CFG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define REG_TEST 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define REG_SHUTDOWN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define REG_VCO_CTRL 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REG_BASEBAND_CTRL 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG_DC_OFFSET_CTRL 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_DC_OFFSET_DAC 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_ROM_TABLE_ADDR 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Read Only Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_ROM_TABLE_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_STATUS 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_AUTOTUNE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct max2165_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct max2165_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	struct i2c_adapter *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	u32 bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	u8 tf_ntch_low_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	u8 tf_ntch_hi_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	u8 tf_balun_low_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	u8 tf_balun_hi_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	u8 bb_filter_7mhz_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	u8 bb_filter_8mhz_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif