Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Driver for Maxim MAX2165 silicon tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (c) 2009 David T. L. Wong <davidtlwong@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "max2165.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "max2165_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "tuner-i2c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define dprintk(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 			printk(KERN_DEBUG "max2165: " args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int max2165_write_reg(struct max2165_priv *priv, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	msg.addr = priv->config->i2c_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	if (debug >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		dprintk("%s: reg=0x%02X, data=0x%02X\n", __func__, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	ret = i2c_transfer(priv->i2c, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			__func__, reg, data, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return (ret != 1) ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static int max2165_read_reg(struct max2165_priv *priv, u8 reg, u8 *p_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u8 dev_addr = priv->config->i2c_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u8 b0[] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u8 b1[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		{ .addr = dev_addr, .flags = 0, .buf = b0, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		{ .addr = dev_addr, .flags = I2C_M_RD, .buf = b1, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	ret = i2c_transfer(priv->i2c, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	if (ret != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	*p_data = b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (debug >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		dprintk("%s: reg=0x%02X, data=0x%02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			__func__, reg, b1[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int max2165_mask_write_reg(struct max2165_priv *priv, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u8 mask, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	data &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ret = max2165_read_reg(priv, reg, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	v &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	v |= data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ret = max2165_write_reg(priv, reg, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int max2165_read_rom_table(struct max2165_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u8 dat[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		max2165_write_reg(priv, REG_ROM_TABLE_ADDR, i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		max2165_read_reg(priv, REG_ROM_TABLE_DATA, &dat[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	priv->tf_ntch_low_cfg = dat[0] >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	priv->tf_ntch_hi_cfg = dat[0] & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	priv->tf_balun_low_ref = dat[1] & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	priv->tf_balun_hi_ref = dat[1] >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	priv->bb_filter_7mhz_cfg = dat[2] & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	priv->bb_filter_8mhz_cfg = dat[2] >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	dprintk("tf_ntch_low_cfg = 0x%X\n", priv->tf_ntch_low_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	dprintk("tf_ntch_hi_cfg = 0x%X\n", priv->tf_ntch_hi_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	dprintk("tf_balun_low_ref = 0x%X\n", priv->tf_balun_low_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	dprintk("tf_balun_hi_ref = 0x%X\n", priv->tf_balun_hi_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	dprintk("bb_filter_7mhz_cfg = 0x%X\n", priv->bb_filter_7mhz_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	dprintk("bb_filter_8mhz_cfg = 0x%X\n", priv->bb_filter_8mhz_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int max2165_set_osc(struct max2165_priv *priv, u8 osc /*MHz*/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	v = (osc / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (v == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		v = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		v -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	max2165_mask_write_reg(priv, REG_PLL_CFG, 0x07, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int max2165_set_bandwidth(struct max2165_priv *priv, u32 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (bw == 8000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		val = priv->bb_filter_8mhz_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		val = priv->bb_filter_7mhz_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	max2165_mask_write_reg(priv, REG_BASEBAND_CTRL, 0xF0, val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int fixpt_div32(u32 dividend, u32 divisor, u32 *quotient, u32 *fraction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u32 q, f = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (0 == divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	q = dividend / divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	remainder = dividend - q * divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	for (i = 0; i < 31; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		remainder <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		if (remainder >= divisor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			f += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			remainder -= divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		f <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	*quotient = q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	*fraction = f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int max2165_set_rf(struct max2165_priv *priv, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u8 tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u8 tf_ntch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32 quotient, fraction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* Set PLL divider according to RF frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ret = fixpt_div32(freq / 1000, priv->config->osc_clk * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			 &quotient, &fraction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* 20-bit fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	fraction >>= 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	max2165_write_reg(priv, REG_NDIV_INT, quotient);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	max2165_mask_write_reg(priv, REG_NDIV_FRAC2, 0x0F, fraction >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	max2165_write_reg(priv, REG_NDIV_FRAC1, fraction >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	max2165_write_reg(priv, REG_NDIV_FRAC0, fraction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/* Norch Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	tf_ntch = (freq < 725000000) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		priv->tf_ntch_low_cfg : priv->tf_ntch_hi_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* Tracking filter balun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	t = priv->tf_balun_low_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	t += (priv->tf_balun_hi_ref - priv->tf_balun_low_ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		* (freq / 1000 - 470000) / (780000 - 470000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	tf = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	dprintk("tf = %X\n", tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	tf |= tf_ntch << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	max2165_write_reg(priv, REG_TRACK_FILTER, tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void max2165_debug_status(struct max2165_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	u8 status, autotune;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	u8 auto_vco_success, auto_vco_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	u8 pll_locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u8 dc_offset_low, dc_offset_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u8 signal_lv_over_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	u8 vco, vco_sub_band, adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	max2165_read_reg(priv, REG_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	max2165_read_reg(priv, REG_AUTOTUNE, &autotune);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	auto_vco_success = (status >> 6) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	auto_vco_active = (status >> 5) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	pll_locked = (status >> 4) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	dc_offset_low = (status >> 3) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	dc_offset_hi = (status >> 2) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	signal_lv_over_threshold = status & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	vco = autotune >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	vco_sub_band = (autotune >> 3) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	adc = autotune & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	dprintk("auto VCO active: %d, auto VCO success: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		auto_vco_active, auto_vco_success);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	dprintk("PLL locked: %d\n", pll_locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	dprintk("DC offset low: %d, DC offset high: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		dc_offset_low, dc_offset_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	dprintk("Signal lvl over threshold: %d\n", signal_lv_over_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	dprintk("VCO: %d, VCO Sub-band: %d, ADC: %d\n", vco, vco_sub_band, adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int max2165_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct max2165_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	switch (c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		priv->frequency = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		printk(KERN_INFO "MAX2165: bandwidth %d Hz not supported.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		       c->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	dprintk("%s() frequency=%d\n", __func__, c->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	max2165_set_bandwidth(priv, c->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	ret = max2165_set_rf(priv, priv->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	mdelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	max2165_debug_status(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int max2165_get_frequency(struct dvb_frontend *fe, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	struct max2165_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	*freq = priv->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int max2165_get_bandwidth(struct dvb_frontend *fe, u32 *bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct max2165_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	*bw = priv->bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int max2165_get_status(struct dvb_frontend *fe, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct max2165_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	u16 lock_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	max2165_debug_status(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	*status = lock_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int max2165_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int max2165_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct max2165_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	/* Setup initial values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	/* Fractional Mode on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	max2165_write_reg(priv, REG_NDIV_FRAC2, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	/* LNA on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	max2165_write_reg(priv, REG_LNA, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	max2165_write_reg(priv, REG_PLL_CFG, 0x7A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	max2165_write_reg(priv, REG_TEST, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	max2165_write_reg(priv, REG_SHUTDOWN, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	max2165_write_reg(priv, REG_VCO_CTRL, 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	max2165_write_reg(priv, REG_BASEBAND_CTRL, 0xC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	max2165_write_reg(priv, REG_DC_OFFSET_CTRL, 0x75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	max2165_write_reg(priv, REG_DC_OFFSET_DAC, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	max2165_write_reg(priv, REG_ROM_TABLE_ADDR, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	max2165_set_osc(priv, priv->config->osc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	max2165_read_rom_table(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	max2165_set_bandwidth(priv, 8000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			fe->ops.i2c_gate_ctrl(fe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void max2165_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	struct max2165_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	dprintk("%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct dvb_tuner_ops max2165_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.name              = "Maxim MAX2165",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.frequency_min_hz  = 470 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		.frequency_max_hz  = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		.frequency_step_hz =  50 * kHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	.release	   = max2165_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	.init		   = max2165_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	.sleep		   = max2165_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	.set_params	   = max2165_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	.set_analog_params = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	.get_frequency	   = max2165_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	.get_bandwidth	   = max2165_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	.get_status	   = max2165_get_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct dvb_frontend *max2165_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 				   struct i2c_adapter *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 				   struct max2165_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	struct max2165_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	dprintk("%s(%d-%04x)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		i2c ? i2c_adapter_id(i2c) : -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		cfg ? cfg->i2c_address : -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	priv = kzalloc(sizeof(struct max2165_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	memcpy(&fe->ops.tuner_ops, &max2165_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	priv->config = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	priv->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	max2165_init(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	max2165_debug_status(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) EXPORT_SYMBOL(max2165_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MODULE_AUTHOR("David T. L. Wong <davidtlwong@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MODULE_DESCRIPTION("Maxim MAX2165 silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MODULE_LICENSE("GPL");