^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ITE IT913X silicon tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * IT9137 Copyright (C) ITE Tech Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "it913x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct it913x_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u8 chip_ver:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u8 role:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u16 xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 fdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u8 clk_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 fn_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) bool active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int it913x_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct it913x_dev *dev = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct platform_device *pdev = dev->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 iqik_m_cal, nv_val, buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const u8 nv[] = {48, 32, 24, 16, 12, 8, 6, 4, 2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) dev_dbg(&pdev->dev, "role %u\n", dev->role);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ret = regmap_write(dev->regmap, 0x80ec4c, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) usleep_range(10000, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ret = regmap_read(dev->regmap, 0x80ec86, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) switch (utmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* 12.000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) dev->clk_mode = utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) dev->xtal = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) dev->fdiv = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) iqik_m_cal = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* 20.480 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dev->clk_mode = utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dev->xtal = 640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev->fdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) iqik_m_cal = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dev_err(&pdev->dev, "unknown clock identifier %d\n", utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = regmap_read(dev->regmap, 0x80ed03, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) else if (utmp < ARRAY_SIZE(nv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) nv_val = nv[utmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) nv_val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TIMEOUT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) timeout = jiffies + msecs_to_jiffies(TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) while (!time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ret = regmap_bulk_read(dev->regmap, 0x80ed23, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) utmp = (buf[1] << 8) | (buf[0] << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (utmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_dbg(&pdev->dev, "r_fbc_m_bdry took %u ms, val %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) jiffies_to_msecs(jiffies) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) (jiffies_to_msecs(timeout) - TIMEOUT), utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev->fn_min = dev->xtal * utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev->fn_min /= (dev->fdiv * nv_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev->fn_min *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_dbg(&pdev->dev, "fn_min %u\n", dev->fn_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Chip version BX never sets that flag so we just wait 50ms in that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * case. It is possible poll BX similarly than AX and then timeout in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * order to get 50ms delay, but that causes about 120 extra I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * messages. As for now, we just wait and reduce IO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (dev->chip_ver == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TIMEOUT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) timeout = jiffies + msecs_to_jiffies(TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) while (!time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = regmap_read(dev->regmap, 0x80ec82, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (utmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_dbg(&pdev->dev, "p_tsm_init_mode took %u ms, val %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) jiffies_to_msecs(jiffies) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) (jiffies_to_msecs(timeout) - TIMEOUT), utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = regmap_write(dev->regmap, 0x80ed81, iqik_m_cal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = regmap_write(dev->regmap, 0x80ec57, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = regmap_write(dev->regmap, 0x80ec58, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = regmap_write(dev->regmap, 0x80ec40, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev->active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_dbg(&pdev->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int it913x_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct it913x_dev *dev = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct platform_device *pdev = dev->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int ret, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_dbg(&pdev->dev, "role %u\n", dev->role);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev->active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = regmap_bulk_write(dev->regmap, 0x80ec40, "\x00", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Writing '0x00' to master tuner register '0x80ec08' causes slave tuner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * communication lost. Due to that, we cannot put master full sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (dev->role == IT913X_ROLE_DUAL_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) len = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_dbg(&pdev->dev, "role %u, len %d\n", dev->role, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = regmap_bulk_write(dev->regmap, 0x80ec02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "\x3f\x1f\x3f\x3e\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = regmap_bulk_write(dev->regmap, 0x80ec12, "\x00\x00\x00\x00", 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = regmap_bulk_write(dev->regmap, 0x80ec17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "\x00\x00\x00\x00\x00\x00\x00\x00\x00", 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = regmap_bulk_write(dev->regmap, 0x80ec22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = regmap_bulk_write(dev->regmap, 0x80ec20, "\x00", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = regmap_bulk_write(dev->regmap, 0x80ec3f, "\x01", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_dbg(&pdev->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int it913x_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct it913x_dev *dev = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct platform_device *pdev = dev->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int utmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 pre_lo_freq, t_cal_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u16 iqik_m_cal, n_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 u8tmp, n, l_band, lna_band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dev_dbg(&pdev->dev, "role=%u, frequency %u, bandwidth_hz %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev->role, c->frequency, c->bandwidth_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!dev->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (c->frequency <= 74000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) n_div = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } else if (c->frequency <= 111000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) n_div = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) n = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } else if (c->frequency <= 148000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) n_div = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) n = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else if (c->frequency <= 222000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) n_div = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) n = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) } else if (c->frequency <= 296000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) n_div = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) n = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } else if (c->frequency <= 445000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) n_div = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) n = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) } else if (c->frequency <= dev->fn_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) n_div = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) n = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) } else if (c->frequency <= 950000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) n_div = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) n = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) n_div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = regmap_read(dev->regmap, 0x80ed81, &utmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) iqik_m_cal = utmp * n_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (utmp < 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (dev->clk_mode == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) iqik_m_cal = (iqik_m_cal * 9) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) iqik_m_cal >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) iqik_m_cal = 0x40 - iqik_m_cal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (dev->clk_mode == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) iqik_m_cal = ~((iqik_m_cal * 9) >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) iqik_m_cal = ~(iqik_m_cal >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) t_cal_freq = (c->frequency / 1000) * n_div * dev->fdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pre_lo_freq = t_cal_freq / dev->xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) utmp = pre_lo_freq * dev->xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if ((t_cal_freq - utmp) >= (dev->xtal >> 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pre_lo_freq++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pre_lo_freq += (u32) n << 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Frequency OMEGA_IQIK_M_CAL_MID*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) t_cal_freq = pre_lo_freq + (u32)iqik_m_cal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_dbg(&pdev->dev, "t_cal_freq %u, pre_lo_freq %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) t_cal_freq, pre_lo_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (c->frequency <= 440000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) l_band = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) lna_band = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } else if (c->frequency <= 484000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) l_band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) lna_band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) } else if (c->frequency <= 533000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) l_band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) lna_band = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else if (c->frequency <= 587000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) l_band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) lna_band = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } else if (c->frequency <= 645000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) l_band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) lna_band = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } else if (c->frequency <= 710000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) l_band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) lna_band = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) } else if (c->frequency <= 782000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) l_band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) lna_band = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } else if (c->frequency <= 860000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) l_band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) lna_band = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } else if (c->frequency <= 1492000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) l_band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) lna_band = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } else if (c->frequency <= 1685000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) l_band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) lna_band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* XXX: latest windows driver does not set that at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = regmap_write(dev->regmap, 0x80ee06, lna_band);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (c->bandwidth_hz <= 5000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) else if (c->bandwidth_hz <= 6000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8tmp = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) else if (c->bandwidth_hz <= 7000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u8tmp = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u8tmp = 6; /* 8000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = regmap_write(dev->regmap, 0x80ec56, u8tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* XXX: latest windows driver sets different value (a8 != 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = regmap_write(dev->regmap, 0x80ec4c, 0xa0 | (l_band << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = regmap_write(dev->regmap, 0x80ec4d, (t_cal_freq >> 0) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = regmap_write(dev->regmap, 0x80ec4e, (t_cal_freq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = regmap_write(dev->regmap, 0x80011e, (pre_lo_freq >> 0) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = regmap_write(dev->regmap, 0x80011f, (pre_lo_freq >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_dbg(&pdev->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct dvb_tuner_ops it913x_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .name = "ITE IT913X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .frequency_min_hz = 174 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .frequency_max_hz = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .init = it913x_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .sleep = it913x_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .set_params = it913x_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int it913x_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct it913x_platform_data *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct dvb_frontend *fe = pdata->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct it913x_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) const struct platform_device_id *id = platform_get_device_id(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) char *chip_ver_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev = kzalloc(sizeof(struct it913x_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(&pdev->dev, "kzalloc() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev->regmap = pdata->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev->fe = pdata->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev->chip_ver = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev->role = pdata->role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) fe->tuner_priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) memcpy(&fe->ops.tuner_ops, &it913x_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (dev->chip_ver == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) chip_ver_str = "AX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) else if (dev->chip_ver == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) chip_ver_str = "BX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) chip_ver_str = "??";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_info(&pdev->dev, "ITE IT913X %s successfully attached\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) chip_ver_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_dbg(&pdev->dev, "chip_ver %u, role %u\n", dev->chip_ver, dev->role);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_dbg(&pdev->dev, "failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int it913x_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct it913x_dev *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct dvb_frontend *fe = dev->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_dbg(&pdev->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct platform_device_id it913x_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {"it9133ax-tuner", 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {"it9133bx-tuner", 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MODULE_DEVICE_TABLE(platform, it913x_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static struct platform_driver it913x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .name = "it913x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .probe = it913x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .remove = it913x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .id_table = it913x_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) module_platform_driver(it913x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_DESCRIPTION("ITE IT913X silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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