^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * FCI FC2580 silicon tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "fc2580_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * I2C write and read works only for one single register. Multiple registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * could not be accessed using normal register address auto-increment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * There could be (very likely) register to change that behavior....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* write single register conditionally only when value differs from 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * XXX: This is special routine meant only for writing fc2580_freq_regs_lut[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * values. Do not use for the other purposes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static int fc2580_wr_reg_ff(struct fc2580_dev *dev, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) if (val == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return regmap_write(dev->regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int fc2580_set_params(struct fc2580_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int uitmp, div_ref, div_ref_val, div_n, k, k_cw, div_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u64 f_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 synth_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (!dev->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) dev_dbg(&client->dev, "tuner is sleeping\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Fractional-N synthesizer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * +---------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * v |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Fref +----+ +----+ +-------+ +----+ +------+ +---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * ------> | /R | --> | PD | --> | VCO | ------> | /2 | --> | /N.F | <-- | K |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * +----+ +----+ +-------+ +----+ +------+ +---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * +-------+ Fout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * | /Rout | ------>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * +-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) for (i = 0; i < ARRAY_SIZE(fc2580_pll_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (dev->f_frequency <= fc2580_pll_lut[i].freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (i == ARRAY_SIZE(fc2580_pll_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DIV_PRE_N 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define F_REF dev->clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) div_out = fc2580_pll_lut[i].div_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) f_vco = (u64) dev->f_frequency * div_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) synth_config = fc2580_pll_lut[i].band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (f_vco < 2600000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) synth_config |= 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) synth_config |= 0x0e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* select reference divider R (keep PLL div N in valid range) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DIV_N_MIN 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (f_vco >= div_u64((u64) DIV_PRE_N * DIV_N_MIN * F_REF, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) div_ref = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) div_ref_val = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } else if (f_vco >= div_u64((u64) DIV_PRE_N * DIV_N_MIN * F_REF, 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) div_ref = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) div_ref_val = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) div_ref = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) div_ref_val = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* calculate PLL integer and fractional control word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) uitmp = DIV_PRE_N * F_REF / div_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) div_n = div_u64_rem(f_vco, uitmp, &k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) k_cw = div_u64((u64) k * 0x100000, uitmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "frequency=%u bandwidth=%u f_vco=%llu F_REF=%u div_ref=%u div_n=%u k=%u div_out=%u k_cw=%0x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev->f_frequency, dev->f_bandwidth, f_vco, F_REF, div_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) div_n, k, div_out, k_cw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = regmap_write(dev->regmap, 0x02, synth_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = regmap_write(dev->regmap, 0x18, div_ref_val << 0 | k_cw >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = regmap_write(dev->regmap, 0x1a, (k_cw >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = regmap_write(dev->regmap, 0x1b, (k_cw >> 0) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = regmap_write(dev->regmap, 0x1c, div_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) for (i = 0; i < ARRAY_SIZE(fc2580_freq_regs_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (dev->f_frequency <= fc2580_freq_regs_lut[i].freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (i == ARRAY_SIZE(fc2580_freq_regs_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = fc2580_wr_reg_ff(dev, 0x25, fc2580_freq_regs_lut[i].r25_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ret = fc2580_wr_reg_ff(dev, 0x27, fc2580_freq_regs_lut[i].r27_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = fc2580_wr_reg_ff(dev, 0x28, fc2580_freq_regs_lut[i].r28_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret = fc2580_wr_reg_ff(dev, 0x29, fc2580_freq_regs_lut[i].r29_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = fc2580_wr_reg_ff(dev, 0x2b, fc2580_freq_regs_lut[i].r2b_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = fc2580_wr_reg_ff(dev, 0x2c, fc2580_freq_regs_lut[i].r2c_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = fc2580_wr_reg_ff(dev, 0x2d, fc2580_freq_regs_lut[i].r2d_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = fc2580_wr_reg_ff(dev, 0x30, fc2580_freq_regs_lut[i].r30_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = fc2580_wr_reg_ff(dev, 0x44, fc2580_freq_regs_lut[i].r44_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = fc2580_wr_reg_ff(dev, 0x50, fc2580_freq_regs_lut[i].r50_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = fc2580_wr_reg_ff(dev, 0x53, fc2580_freq_regs_lut[i].r53_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = fc2580_wr_reg_ff(dev, 0x5f, fc2580_freq_regs_lut[i].r5f_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = fc2580_wr_reg_ff(dev, 0x61, fc2580_freq_regs_lut[i].r61_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = fc2580_wr_reg_ff(dev, 0x62, fc2580_freq_regs_lut[i].r62_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = fc2580_wr_reg_ff(dev, 0x63, fc2580_freq_regs_lut[i].r63_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = fc2580_wr_reg_ff(dev, 0x67, fc2580_freq_regs_lut[i].r67_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = fc2580_wr_reg_ff(dev, 0x68, fc2580_freq_regs_lut[i].r68_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = fc2580_wr_reg_ff(dev, 0x69, fc2580_freq_regs_lut[i].r69_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = fc2580_wr_reg_ff(dev, 0x6a, fc2580_freq_regs_lut[i].r6a_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = fc2580_wr_reg_ff(dev, 0x6b, fc2580_freq_regs_lut[i].r6b_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret = fc2580_wr_reg_ff(dev, 0x6c, fc2580_freq_regs_lut[i].r6c_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = fc2580_wr_reg_ff(dev, 0x6d, fc2580_freq_regs_lut[i].r6d_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ret = fc2580_wr_reg_ff(dev, 0x6e, fc2580_freq_regs_lut[i].r6e_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = fc2580_wr_reg_ff(dev, 0x6f, fc2580_freq_regs_lut[i].r6f_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* IF filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) for (i = 0; i < ARRAY_SIZE(fc2580_if_filter_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (dev->f_bandwidth <= fc2580_if_filter_lut[i].freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (i == ARRAY_SIZE(fc2580_if_filter_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = regmap_write(dev->regmap, 0x36, fc2580_if_filter_lut[i].r36_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) uitmp = (unsigned int) 8058000 - (dev->f_bandwidth * 122 / 100 / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) uitmp = div64_u64((u64) dev->clk * uitmp, 1000000000000ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = regmap_write(dev->regmap, 0x37, uitmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = regmap_write(dev->regmap, 0x39, fc2580_if_filter_lut[i].r39_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) timeout = jiffies + msecs_to_jiffies(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) for (uitmp = ~0xc0; !time_after(jiffies, timeout) && uitmp != 0xc0;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* trigger filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = regmap_write(dev->regmap, 0x2e, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* locked when [7:6] are set (val: d7 6MHz, d5 7MHz, cd 8MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = regmap_read(dev->regmap, 0x2f, &uitmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) uitmp &= 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = regmap_write(dev->regmap, 0x2e, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (uitmp != 0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_dbg(&client->dev, "filter did not lock %02x\n", uitmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int fc2580_init(struct fc2580_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) for (i = 0; i < ARRAY_SIZE(fc2580_init_reg_vals); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = regmap_write(dev->regmap, fc2580_init_reg_vals[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) fc2580_init_reg_vals[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev->active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int fc2580_sleep(struct fc2580_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev->active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = regmap_write(dev->regmap, 0x02, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * DVB API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int fc2580_dvb_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct fc2580_dev *dev = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev->f_frequency = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev->f_bandwidth = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return fc2580_set_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int fc2580_dvb_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return fc2580_init(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int fc2580_dvb_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return fc2580_sleep(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int fc2580_dvb_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *frequency = 0; /* Zero-IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const struct dvb_tuner_ops fc2580_dvb_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .name = "FCI FC2580",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .frequency_min_hz = 174 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .frequency_max_hz = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .init = fc2580_dvb_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .sleep = fc2580_dvb_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .set_params = fc2580_dvb_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .get_if_frequency = fc2580_dvb_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * V4L2 API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #if IS_ENABLED(CONFIG_VIDEO_V4L2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct v4l2_frequency_band bands[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .type = V4L2_TUNER_RF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .rangelow = 130000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .rangehigh = 2000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static inline struct fc2580_dev *fc2580_subdev_to_dev(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return container_of(sd, struct fc2580_dev, subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int fc2580_standby(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct fc2580_dev *dev = fc2580_subdev_to_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = fc2580_sleep(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return fc2580_set_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int fc2580_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct fc2580_dev *dev = fc2580_subdev_to_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_dbg(&client->dev, "index=%d\n", v->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) strscpy(v->name, "FCI FC2580", sizeof(v->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) v->type = V4L2_TUNER_RF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) v->rangelow = bands[0].rangelow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) v->rangehigh = bands[0].rangehigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int fc2580_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct fc2580_dev *dev = fc2580_subdev_to_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_dbg(&client->dev, "index=%d\n", v->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int fc2580_g_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct fc2580_dev *dev = fc2580_subdev_to_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_dbg(&client->dev, "tuner=%d\n", f->tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) f->frequency = dev->f_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int fc2580_s_frequency(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) const struct v4l2_frequency *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct fc2580_dev *dev = fc2580_subdev_to_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_dbg(&client->dev, "tuner=%d type=%d frequency=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) f->tuner, f->type, f->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev->f_frequency = clamp_t(unsigned int, f->frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) bands[0].rangelow, bands[0].rangehigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return fc2580_set_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int fc2580_enum_freq_bands(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct v4l2_frequency_band *band)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct fc2580_dev *dev = fc2580_subdev_to_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_dbg(&client->dev, "tuner=%d type=%d index=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) band->tuner, band->type, band->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (band->index >= ARRAY_SIZE(bands))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) band->capability = bands[band->index].capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) band->rangelow = bands[band->index].rangelow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) band->rangehigh = bands[band->index].rangehigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct v4l2_subdev_tuner_ops fc2580_subdev_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .standby = fc2580_standby,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .g_tuner = fc2580_g_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .s_tuner = fc2580_s_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .g_frequency = fc2580_g_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .s_frequency = fc2580_s_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .enum_freq_bands = fc2580_enum_freq_bands,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct v4l2_subdev_ops fc2580_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .tuner = &fc2580_subdev_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int fc2580_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct fc2580_dev *dev = container_of(ctrl->handler, struct fc2580_dev, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_dbg(&client->dev, "ctrl: id=%d name=%s cur.val=%d val=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ctrl->id, ctrl->name, ctrl->cur.val, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case V4L2_CID_RF_TUNER_BANDWIDTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * TODO: Auto logic does not work 100% correctly as tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * do not have information to calculate maximum suitable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * bandwidth. Calculating it is responsible of master driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev->f_bandwidth = dev->bandwidth->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = fc2580_set_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_dbg(&client->dev, "unknown ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct v4l2_ctrl_ops fc2580_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .s_ctrl = fc2580_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct v4l2_subdev *fc2580_get_v4l2_subdev(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct fc2580_dev *dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (dev->subdev.ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return &dev->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int fc2580_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct fc2580_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct fc2580_platform_data *pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct dvb_frontend *fe = pdata->dvb_frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) unsigned int uitmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct regmap_config regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (pdata->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev->clk = pdata->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev->clk = 16384000; /* internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev->regmap = devm_regmap_init_i2c(client, ®map_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (IS_ERR(dev->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = PTR_ERR(dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* check if the tuner is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = regmap_read(dev->regmap, 0x01, &uitmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_dbg(&client->dev, "chip_id=%02x\n", uitmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) switch (uitmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case 0x56:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) case 0x5a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #if IS_ENABLED(CONFIG_VIDEO_V4L2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Register controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) v4l2_ctrl_handler_init(&dev->hdl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev->bandwidth_auto = v4l2_ctrl_new_std(&dev->hdl, &fc2580_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) V4L2_CID_RF_TUNER_BANDWIDTH_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev->bandwidth = v4l2_ctrl_new_std(&dev->hdl, &fc2580_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) V4L2_CID_RF_TUNER_BANDWIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 3000, 10000000, 1, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) v4l2_ctrl_auto_cluster(2, &dev->bandwidth_auto, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (dev->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = dev->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_err(&client->dev, "Could not initialize controls\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) v4l2_ctrl_handler_free(&dev->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev->subdev.ctrl_handler = &dev->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev->f_frequency = bands[0].rangelow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev->f_bandwidth = dev->bandwidth->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) v4l2_i2c_subdev_init(&dev->subdev, client, &fc2580_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) fe->tuner_priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) memcpy(&fe->ops.tuner_ops, &fc2580_dvb_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) sizeof(fe->ops.tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pdata->get_v4l2_subdev = fc2580_get_v4l2_subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) i2c_set_clientdata(client, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev_info(&client->dev, "FCI FC2580 successfully identified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) err_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int fc2580_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct fc2580_dev *dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #if IS_ENABLED(CONFIG_VIDEO_V4L2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) v4l2_ctrl_handler_free(&dev->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static const struct i2c_device_id fc2580_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {"fc2580", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MODULE_DEVICE_TABLE(i2c, fc2580_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static struct i2c_driver fc2580_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .name = "fc2580",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .probe = fc2580_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .remove = fc2580_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .id_table = fc2580_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) module_i2c_driver(fc2580_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) MODULE_DESCRIPTION("FCI FC2580 silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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